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https://github.com/RPCS3/llvm-mirror.git
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0ae26fb715
Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
265 lines
7.1 KiB
LLVM
265 lines
7.1 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mcpu=generic %s -o /dev/null
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv6t2-none-eabi %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv6-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV6
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define i32 @f1(i16 %x, i32 %y) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: sxth
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; CHECK: {{smulbt r0, r0, r1|smultb r0, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smulbt|smultb}}
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%tmp1 = sext i16 %x to i32
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%tmp2 = ashr i32 %y, 16
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%tmp3 = mul i32 %tmp2, %tmp1
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ret i32 %tmp3
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}
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define i32 @f2(i32 %x, i32 %y) {
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; CHECK-LABEL: f2:
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; CHECK: smultt
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; CHECK-THUMBV6-NOT: smultt
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%tmp1 = ashr i32 %x, 16
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%tmp3 = ashr i32 %y, 16
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%tmp4 = mul i32 %tmp3, %tmp1
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ret i32 %tmp4
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}
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define i32 @f3(i32 %a, i16 %x, i32 %y) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: sxth
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; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smlabt|smlatb}}
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%tmp = sext i16 %x to i32
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%tmp2 = ashr i32 %y, 16
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%tmp3 = mul i32 %tmp2, %tmp
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%tmp5 = add i32 %tmp3, %a
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ret i32 %tmp5
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}
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define i32 @f4(i32 %a, i32 %x, i32 %y) {
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; CHECK-LABEL: f4:
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; CHECK: smlatt
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; CHECK-THUMBV6-NOT: smlatt
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%tmp1 = ashr i32 %x, 16
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%tmp3 = ashr i32 %y, 16
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%tmp4 = mul i32 %tmp3, %tmp1
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%tmp5 = add i32 %tmp4, %a
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ret i32 %tmp5
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}
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define i32 @f5(i32 %a, i16 %x, i16 %y) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: sxth
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; CHECK: smlabb
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; CHECK-THUMBV6-NOT: smlabb
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%tmp1 = sext i16 %x to i32
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%tmp3 = sext i16 %y to i32
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%tmp4 = mul i32 %tmp3, %tmp1
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%tmp5 = add i32 %tmp4, %a
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ret i32 %tmp5
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}
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define i32 @f6(i32 %a, i32 %x, i16 %y) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: sxth
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; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smlatb|smlabt}}
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%tmp1 = sext i16 %y to i32
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%tmp2 = ashr i32 %x, 16
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%tmp3 = mul i32 %tmp2, %tmp1
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%tmp5 = add i32 %tmp3, %a
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ret i32 %tmp5
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}
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define i32 @f7(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: f7:
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; CHECK: smlawb r0, r0, r1, r2
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; CHECK-THUMBV6-NOT: smlawb
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%shl = shl i32 %b, 16
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%shr = ashr exact i32 %shl, 16
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%conv = sext i32 %a to i64
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%conv2 = sext i32 %shr to i64
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%mul = mul nsw i64 %conv2, %conv
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%shr49 = lshr i64 %mul, 16
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%conv5 = trunc i64 %shr49 to i32
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%add = add nsw i32 %conv5, %c
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ret i32 %add
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}
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define i32 @f8(i32 %a, i16 signext %b, i32 %c) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: sxth
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; CHECK: smlawb r0, r0, r1, r2
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; CHECK-THUMBV6-NOT: smlawb
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%conv = sext i32 %a to i64
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%conv1 = sext i16 %b to i64
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%mul = mul nsw i64 %conv1, %conv
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%shr5 = lshr i64 %mul, 16
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%conv2 = trunc i64 %shr5 to i32
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%add = add nsw i32 %conv2, %c
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ret i32 %add
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}
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define i32 @f9(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: f9:
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; CHECK: smlawt r0, r0, r1, r2
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; CHECK-THUMBV6-NOT: smlawt
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%conv = sext i32 %a to i64
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%shr = ashr i32 %b, 16
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%conv1 = sext i32 %shr to i64
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%mul = mul nsw i64 %conv1, %conv
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%shr26 = lshr i64 %mul, 16
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%conv3 = trunc i64 %shr26 to i32
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%add = add nsw i32 %conv3, %c
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ret i32 %add
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}
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: smulwb r0, r0, r1
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; CHECK-THUMBV6-NOT: smulwb
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%shl = shl i32 %b, 16
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%shr = ashr exact i32 %shl, 16
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%conv = sext i32 %a to i64
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%conv2 = sext i32 %shr to i64
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%mul = mul nsw i64 %conv2, %conv
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%shr37 = lshr i64 %mul, 16
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%conv4 = trunc i64 %shr37 to i32
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ret i32 %conv4
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}
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define i32 @f11(i32 %a, i16 signext %b) {
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; CHECK-LABEL: f11:
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; CHECK-NOT: sxth
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; CHECK: smulwb r0, r0, r1
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; CHECK-THUMBV6-NOT: smulwb
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%conv = sext i32 %a to i64
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%conv1 = sext i16 %b to i64
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%mul = mul nsw i64 %conv1, %conv
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%shr4 = lshr i64 %mul, 16
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%conv2 = trunc i64 %shr4 to i32
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ret i32 %conv2
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}
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define i32 @f12(i32 %a, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: smulwt r0, r0, r1
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; CHECK-THUMBV6-NOT: smulwt
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%conv = sext i32 %a to i64
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%shr = ashr i32 %b, 16
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%conv1 = sext i32 %shr to i64
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%mul = mul nsw i64 %conv1, %conv
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%shr25 = lshr i64 %mul, 16
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%conv3 = trunc i64 %shr25 to i32
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ret i32 %conv3
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}
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define i32 @f13(i32 %x, i16 %y) {
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; CHECK-LABEL: f13:
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; CHECK-NOT: sxth
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; CHECK: {{smultb r0, r0, r1|smulbt r0, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smultb|smulbt}}
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%tmp1 = sext i16 %y to i32
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%tmp2 = ashr i32 %x, 16
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%tmp3 = mul i32 %tmp2, %tmp1
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ret i32 %tmp3
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}
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define i32 @f14(i32 %x, i32 %y) {
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; CHECK-LABEL: f14:
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; CHECK-NOT: sxth
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; CHECK: {{smultb r0, r0, r1|smulbt r0, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smultb|smulbt}}
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%tmp1 = shl i32 %y, 16
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%tmp2 = ashr i32 %tmp1, 16
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%tmp3 = ashr i32 %x, 16
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%tmp4 = mul i32 %tmp3, %tmp2
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ret i32 %tmp4
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}
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define i32 @f15(i32 %x, i32 %y) {
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; CHECK-LABEL: f15:
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; CHECK-NOT: sxth
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; CHECK: {{smulbt r0, r0, r1|smultb r0, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smulbt|smultb}}
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%tmp1 = shl i32 %x, 16
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%tmp2 = ashr i32 %tmp1, 16
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%tmp3 = ashr i32 %y, 16
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%tmp4 = mul i32 %tmp2, %tmp3
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ret i32 %tmp4
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}
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define i32 @f16(i16 %x, i16 %y) {
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; CHECK-LABEL: f16:
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; CHECK-NOT: sxth
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; CHECK: smulbb
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; CHECK-THUMBV6-NOT: smulbb
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%tmp1 = sext i16 %x to i32
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%tmp2 = sext i16 %x to i32
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%tmp3 = mul i32 %tmp1, %tmp2
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ret i32 %tmp3
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}
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define i32 @f17(i32 %x, i32 %y) {
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; CHECK-LABEL: f17:
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; CHECK: smulbb
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; CHECK-THUMBV6-NOT: smulbb
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%tmp1 = shl i32 %x, 16
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%tmp2 = shl i32 %y, 16
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%tmp3 = ashr i32 %tmp1, 16
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%tmp4 = ashr i32 %tmp2, 16
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%tmp5 = mul i32 %tmp3, %tmp4
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ret i32 %tmp5
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}
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define i32 @f18(i32 %a, i32 %x, i32 %y) {
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; CHECK-LABEL: f18:
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; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smlabt|smlatb}}
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%tmp0 = shl i32 %x, 16
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%tmp1 = ashr i32 %tmp0, 16
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%tmp2 = ashr i32 %y, 16
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%tmp3 = mul i32 %tmp2, %tmp1
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%tmp5 = add i32 %tmp3, %a
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ret i32 %tmp5
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}
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define i32 @f19(i32 %a, i32 %x, i32 %y) {
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; CHECK-LABEL: f19:
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; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}}
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; CHECK-THUMBV6-NOT: {{smlatb|smlabt}}
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%tmp0 = shl i32 %y, 16
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%tmp1 = ashr i32 %tmp0, 16
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%tmp2 = ashr i32 %x, 16
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%tmp3 = mul i32 %tmp2, %tmp1
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%tmp5 = add i32 %tmp3, %a
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ret i32 %tmp5
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}
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define i32 @f20(i32 %a, i32 %x, i32 %y) {
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; CHECK-LABEL: f20:
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; CHECK: smlabb
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; CHECK-THUMBV6-NOT: smlabb
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%tmp1 = shl i32 %x, 16
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%tmp2 = ashr i32 %tmp1, 16
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%tmp3 = shl i32 %y, 16
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%tmp4 = ashr i32 %tmp3, 16
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%tmp5 = mul i32 %tmp2, %tmp4
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%tmp6 = add i32 %tmp5, %a
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ret i32 %tmp6
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}
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define i32 @f21(i32 %a, i32 %x, i16 %y) {
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; CHECK-LABEL: f21
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; CHECK-NOT: sxth
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; CHECK: smlabb
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; CHECK-THUMBV6-NOT: smlabb
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%tmp1 = shl i32 %x, 16
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%tmp2 = ashr i32 %tmp1, 16
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%tmp3 = sext i16 %y to i32
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%tmp4 = mul i32 %tmp2, %tmp3
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%tmp5 = add i32 %a, %tmp4
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ret i32 %tmp5
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}
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