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49546d6e72
Note that cyclone itself doesn't fuse, but newer apple chips do and we are using cyclone as the default when targeting apple OSes. The current code also does not capture all fusion patterns of apple CPUs yet; I am still looking for ways to refactor the code nicely to extend it. llvm-svn: 316036
500 lines
23 KiB
TableGen
500 lines
23 KiB
TableGen
//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing.
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Subtarget features.
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//
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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"Enable ARMv8 FP">;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable cryptographic instructions", [FeatureNEON]>;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable ARMv8 CRC-32 checksum instructions">;
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
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def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
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"Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
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def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
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"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable ARMv8 PMUv3 Performance Monitors extension">;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Full FP16", [FeatureFPARMv8]>;
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def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
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"Enable Statistical Profiling extension">;
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def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
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"Enable Scalable Vector Extension (SVE) instructions">;
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/// Cyclone has register move instructions which are "free".
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zero-cycle register moves">;
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/// Cyclone has instructions which zero registers for "free".
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
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"Reserve X18, making it unavailable "
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"as a GPR">;
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def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
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"Use alias analysis during codegen">;
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def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
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"true",
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"balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
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def FeaturePredictableSelectIsExpensive : SubtargetFeature<
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"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
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"Prefer likely predicted branches over selects">;
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def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
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"CustomAsCheapAsMove", "true",
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"Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
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def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
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"UsePostRAScheduler", "true", "Schedule again after register allocation">;
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def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
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"Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
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def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
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"Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
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def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
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"true", "STR of Q register with register offset is slow">;
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def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
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"alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
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"true", "Use alternative pattern for sextload convert to f32">;
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def FeatureArithmeticBccFusion : SubtargetFeature<
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"arith-bcc-fusion", "HasArithmeticBccFusion", "true",
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"CPU fuses arithmetic+bcc operations">;
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def FeatureArithmeticCbzFusion : SubtargetFeature<
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"arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
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"CPU fuses arithmetic + cbz/cbnz operations">;
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def FeatureFuseAES : SubtargetFeature<
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"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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def FeatureFuseLiterals : SubtargetFeature<
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"fuse-literals", "HasFuseLiterals", "true",
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"CPU fuses literal generation operations">;
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def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
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"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
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"Disable latency scheduling heuristic">;
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def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
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"Enable support for RCPC extension">;
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def FeatureUseRSqrt : SubtargetFeature<
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"use-reciprocal-square-root", "UseRSqrt", "true",
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"Use the reciprocal square root approximation">;
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def FeatureDotProd : SubtargetFeature<
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"dotprod", "HasDotProd", "true",
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"Enable dot product support">;
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def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
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"NegativeImmediates", "false",
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"Convert immediates and instructions "
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"to their negated or complemented "
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"equivalent when the immediate does "
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"not fit in the encoding.">;
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def FeatureLSLFast : SubtargetFeature<
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"lsl-fast", "HasLSLFast", "true",
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"CPU has a fastpath logical shift of up to 3 places">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
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def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
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"Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
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def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
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"Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AArch64RegisterInfo.td"
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include "AArch64RegisterBanks.td"
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include "AArch64CallingConvention.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AArch64Schedule.td"
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include "AArch64InstrInfo.td"
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def AArch64InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Named operands for MRS/MSR/TLBI/...
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//===----------------------------------------------------------------------===//
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include "AArch64SystemOperands.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Processors supported.
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//
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include "AArch64SchedA53.td"
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include "AArch64SchedA57.td"
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include "AArch64SchedCyclone.td"
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include "AArch64SchedFalkor.td"
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include "AArch64SchedKryo.td"
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include "AArch64SchedM1.td"
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include "AArch64SchedThunderX.td"
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include "AArch64SchedThunderX2T99.td"
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def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
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"Cortex-A35 ARM processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors", [
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FeatureBalanceFPOps,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureUseAA
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]>;
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def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
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"Cortex-A55 ARM processors", [
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HasV8_2aOps,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeatureFullFP16,
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FeatureDotProd,
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FeatureRCPC,
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FeaturePerfMon
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]>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors", [
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FeatureBalanceFPOps,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureFuseLiterals,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive
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]>;
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def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
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"Cortex-A72 ARM processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
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"Cortex-A73 ARM processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
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"Cortex-A75 ARM processors", [
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HasV8_2aOps,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeatureFullFP16,
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FeatureDotProd,
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FeatureRCPC,
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FeaturePerfMon
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]>;
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// Note that cyclone does not fuse AES instructions, but newer apple chips do
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// perform the fusion and cyclone is used by default when targetting apple OSes.
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def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
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"Cyclone", [
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FeatureAlternateSExtLoadCVTF32Pattern,
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FeatureArithmeticBccFusion,
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FeatureArithmeticCbzFusion,
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FeatureCrypto,
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FeatureDisableLatencySchedHeuristic,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon,
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FeatureSlowMisaligned128Store,
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FeatureZCRegMove,
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FeatureZCZeroing
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]>;
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def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
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"Samsung Exynos-M1 processors",
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[FeatureSlowPaired128,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureSlowMisaligned128Store,
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FeatureUseRSqrt,
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FeatureZCZeroing]>;
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def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
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"Samsung Exynos-M2/M3 processors",
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[FeatureSlowPaired128,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureSlowMisaligned128Store,
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FeatureZCZeroing]>;
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def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
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"Qualcomm Kryo processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureZCZeroing,
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FeatureLSLFast
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]>;
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def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
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"Qualcomm Falkor processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureRDM,
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FeatureZCZeroing,
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FeatureLSLFast,
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FeatureSlowSTRQro
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]>;
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def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
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"Qualcomm Saphira processors", [
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeatureSPE,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureZCZeroing,
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FeatureLSLFast,
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HasV8_3aOps]>;
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def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
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"ThunderX2T99",
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"Cavium ThunderX2 processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureArithmeticBccFusion,
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FeatureNEON,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureLSE,
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HasV8_1aOps]>;
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def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
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"Cavium ThunderX processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureNEON]>;
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def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
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"ThunderXT88",
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"Cavium ThunderX processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureNEON]>;
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def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
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"ThunderXT81",
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"Cavium ThunderX processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureNEON]>;
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def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
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"ThunderXT83",
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"Cavium ThunderX processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureNEON]>;
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def : ProcessorModel<"generic", NoSchedModel, [
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler
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]>;
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// FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
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def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
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def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
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def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
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def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
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// FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57.
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def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
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def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
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def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
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def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
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def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
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def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
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def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
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def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
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def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
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// Cavium ThunderX/ThunderX T8X Processors
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def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
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def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
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def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
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def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
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// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
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def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def GenericAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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string Name = "generic";
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string BreakCharacters = ".";
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}
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def AppleAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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string Name = "apple-neon";
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string BreakCharacters = ".";
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}
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//===----------------------------------------------------------------------===//
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// Assembly printer
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//===----------------------------------------------------------------------===//
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// AArch64 Uses the MC printer for asm output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def GenericAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def AppleAsmWriter : AsmWriter {
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let AsmWriterClassName = "AppleInstPrinter";
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|
int PassSubtarget = 1;
|
|
int Variant = 1;
|
|
int isMCAsmWriter = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target Declaration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def AArch64 : Target {
|
|
let InstructionSet = AArch64InstrInfo;
|
|
let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
|
|
let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
|
|
}
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