Simon Pilgrim 9bb9f0f392 [X86][AVX2] Vectorized i16 shift operators ... Part of D9474, this patch extends AVX2 v16i16 types to 2 x 8i32 vectors and uses i32 shift variable shifts before packing back to i16. Adds AVX2 tests for v8i16 and v16i16 llvm-svn: 238149		2015-05-25 17:49:13 +00:00
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AArch64	[AArch64][CGP] Sink zext feeding stxr/stlxr into the same block.	2015-05-22 21:37:17 +00:00
ARM	Stop resetting NoFramePointerElim in TargetMachine::resetTargetOptions.	2015-05-23 01:14:08 +00:00
BPF
CPP
Generic	Revert r237954, "Resubmit r237708 (MIR Serialization: print and parse LLVM IR using MIR format)."	2015-05-22 07:17:07 +00:00
Hexagon
Inputs
Mips	Revert r237789 - [mips] The naming convention for private labels is ABI dependant.	2015-05-20 14:18:59 +00:00
MSP430
NVPTX
PowerPC	This patch adds support for the vector quadword add/sub instructions introduced	2015-05-25 15:49:26 +00:00
R600	R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips	2015-05-25 16:15:54 +00:00
SPARC	Add support for the Sparc implementation-defined "ASR" registers.	2015-05-18 16:29:48 +00:00
SystemZ
Thumb
Thumb2	Revert r237590, "ARM: allow jump tables to be placed as constant islands."	2015-05-21 23:20:55 +00:00
WinEH	[WinEH] C++ EH state numbering fixes	2015-05-20 23:22:24 +00:00
X86	[X86][AVX2] Vectorized i16 shift operators	2015-05-25 17:49:13 +00:00
XCore