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12cdca9076
Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
14 lines
462 B
ArmAsm
14 lines
462 B
ArmAsm
// RUN: not llvm-mc %s -triple x86_64-unknown-unknown --show-encoding -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s
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// ERR: Register k0 can't be used as write mask
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vpcmpd $1, %zmm24, %zmm7, %k5{%k0}
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// ERR: Expected a {z} mark at this point
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vfmsub213ps %zmm8, %zmm8, %zmm8{%k2} {rn-sae}
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// ERR: Expected an op-mask register at this point
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vfmsub213ps %zmm8, %zmm8, %zmm8 {rn-sae}
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// ERR: invalid operand for instruction
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cvtsd2sil {rn-sae}, %xmm1, %eax
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