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12cdca9076
Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
31 lines
1.3 KiB
ArmAsm
31 lines
1.3 KiB
ArmAsm
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
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// CHECK: vpclmulqdq $17, %ymm3, %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xe3,0x6d,0x44,0xcb,0x11]
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vpclmulqdq $17, %ymm3, %ymm2, %ymm1
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// CHECK: vpclmulqdq $1, (%rcx), %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xe3,0x6d,0x44,0x09,0x01]
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vpclmulqdq $1, (%rcx), %ymm2, %ymm1
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// CHECK: vpclmulqdq $1, -4(%rsp), %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xe3,0x6d,0x44,0x4c,0x24,0xfc,0x01]
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vpclmulqdq $1, -4(%rsp), %ymm2, %ymm1
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// CHECK: vpclmulqdq $1, 4(%rsp), %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xe3,0x6d,0x44,0x4c,0x24,0x04,0x01]
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vpclmulqdq $1, 4(%rsp), %ymm2, %ymm1
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// CHECK: vpclmulqdq $1, 268435456(%rcx,%r14,8), %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xa3,0x6d,0x44,0x8c,0xf1,0x00,0x00,0x00,0x10,0x01]
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vpclmulqdq $1, 268435456(%rcx,%r14,8), %ymm2, %ymm1
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// CHECK: vpclmulqdq $1, -536870912(%rcx,%r14,8), %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xa3,0x6d,0x44,0x8c,0xf1,0x00,0x00,0x00,0xe0,0x01]
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vpclmulqdq $1, -536870912(%rcx,%r14,8), %ymm2, %ymm1
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// CHECK: vpclmulqdq $1, -536870910(%rcx,%r14,8), %ymm2, %ymm1
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// CHECK: encoding: [0xc4,0xa3,0x6d,0x44,0x8c,0xf1,0x02,0x00,0x00,0xe0,0x01]
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vpclmulqdq $1, -536870910(%rcx,%r14,8), %ymm2, %ymm1
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