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e01dc73ad2
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
242 lines
6.5 KiB
C++
242 lines
6.5 KiB
C++
//===- RDFRegisters.h -------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
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#define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <set>
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#include <vector>
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namespace llvm {
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class MachineFunction;
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class raw_ostream;
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namespace rdf {
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using RegisterId = uint32_t;
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// Template class for a map translating uint32_t into arbitrary types.
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// The map will act like an indexed set: upon insertion of a new object,
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// it will automatically assign a new index to it. Index of 0 is treated
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// as invalid and is never allocated.
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template <typename T, unsigned N = 32>
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struct IndexedSet {
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IndexedSet() { Map.reserve(N); }
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T get(uint32_t Idx) const {
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// Index Idx corresponds to Map[Idx-1].
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assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
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return Map[Idx-1];
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}
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uint32_t insert(T Val) {
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// Linear search.
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auto F = llvm::find(Map, Val);
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if (F != Map.end())
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return F - Map.begin() + 1;
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Map.push_back(Val);
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return Map.size(); // Return actual_index + 1.
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}
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uint32_t find(T Val) const {
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auto F = llvm::find(Map, Val);
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assert(F != Map.end());
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return F - Map.begin() + 1;
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}
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uint32_t size() const { return Map.size(); }
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using const_iterator = typename std::vector<T>::const_iterator;
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const_iterator begin() const { return Map.begin(); }
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const_iterator end() const { return Map.end(); }
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private:
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std::vector<T> Map;
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};
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struct RegisterRef {
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RegisterId Reg = 0;
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LaneBitmask Mask = LaneBitmask::getNone();
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RegisterRef() = default;
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explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
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: Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
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operator bool() const {
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return Reg != 0 && Mask.any();
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}
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bool operator== (const RegisterRef &RR) const {
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return Reg == RR.Reg && Mask == RR.Mask;
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}
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bool operator!= (const RegisterRef &RR) const {
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return !operator==(RR);
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}
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bool operator< (const RegisterRef &RR) const {
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return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
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}
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};
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struct PhysicalRegisterInfo {
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PhysicalRegisterInfo(const TargetRegisterInfo &tri,
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const MachineFunction &mf);
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static bool isRegMaskId(RegisterId R) {
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return TargetRegisterInfo::isStackSlot(R);
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}
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RegisterId getRegMaskId(const uint32_t *RM) const {
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return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
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}
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const uint32_t *getRegMaskBits(RegisterId R) const {
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return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
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}
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RegisterRef normalize(RegisterRef RR) const;
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bool alias(RegisterRef RA, RegisterRef RB) const {
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if (!isRegMaskId(RA.Reg))
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return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
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return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
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}
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std::set<RegisterId> getAliasSet(RegisterId Reg) const;
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RegisterRef getRefForUnit(uint32_t U) const {
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return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
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}
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const BitVector &getMaskUnits(RegisterId MaskId) const {
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return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
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}
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RegisterRef mapTo(RegisterRef RR, unsigned R) const;
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const TargetRegisterInfo &getTRI() const { return TRI; }
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private:
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struct RegInfo {
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const TargetRegisterClass *RegClass = nullptr;
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};
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struct UnitInfo {
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RegisterId Reg = 0;
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LaneBitmask Mask;
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};
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struct MaskInfo {
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BitVector Units;
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};
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const TargetRegisterInfo &TRI;
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IndexedSet<const uint32_t*> RegMasks;
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std::vector<RegInfo> RegInfos;
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std::vector<UnitInfo> UnitInfos;
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std::vector<MaskInfo> MaskInfos;
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bool aliasRR(RegisterRef RA, RegisterRef RB) const;
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bool aliasRM(RegisterRef RR, RegisterRef RM) const;
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bool aliasMM(RegisterRef RM, RegisterRef RN) const;
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};
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struct RegisterAggr {
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RegisterAggr(const PhysicalRegisterInfo &pri)
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: Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
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RegisterAggr(const RegisterAggr &RG) = default;
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bool empty() const { return Units.none(); }
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bool hasAliasOf(RegisterRef RR) const;
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bool hasCoverOf(RegisterRef RR) const;
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static bool isCoverOf(RegisterRef RA, RegisterRef RB,
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const PhysicalRegisterInfo &PRI) {
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return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
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}
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RegisterAggr &insert(RegisterRef RR);
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RegisterAggr &insert(const RegisterAggr &RG);
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RegisterAggr &intersect(RegisterRef RR);
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RegisterAggr &intersect(const RegisterAggr &RG);
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RegisterAggr &clear(RegisterRef RR);
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RegisterAggr &clear(const RegisterAggr &RG);
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RegisterRef intersectWith(RegisterRef RR) const;
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RegisterRef clearIn(RegisterRef RR) const;
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RegisterRef makeRegRef() const;
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void print(raw_ostream &OS) const;
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struct rr_iterator {
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using MapType = std::map<RegisterId, LaneBitmask>;
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private:
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MapType Masks;
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MapType::iterator Pos;
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unsigned Index;
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const RegisterAggr *Owner;
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public:
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rr_iterator(const RegisterAggr &RG, bool End);
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RegisterRef operator*() const {
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return RegisterRef(Pos->first, Pos->second);
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}
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rr_iterator &operator++() {
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++Pos;
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++Index;
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return *this;
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}
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bool operator==(const rr_iterator &I) const {
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assert(Owner == I.Owner);
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(void)Owner;
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return Index == I.Index;
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}
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bool operator!=(const rr_iterator &I) const {
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return !(*this == I);
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}
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};
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rr_iterator rr_begin() const {
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return rr_iterator(*this, false);
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}
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rr_iterator rr_end() const {
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return rr_iterator(*this, true);
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}
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private:
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BitVector Units;
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const PhysicalRegisterInfo &PRI;
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};
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// Optionally print the lane mask, if it is not ~0.
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struct PrintLaneMaskOpt {
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PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {}
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LaneBitmask Mask;
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};
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raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P);
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} // end namespace rdf
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
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