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llvm-mirror/test/CodeGen
Wei Mi 4f28dc3b0c [LSR] Recommit: Allow formula containing Reg for SCEVAddRecExpr related with outerloop.
The recommit includes some changes of testcases. No functional change to the patch.

In RateRegister of existing LSR, if a formula contains a Reg which is a SCEVAddRecExpr,
and this SCEVAddRecExpr's loop is an outerloop, the formula will be marked as Loser
and dropped.

Suppose we have an IR that %for.body is outerloop and %for.body2 is innerloop. LSR only
handle inner loop now so only %for.body2 will be handled.

Using the logic above, formula like
reg(%array) + reg({1,+, %size}<%for.body>) + 1*reg({0,+,1}<%for.body2>) will be dropped
no matter what because reg({1,+, %size}<%for.body>) is a SCEVAddRecExpr type reg related
with outerloop. Only formula like
reg(%array) + 1*reg({{1,+, %size}<%for.body>,+,1}<nuw><nsw><%for.body2>) will be kept
because the SCEVAddRecExpr related with outerloop is folded into the initial value of the
SCEVAddRecExpr related with current loop.

But in some cases, we do need to share the basic induction variable
reg{0 ,+, 1}<%for.body2> among LSR Uses to reduce the final total number of induction
variables used by LSR, so we don't want to drop the formula like
reg(%array) + reg({1,+, %size}<%for.body>) + 1*reg({0,+,1}<%for.body2>) unconditionally.

From the existing comment, it tries to avoid considering multiple level loops at the same time.
However, existing LSR only handles innermost loop, so for any SCEVAddRecExpr with a loop other
than current loop, it is an invariant and will be simple to handle, and the formula doesn't have
to be dropped.

Differential Revision: https://reviews.llvm.org/D26429

llvm-svn: 294814
2017-02-11 00:50:23 +00:00
..
AArch64 [LSR] Recommit: Allow formula containing Reg for SCEVAddRecExpr related with outerloop. 2017-02-11 00:50:23 +00:00
AMDGPU AMDGPU : Add trap handler support. 2017-02-10 02:15:29 +00:00
ARM [ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic 2017-02-10 17:41:08 +00:00
AVR [AVR] Implement stacksave/stackrestore by expanding (PR31342) 2017-02-05 21:35:45 +00:00
BPF
Generic [AVR] XFAIL a set of failing CodeGen tests 2017-02-08 10:24:18 +00:00
Hexagon [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
Inputs
Lanai
Mips [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
MIR
MSP430
NVPTX [NVPTX] Add tests that invariant vector loads get lowered to ld.global.nc. 2017-02-04 01:54:56 +00:00
PowerPC Add test case for pr31890. NFC 2017-02-08 14:35:48 +00:00
SPARC [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
SystemZ [TLI] Robustize SDAG LibFunc proto checking by merging it into TLI. 2017-02-03 19:11:19 +00:00
Thumb [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
Thumb2
WebAssembly
WinEH
X86 [LSR] Recommit: Allow formula containing Reg for SCEVAddRecExpr related with outerloop. 2017-02-11 00:50:23 +00:00
XCore Move some error handling down to MCStreamer. 2017-02-10 15:13:12 +00:00