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51057b05fa
This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216217
289 lines
9.4 KiB
C++
289 lines
9.4 KiB
C++
//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SIRegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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using namespace llvm;
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SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
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: AMDGPURegisterInfo(st)
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{ }
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BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(AMDGPU::EXEC);
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Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
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return Reserved;
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}
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unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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return RC->getNumRegs();
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}
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bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
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return Fn.getFrameInfo()->hasStackObjects();
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}
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static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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switch (Op) {
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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return 16;
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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return 4;
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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return 2;
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case AMDGPU::SI_SPILL_S32_SAVE:
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case AMDGPU::SI_SPILL_S32_RESTORE:
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return 1;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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MachineFunction *MF = MI->getParent()->getParent();
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MachineBasicBlock *MBB = MI->getParent();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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MachineOperand &FIOp = MI->getOperand(FIOperandNum);
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int Index = MI->getOperand(FIOperandNum).getIndex();
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switch (MI->getOpcode()) {
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// SGPR register spill
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S32_SAVE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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struct SIMachineFunctionInfo::SpilledReg Spill =
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MFI->getSpilledReg(MF, Index, i);
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if (Spill.VGPR == AMDGPU::NoRegister) {
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LLVMContext &Ctx = MF->getFunction()->getContext();
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Ctx.emitError("Ran out of VGPRs for spilling SGPR");
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}
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
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.addReg(SubReg)
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.addImm(Spill.Lane);
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}
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MI->eraseFromParent();
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break;
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}
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// SGPR register restore
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_S32_RESTORE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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struct SIMachineFunctionInfo::SpilledReg Spill =
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MFI->getSpilledReg(MF, Index, i);
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if (Spill.VGPR == AMDGPU::NoRegister) {
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LLVMContext &Ctx = MF->getFunction()->getContext();
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Ctx.emitError("Ran out of VGPRs for spilling SGPR");
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}
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
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.addReg(Spill.VGPR)
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.addImm(Spill.Lane);
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}
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TII->insertNOPs(MI, 3);
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MI->eraseFromParent();
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break;
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}
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default: {
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int64_t Offset = FrameInfo->getObjectOffset(Index);
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FIOp.ChangeToImmediate(Offset);
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if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
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unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
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.addImm(Offset);
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FIOp.ChangeToRegister(TmpReg, false);
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}
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}
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}
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}
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const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::VReg_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
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return getEncodingValue(Reg) & 0xff;
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}
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const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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const TargetRegisterClass *BaseClasses[] = {
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&AMDGPU::VReg_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::VReg_64RegClass,
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&AMDGPU::SReg_64RegClass,
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&AMDGPU::SReg_128RegClass,
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&AMDGPU::SReg_256RegClass
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};
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for (const TargetRegisterClass *BaseClass : BaseClasses) {
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if (BaseClass->contains(Reg)) {
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return BaseClass;
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}
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}
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return nullptr;
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}
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bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
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if (!RC) {
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return false;
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}
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return !hasVGPRs(RC);
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}
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bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
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return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
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}
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const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const {
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if (hasVGPRs(SRC)) {
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return SRC;
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} else if (SRC == &AMDGPU::SCCRegRegClass) {
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return &AMDGPU::VCCRegRegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
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return &AMDGPU::VReg_32RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
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return &AMDGPU::VReg_64RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
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return &AMDGPU::VReg_128RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
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return &AMDGPU::VReg_256RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
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return &AMDGPU::VReg_512RegClass;
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}
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return nullptr;
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}
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const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
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const TargetRegisterClass *RC, unsigned SubIdx) const {
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if (SubIdx == AMDGPU::NoSubRegister)
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return RC;
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// If this register has a sub-register, we can safely assume it is a 32-bit
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// register, because all of SI's sub-registers are 32-bit.
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if (isSGPRClass(RC)) {
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return &AMDGPU::SGPR_32RegClass;
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} else {
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return &AMDGPU::VGPR_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
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const TargetRegisterClass *SubRC,
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unsigned Channel) const {
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switch (Reg) {
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case AMDGPU::VCC:
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switch(Channel) {
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case 0: return AMDGPU::VCC_LO;
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case 1: return AMDGPU::VCC_HI;
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default: llvm_unreachable("Invalid SubIdx for VCC");
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}
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break;
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}
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unsigned Index = getHWRegIndex(Reg);
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return SubRC->getRegister(Index + Channel);
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}
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bool SIRegisterInfo::regClassCanUseImmediate(int RCID) const {
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switch (RCID) {
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default: return false;
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case AMDGPU::SSrc_32RegClassID:
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case AMDGPU::SSrc_64RegClassID:
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case AMDGPU::VSrc_32RegClassID:
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case AMDGPU::VSrc_64RegClassID:
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return true;
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}
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}
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bool SIRegisterInfo::regClassCanUseImmediate(
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const TargetRegisterClass *RC) const {
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return regClassCanUseImmediate(RC->getID());
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}
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unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
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enum PreloadedValue Value) const {
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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switch (Value) {
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case SIRegisterInfo::TGID_X:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
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case SIRegisterInfo::TGID_Y:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
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case SIRegisterInfo::TGID_Z:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
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case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
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case SIRegisterInfo::SCRATCH_PTR:
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return AMDGPU::SGPR2_SGPR3;
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}
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llvm_unreachable("unexpected preloaded value type");
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}
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