Kai Nacke fd99c3fbd8 [MIPS] Add cpu octeon and some instructions ... The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337		2014-03-20 11:51:58 +00:00
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AArch64	[AArch64]Fix improper diagnostics about offset range of load/store instructions.	2014-03-04 02:05:13 +00:00
ARM	Reapply 'ARM IAS: support .thumb_set'	2014-03-20 06:05:33 +00:00
AsmParser	Move tests that require ARM to an ARM test directory.	2014-03-18 22:43:59 +00:00
COFF	Object/COFF: change data type of SymbolNumber from int16 to uint16.	2014-03-15 00:04:08 +00:00
Disassembler	Test case for r204305.	2014-03-20 06:45:10 +00:00
ELF	Look through variables when computing relocations.	2014-03-20 02:12:01 +00:00
MachO	Move yet another test that requires ARM to an ARM test directory.	2014-03-18 23:12:09 +00:00
Markup
Mips	[MIPS] Add cpu octeon and some instructions	2014-03-20 11:51:58 +00:00
PowerPC	[PowerPC] Initial support for the VSX instruction set	2014-03-13 07:58:58 +00:00
Sparc	[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.	2014-03-02 23:39:07 +00:00
SystemZ	[SystemZ] Add MC support for interlocked-access 1 instructions	2013-12-24 15:14:05 +00:00
X86	Look through variables when computing relocations.	2014-03-20 02:12:01 +00:00