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llvm-mirror/lib/Target/Sparc
James Y Knight 5a3ef042dd Fix assert when emitting llvm.pow.f86.
This occurred due to introducing the invalid i64 type after type
legalization had already finished, in an attempt to workaround bitcast
f64 -> v2i32 not doing constant folding.

The *right* thing is to actually fix bitcast, but that has other
complications. So, for now, just get rid of the broken workaround, and
check in a test-case showing that it doesn't crash, with TODOs for
emitting proper code.

llvm-svn: 249908
2015-10-09 21:36:19 +00:00
..
AsmParser [SPARCv9] Add support for the rdpr/wrpr instructions. 2015-10-04 09:11:22 +00:00
Disassembler [SPARCv9] Add support for the rdpr/wrpr instructions. 2015-10-04 09:11:22 +00:00
InstPrinter
MCTargetDesc Fix pr24486. 2015-10-05 12:07:05 +00:00
TargetInfo
CMakeLists.txt
DelaySlotFiller.cpp
LLVMBuild.txt
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcFrameLowering.cpp [SPARC] Fix stupid oversight in stack realignment support. 2015-08-26 17:57:51 +00:00
SparcFrameLowering.h [SPARC] Fix stupid oversight in stack realignment support. 2015-08-26 17:57:51 +00:00
SparcInstr64Bit.td
SparcInstrAliases.td [SPARC] Both GNU and Solaris as support eq as condition code for integer ops. 2015-09-16 14:41:36 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td [SPARCv9] Add support for the rdpr/wrpr instructions. 2015-10-04 09:11:22 +00:00
SparcInstrVIS.td
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Fix assert when emitting llvm.pow.f86. 2015-10-09 21:36:19 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp
SparcRegisterInfo.cpp [Sparc] Support user-specified stack object overalignment. 2015-08-21 04:17:56 +00:00
SparcRegisterInfo.h [Sparc] Support user-specified stack object overalignment. 2015-08-21 04:17:56 +00:00
SparcRegisterInfo.td [SPARCv9] Add support for the rdpr/wrpr instructions. 2015-10-04 09:11:22 +00:00
SparcSubtarget.cpp Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC. 2015-09-15 16:17:27 +00:00
SparcSubtarget.h [SPARC] Switch to the Machine Scheduler. 2015-09-10 21:49:06 +00:00
SparcTargetMachine.cpp
SparcTargetMachine.h
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h
SparcTargetStreamer.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.