Francesco Petrogalli 6fee8f8f2e [SVE][VLS] Don't combine logical AND. ... Testing is performed when targeting 128, 256 and 512-bit wide vectors. For 128-bit vectors, the original behavior of using NEON instructions is preserved. Differential Revision: https://reviews.llvm.org/D85479		2020-08-12 20:00:07 +01:00
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AArch64	[SVE][VLS] Don't combine logical AND.	2020-08-12 20:00:07 +01:00
AMDGPU	AMDGPU/GlobalISel: Select llvm.amdgcn.global.atomic.fadd	2020-08-12 10:04:53 -04:00
ARC
ARM
AVR
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC	[AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations	2020-08-11 15:26:19 -04:00
RISCV
SPARC
SystemZ
Thumb
Thumb2	[ARM] Predicated VFMA patterns	2020-08-12 18:35:01 +01:00
VE	[VE] Change to promote i32 AND/OR/XOR operations	2020-08-12 16:23:50 +09:00
WebAssembly
WinCFGuard
WinEH
X86	[X86][GlobalISel] Legalize G_ICMP results to s8.	2020-08-12 10:13:59 -07:00
XCore