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495 lines
22 KiB
LLVM
495 lines
22 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
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; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
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; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
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; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
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; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4
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; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
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; Test subword and word stores.
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@a = common global i8 0, align 4
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@b = common global i16 0, align 4
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@c = common global i32 0, align 4
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@d = common global i64 0, align 8
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define void @f1(i8 %a) {
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; MIPS32-LABEL: f1:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
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; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
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;
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; MMR3-LABEL: f1:
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; MMR3: # %bb.0:
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; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
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; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
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;
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; MIPS32R6-LABEL: f1:
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; MIPS32R6: # %bb.0:
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; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
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; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
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;
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; MMR6-LABEL: f1:
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; MMR6: # %bb.0:
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; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
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; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
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; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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;
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; MIPS4-LABEL: f1:
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; MIPS4: # %bb.0:
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; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%highest(a))>>
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; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%higher(a))>>
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; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Imm:16>>
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; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%hi(a))>>
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; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Imm:16>>
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; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%lo(a))>>
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;
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; MIPS64R6-LABEL: f1:
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; MIPS64R6: # %bb.0:
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; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
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; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
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; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Imm:16>>
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; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
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; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Imm:16>>
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; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
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store i8 %a, i8 * @a
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ret void
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}
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define void @f2(i16 %a) {
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; MIPS32-LABEL: f2:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
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; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
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;
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; MMR3-LABEL: f2:
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; MMR3: # %bb.0:
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; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
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; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
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;
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; MIPS32R6-LABEL: f2:
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; MIPS32R6: # %bb.0:
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; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
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; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
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;
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; MMR6-LABEL: f2:
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; MMR6: # %bb.0:
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; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
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; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
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; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
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; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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;
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; MIPS4-LABEL: f2:
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; MIPS4: # %bb.0:
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; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%highest(b))>>
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; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%higher(b))>>
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; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Imm:16>>
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; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%hi(b))>>
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; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Imm:16>>
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; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS4-NEXT: # <MCOperand Expr:(%lo(b))>>
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;
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; MIPS64R6-LABEL: f2:
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; MIPS64R6: # %bb.0:
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; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
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; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
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; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Imm:16>>
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; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
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; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Imm:16>>
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; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
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store i16 %a, i16 * @b
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ret void
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}
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define void @f3(i32 %a) {
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; MIPS32-LABEL: f3:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
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; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
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;
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; MMR3-LABEL: f3:
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; MMR3: # %bb.0:
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; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
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; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
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;
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; MIPS32R6-LABEL: f3:
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; MIPS32R6: # %bb.0:
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; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
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; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
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; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
|
|
;
|
|
; MMR6-LABEL: f3:
|
|
; MMR6: # %bb.0:
|
|
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
|
|
; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
|
|
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
;
|
|
; MIPS4-LABEL: f3:
|
|
; MIPS4: # %bb.0:
|
|
; MIPS4-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Imm:0>>
|
|
; MIPS4-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%highest(c))>>
|
|
; MIPS4-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%higher(c))>>
|
|
; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS4-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%hi(c))>>
|
|
; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
; MIPS4-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%lo(c))>>
|
|
;
|
|
; MIPS64R6-LABEL: f3:
|
|
; MIPS64R6: # %bb.0:
|
|
; MIPS64R6-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Imm:0>>
|
|
; MIPS64R6-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
|
|
; MIPS64R6-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
|
|
; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS64R6-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
|
|
; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
; MIPS64R6-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
|
|
store i32 %a, i32 * @c
|
|
ret void
|
|
}
|
|
|
|
define void @f4(i64 %a) {
|
|
; MIPS32-LABEL: f4:
|
|
; MIPS32: # %bb.0:
|
|
; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Expr:(%hi(d))>>
|
|
; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
; MIPS32-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32-NEXT: # <MCOperand Imm:4>>
|
|
;
|
|
; MMR3-LABEL: f4:
|
|
; MMR3: # %bb.0:
|
|
; MMR3-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Expr:(%hi(d))>>
|
|
; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR3-NEXT: # <MCOperand Imm:4>>
|
|
; MMR3-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
|
; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
;
|
|
; MIPS32R6-LABEL: f4:
|
|
; MIPS32R6: # %bb.0:
|
|
; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(d))>>
|
|
; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS32R6-NEXT: # <MCOperand Imm:4>>
|
|
;
|
|
; MMR6-LABEL: f4:
|
|
; MMR6: # %bb.0:
|
|
; MMR6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Expr:(%hi(d))>>
|
|
; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MMR6-NEXT: # <MCOperand Imm:4>>
|
|
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
|
|
; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
;
|
|
; MIPS4-LABEL: f4:
|
|
; MIPS4: # %bb.0:
|
|
; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%highest(d))>>
|
|
; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%higher(d))>>
|
|
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%hi(d))>>
|
|
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS4-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
;
|
|
; MIPS64R6-LABEL: f4:
|
|
; MIPS64R6: # %bb.0:
|
|
; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(d))>>
|
|
; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(d))>>
|
|
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(d))>>
|
|
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
|
|
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
|
; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
|
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(d))>>
|
|
store i64 %a, i64 * @d
|
|
ret void
|
|
}
|