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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
82 lines
2.7 KiB
LLVM
82 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IF
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; Exercises the ILP32 calling convention code in the case that f32 is a legal
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; type. As well as testing that lowering is correct, these tests also aim to
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; check that floating point load/store or integer load/store is chosen
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; optimally when floats are passed on the stack.
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define float @onstack_f32_noop(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
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; RV32IF-LABEL: onstack_f32_noop:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lw a0, 4(sp)
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; RV32IF-NEXT: ret
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ret float %f
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}
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define float @onstack_f32_fadd(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
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; RV32IF-LABEL: onstack_f32_fadd:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: flw ft0, 4(sp)
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; RV32IF-NEXT: flw ft1, 0(sp)
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fadd float %e, %f
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ret float %1
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}
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define float @caller_onstack_f32_noop(float %a) nounwind {
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; RV32IF-LABEL: caller_onstack_f32_noop:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp)
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; RV32IF-NEXT: sw a0, 4(sp)
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; RV32IF-NEXT: lui a1, 264704
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; RV32IF-NEXT: addi a0, zero, 1
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; RV32IF-NEXT: addi a2, zero, 2
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; RV32IF-NEXT: addi a4, zero, 3
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; RV32IF-NEXT: addi a6, zero, 4
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; RV32IF-NEXT: sw a1, 0(sp)
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; RV32IF-NEXT: mv a1, zero
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; RV32IF-NEXT: mv a3, zero
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; RV32IF-NEXT: mv a5, zero
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; RV32IF-NEXT: mv a7, zero
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; RV32IF-NEXT: call onstack_f32_noop
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; RV32IF-NEXT: lw ra, 12(sp)
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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%1 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float 5.0, float %a)
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ret float %1
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}
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define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
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; RV32IF-LABEL: caller_onstack_f32_fadd:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp)
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft2, ft1, ft0
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; RV32IF-NEXT: fsub.s ft0, ft0, ft1
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; RV32IF-NEXT: fsw ft0, 4(sp)
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; RV32IF-NEXT: addi a0, zero, 1
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; RV32IF-NEXT: addi a2, zero, 2
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; RV32IF-NEXT: addi a4, zero, 3
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; RV32IF-NEXT: addi a6, zero, 4
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; RV32IF-NEXT: fsw ft2, 0(sp)
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; RV32IF-NEXT: mv a1, zero
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; RV32IF-NEXT: mv a3, zero
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; RV32IF-NEXT: mv a5, zero
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; RV32IF-NEXT: mv a7, zero
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; RV32IF-NEXT: call onstack_f32_noop
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; RV32IF-NEXT: lw ra, 12(sp)
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = fsub float %b, %a
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%3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2)
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ret float %3
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}
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