mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
1ae2a5de8f
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
35 lines
1.1 KiB
LLVM
35 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
|
|
;
|
|
; The test case check that RV64 could handle the stack adjustment offset exceed
|
|
; 32-bit.
|
|
|
|
define void @foo() nounwind {
|
|
; CHECK-LABEL: foo:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: addi sp, sp, -2032
|
|
; CHECK-NEXT: sd ra, 2024(sp)
|
|
; CHECK-NEXT: lui a0, 95
|
|
; CHECK-NEXT: addiw a0, a0, 1505
|
|
; CHECK-NEXT: slli a0, a0, 13
|
|
; CHECK-NEXT: addi a0, a0, -2000
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: call baz
|
|
; CHECK-NEXT: lui a0, 95
|
|
; CHECK-NEXT: addiw a0, a0, 1505
|
|
; CHECK-NEXT: slli a0, a0, 13
|
|
; CHECK-NEXT: addi a0, a0, -2000
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: ld ra, 2024(sp)
|
|
; CHECK-NEXT: addi sp, sp, 2032
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%w = alloca [100000000 x { fp128, fp128 }], align 16
|
|
%arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
|
|
call void @baz({ fp128, fp128 }* nonnull %arraydecay)
|
|
ret void
|
|
}
|
|
|
|
declare void @baz({ fp128, fp128 }*)
|