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4e3b9e456b
SelectionDAGBuilder::visitShift will always zero-extend a shift amount when it is promoted to the ShiftAmountTy. This results in zero-extension (masking) which is unnecessary for RISC-V as the shift operations only read the lower 5 or 6 bits (RV32 or RV64). I initially proposed adding a getExtendForShiftAmount hook so the shift amount can be any-extended (D52975). @efriedma explained this was unsafe, so I have instead eliminate the unnecessary and operations at instruction selection time in a manner similar to X86InstrCompiler.td. Differential Revision: https://reviews.llvm.org/D53224 llvm-svn: 344432
71 lines
1.9 KiB
LLVM
71 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; This test checks that unnecessary masking of shift amount operands is
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; eliminated during instruction selection. The test needs to ensure that the
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; masking is not removed if it may affect the shift amount.
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define i32 @sll_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sll_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: ret
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%1 = and i32 %b, 31
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%2 = shl i32 %a, %1
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ret i32 %2
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}
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define i32 @sll_non_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sll_non_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 15
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: ret
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%1 = and i32 %b, 15
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%2 = shl i32 %a, %1
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ret i32 %2
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}
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define i32 @srl_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srl_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: ret
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%1 = and i32 %b, 4095
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%2 = lshr i32 %a, %1
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ret i32 %2
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}
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define i32 @srl_non_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srl_non_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 7
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: ret
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%1 = and i32 %b, 7
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%2 = lshr i32 %a, %1
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ret i32 %2
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}
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define i32 @sra_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sra_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: ret
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%1 = and i32 %b, 65535
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%2 = ashr i32 %a, %1
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ret i32 %2
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}
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define i32 @sra_non_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sra_non_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 32
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: ret
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%1 = and i32 %b, 32
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%2 = ashr i32 %a, %1
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ret i32 %2
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}
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