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edd0920371
This patch adds support for compact jumps similiar to the previous compact branch support for MIPSR6. Unlike compact branches, compact jumps do not have a forbidden slot. As MipsInstrInfo::getEquivalentCompactForm can determine the correct expansion for jumps and branches for both microMIPS and MIPSR6, remove the unnecessary distinction in the delay slot filler. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders llvm-svn: 265390
236 lines
11 KiB
TableGen
236 lines
11 KiB
TableGen
//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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// Notes about removals/changes from MIPS32r6:
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// Reencoded: dclo, dclz
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
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class DAUI_ENC : DAUI_FM;
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class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
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class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
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class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
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class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
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class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
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class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
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class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
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class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
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class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
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class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
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class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>;
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class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;
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class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
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class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
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class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
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class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
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class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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string Constraints = "$rs = $rt";
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InstrItinClass Itinerary = itin;
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}
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class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
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class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
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class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
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class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
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class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
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class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
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class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
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class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
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class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
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class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
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class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
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class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
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class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
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class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
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class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
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class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
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class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
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class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, II_LLD>;
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class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
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class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
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class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
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class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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GPR64Opnd> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
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bit isBarrier = 1;
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bit isTerminator = 1;
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list<Register> Defs = [AT];
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [NotInMicroMips] in {
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def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
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def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
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def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
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def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
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}
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def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
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def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
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def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
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def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
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def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
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def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
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def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
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def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
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def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
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def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
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def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
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def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
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def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
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def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
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let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
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def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
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}
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let isCodeGenOnly = 1 in {
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def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
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def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Aliases
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//
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//===----------------------------------------------------------------------===//
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def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
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//===----------------------------------------------------------------------===//
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//
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// Patterns and Pseudo Instructions
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//
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//===----------------------------------------------------------------------===//
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// i64 selects
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def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, i64:$cond),
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(SELEQZ64 i64:$f, i64:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, i64:$cond),
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(SELNEZ64 i64:$f, i64:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, i64:$cond),
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(SELEQZ64 i64:$f, i64:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
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(SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
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(SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
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ISA_MIPS64R6;
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def : MipsPat<
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(select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t,
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(SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)),
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(SELNEZ64 i64:$f,
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(SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)))>,
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ISA_MIPS64R6;
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def : MipsPat<
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(select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t,
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(SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)),
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(SELNEZ64 i64:$f,
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(SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
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(SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
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(SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
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(SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
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(SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
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// i64 selects from an i32 comparison
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// One complicating factor here is that bits 32-63 of an i32 are undefined.
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// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
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// This would allow us to remove the sign-extensions here.
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def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
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(SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))),
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(SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))),
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(SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))))>,
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ISA_MIPS64R6;
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def : MipsPat<(select i32:$cond, i64:$t, immz),
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(SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
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(SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
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(SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select i32:$cond, immz, i64:$f),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
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(SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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