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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
llvm-mirror/test/TableGen
Quentin Colombet acf8746c63 [GlobalISel] Add a generic machine opcode for ADD.
The selection process being split into separate passes, we need generic opcodes
to translate the LLVM IR to target independent code.

This patch adds an opcode for addition: G_ADD.

Differential Revision: http://reviews.llvm.org/D15472

llvm-svn: 258333
2016-01-20 19:14:55 +00:00
..
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AnonDefinitionOnDemand.td
AsmPredicateCondsEmission.td Use std::bitset for SubtargetFeatures. 2015-05-26 10:47:10 +00:00
BitOffsetDecoder.td
BitsInit.td
BitsInitOverflow.td
cast-list-initializer.td TableGen: Support folding casts from bits to int 2015-07-31 01:12:06 +00:00
cast.td
ClassInstanceValue.td
CStyleComment.td
Dag.td
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
eq.td
eqbit.td
FieldAccess.td
foreach.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
if-empty-list-arg.td
if.td
ifbit.td
Include.inc
Include.td
IntBitInit.td
intrinsic-long-name.td
intrinsic-order.td
intrinsic-varargs.td Add new vector types for 512-, 1024- and 2048-bit vectors 2015-11-24 13:07:35 +00:00
LazyChange.td
LetInsideMultiClasses.td
lisp.td
list-element-bitref.td
ListArgs.td
ListArgsSimple.td
listconcat.td
ListConversion.td
ListManip.td
ListOfList.td
ListSlices.td
lit.local.cfg
LoLoL.td
math.td
MultiClass.td
MultiClassDefName.td [TableGen] Resolve complex def names inside multiclasses 2015-05-21 04:32:56 +00:00
MultiClassInherit.td
MultiPat.td
nested-comment.td
NestedForeach.td
Paste.td
pr8330.td
SetTheory.td
SiblingForeach.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td [GlobalISel] Add a generic machine opcode for ADD. 2016-01-20 19:14:55 +00:00
trydecode-emission3.td [GlobalISel] Add a generic machine opcode for ADD. 2016-01-20 19:14:55 +00:00
trydecode-emission.td [GlobalISel] Add a generic machine opcode for ADD. 2016-01-20 19:14:55 +00:00
TwoLevelName.td Add test cases that will show the bug that was fixed in r256725. 2016-01-13 07:53:11 +00:00
UnsetBitInit.td
UnterminatedComment.td
usevalname.td
ValidIdentifiers.td