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aa2c5cf11c
Original message: Get rid of the ifdefs in TargetLowering. Introduce a new API used only by GlobalISel: CallLowering. This API will contain target hooks dedicated to call lowering. llvm-svn: 260998
114 lines
4.0 KiB
C++
114 lines
4.0 KiB
C++
//===-- llvm/lib/Target/AArch64/AArch64CallLowering.cpp - Call lowering ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64CallLowering.h"
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#include "AArch64ISelLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {
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}
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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bool AArch64CallLowering::LowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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return false;
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}
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bool AArch64CallLowering::LowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args,
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const SmallVectorImpl<unsigned> &VRegs) const {
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return false;
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}
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#else
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bool AArch64CallLowering::LowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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MachineInstr *Return = MIRBuilder.buildInstr(AArch64::RET_ReallyLR);
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assert(Return && "Unable to build a return instruction?!");
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assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
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if (VReg) {
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assert(Val->getType()->isIntegerTy() && "Type not supported yet");
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unsigned Size = Val->getType()->getPrimitiveSizeInBits();
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assert((Size == 64 || Size == 32) && "Size not supported yet");
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unsigned ResReg = (Size == 32) ? AArch64::W0 : AArch64::X0;
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// Set the insertion point to be right before Return.
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MIRBuilder.setInstr(*Return, /* Before */ true);
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MachineInstr *Copy =
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MIRBuilder.buildInstr(TargetOpcode::COPY, ResReg, VReg);
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(void)Copy;
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assert(Copy->getNextNode() == Return &&
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"The insertion did not happen where we expected");
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MachineInstrBuilder(MIRBuilder.getMF(), Return)
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.addReg(ResReg, RegState::Implicit);
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}
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return true;
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}
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bool AArch64CallLowering::LowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args,
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const SmallVectorImpl<unsigned> &VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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unsigned NumArgs = Args.size();
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Function::const_arg_iterator CurOrigArg = Args.begin();
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) {
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MVT ValVT = MVT::getVT(CurOrigArg->getType());
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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bool Res =
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AssignFn(i, ValVT, ValVT, CCValAssign::Full, ISD::ArgFlagsTy(), CCInfo);
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assert(!Res && "Call operand has unhandled type");
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(void)Res;
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}
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assert(ArgLocs.size() == Args.size() &&
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"We have a different number of location and args?!");
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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assert(VA.isRegLoc() && "Not yet implemented");
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// Transform the arguments in physical registers into virtual ones.
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MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
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MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg());
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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// We don't care about bitcast.
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break;
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case CCValAssign::AExt:
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case CCValAssign::SExt:
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case CCValAssign::ZExt:
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// Zero/Sign extend the register.
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assert(0 && "Not yet implemented");
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break;
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}
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}
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return true;
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}
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#endif
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