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74a8dfdced
Summary: This patch introduces command-line support for the Armv8.6-a architecture and assembly support for BFloat16. Details can be found https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a in addition to the GCC patch for the 8..6-a CLI: https://gcc.gnu.org/legacy-ml/gcc-patches/2019-11/msg02647.html In detail this patch - march options for armv8.6-a - BFloat16 assembly This is part of a patch series, starting with command-line and Bfloat16 assembly support. The subsequent patches will upstream intrinsics support for BFloat16, followed by Matrix Multiplication and the remaining Virtualization features of the armv8.6-a architecture. Based on work by: - labrinea - MarkMurrayARM - Luke Cheeseman - Javed Asbar - Mikhail Maltsev - Luke Geeson Reviewers: SjoerdMeijer, craig.topper, rjmccall, jfb, LukeGeeson Reviewed By: SjoerdMeijer Subscribers: stuij, kristof.beyls, hiraditya, dexonsmith, danielkiss, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D76062
43 lines
1.4 KiB
ArmAsm
43 lines
1.4 KiB
ArmAsm
// RUN: not llvm-mc -o - -triple=aarch64 -mattr=+sve,bf16 2>&1 %s | FileCheck %s
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bfmlalb z0.S, z1.H, z7.H[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmlalb z0.S, z1.H, z7.H[8]
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// CHECK-NEXT: ^
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bfmlalb z0.S, z1.H, z8.H[7]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmlalb z0.S, z1.H, z8.H[7]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z7.H[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z7.H[8]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z8.H[7]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z8.H[7]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z7.2h[2]
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// CHECK: error: invalid vector kind qualifier
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z7.2h[2]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z2.s[2]
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// CHECK: error: Invalid restricted vector register, expected z0.h..z7.h
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z2.s[2]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.s, z2.h[2]
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// CHECK: error: invalid element width
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// CHECK-NEXT: bfmlalt z0.S, z1.s, z2.h[2]
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// CHECK-NEXT: ^
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movprfx z0.s, p0/m, z7.s
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bfmlalt z0.s, z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx
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// CHECK-NEXT: bfmlalt z0.s, z1.h, z2.h
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// CHECK-NEXT: ^
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