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899b2f53e8
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:
faddv h0, p0.q, z1.h
This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:
.text
<stdin>:1:13: error: not expecting size suffix
cmpne p1.s, p0.b/z, z2.s, 0
^
A similar issue for SVE vector registers was fixed in:
https://reviews.llvm.org/D59636
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62942
llvm-svn: 362780
25 lines
827 B
ArmAsm
25 lines
827 B
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Unexpected type suffix
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pnext p0.b, p15.b, p0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: pnext p0.b, p15.b, p0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pnext p0.b, p15.q, p0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: pnext p0.b, p15.q, p0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Tied operands must match
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pnext p0.b, p15, p1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: pnext p0.b, p15, p1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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