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12cdca9076
Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
13 lines
593 B
ArmAsm
13 lines
593 B
ArmAsm
// RUN: not llvm-mc %s -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 -o /dev/null 2>&1 | FileCheck %s
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// Validate that only OpMask/Zero mark may immediately follow destination
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vfmsub213ps zmm8{rn-sae} {k2}, zmm8, zmm8
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// CHECK: error: Expected an op-mask register at this point
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vfmsub213ps zmm8{k2} {rn-sae}, zmm8, zmm8
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// CHECK: error: Expected a {z} mark at this point
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vfmsub213ps zmm8{rn-sae}, zmm8, zmm8
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// CHECK: error: Expected an op-mask register at this point
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vpcmpltd k5{k0}, zmm7, zmm24
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// CHECK: error: Register k0 can't be used as write mask
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