Daniel Sanders fe8b495815 [mips] Add cache and pref instructions ... Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900		2014-06-13 13:15:59 +00:00
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AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
AsmParser	Rearrange the CHECK lines in this test to make failure more obvious.	2014-06-10 20:16:47 +00:00
COFF	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Disassembler	[mips][mips64r6] Add bgec and bgeuc instructions	2014-06-12 11:47:44 +00:00
ELF	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
MachO	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Markup
Mips	[mips] Add cache and pref instructions	2014-06-13 13:15:59 +00:00
PowerPC	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
X86	[X86] AVX512: Add vmovntdqa	2014-06-10 16:39:53 +00:00