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7a3a160940
Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
53 lines
2.3 KiB
LLVM
53 lines
2.3 KiB
LLVM
; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
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target triple = "thumbv7-apple-ios"
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; <rdar://problem/10032939>
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;
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; The vector %v2 is built like this:
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;
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; %vreg6:ssub_1<def> = ...
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; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
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;
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; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
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; since it implicitly reads the ssub_1 sub-register.
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;
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; CHECK: f1
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; CHECK: vmov d0, r0, r0
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; CHECK: vldr s1, LCPI
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; The vector must be spilled:
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; CHECK: vstr d0,
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; CHECK: asm clobber d0
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; And reloaded after the asm:
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; CHECK: vldr [[D16:d[0-9]+]],
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; CHECK: vstr [[D16]], [r1]
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define void @f1(float %x, <2 x float>* %p) {
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%v1 = insertelement <2 x float> undef, float %x, i32 0
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%v2 = insertelement <2 x float> %v1, float 0x400921FB60000000, i32 1
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%y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
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store <2 x float> %v2, <2 x float>* %p, align 8
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ret void
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}
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; On the other hand, when the partial redef doesn't read the full register
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; because the bits are undef, we should rematerialize. The vector is now built
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; like this:
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;
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; %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>; mem:LD4[ConstantPool]
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;
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; The extra <imp-def> operand indicates that the instruction fully defines the
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; virtual register. It doesn't read the old value.
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;
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; CHECK: f2
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; CHECK: vldr s0, LCPI
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; The vector must not be spilled:
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; CHECK-NOT: vstr
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; CHECK: asm clobber d0
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; But instead rematerialize after the asm:
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; CHECK: vldr [[S0:s[0-9]+]], LCPI
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; CHECK: vstr [[D0:d[0-9]+]], [r0]
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define void @f2(<2 x float>* %p) {
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%v2 = insertelement <2 x float> undef, float 0x400921FB60000000, i32 0
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%y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
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store <2 x float> %v2, <2 x float>* %p, align 8
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ret void
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}
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