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b82983ef6a
These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. llvm-svn: 211247
30 lines
1.3 KiB
LLVM
30 lines
1.3 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone
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; SI-LABEL: @test_trig_preop_f64:
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; SI-DAG: BUFFER_LOAD_DWORD [[SEG:v[0-9]+]]
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; SI-DAG: BUFFER_LOAD_DWORDX2 [[SRC:v\[[0-9]+:[0-9]+\]]],
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; SI: V_TRIG_PREOP_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
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; SI: BUFFER_STORE_DWORDX2 [[RESULT]],
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; SI: S_ENDPGM
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define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%a = load double addrspace(1)* %aptr, align 8
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%b = load i32 addrspace(1)* %bptr, align 4
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%result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 %b) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: @test_trig_preop_f64_imm_segment:
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; SI: BUFFER_LOAD_DWORDX2 [[SRC:v\[[0-9]+:[0-9]+\]]],
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; SI: V_TRIG_PREOP_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
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; SI: BUFFER_STORE_DWORDX2 [[RESULT]],
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; SI: S_ENDPGM
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define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
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%a = load double addrspace(1)* %aptr, align 8
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%result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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