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99 lines
4.4 KiB
LLVM
99 lines
4.4 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck %s
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; SMRD load with an immediate offset.
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; CHECK-LABEL: @smrd0
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; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32 addrspace(2)* %ptr, i64 1
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%1 = load i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with the largest possible immediate offset.
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; CHECK-LABEL: @smrd1
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; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32 addrspace(2)* %ptr, i64 255
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%1 = load i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate.
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; CHECK-LABEL: @smrd2
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; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400
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; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32 addrspace(2)* %ptr, i64 256
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%1 = load i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with a 64-bit offset
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; CHECK-LABEL: @smrd3
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; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4
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; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0
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; FIXME: We don't need to copy these values to VGPRs
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; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]]
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; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]]
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; FIXME: We should be able to use S_LOAD_DWORD here
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; BUFFER_LOAD_DWORD v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v[[[VLO]]:[[VHI]]] + 0x0
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define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
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%1 = load i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load using the load.const intrinsic with an immediate offset
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; CHECK-LABEL: @smrd_load_const0
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; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
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define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load using the load.const intrinsic with an offset greater largest possible
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; immediate offset.
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; CHECK-LABEL: @smrd_load_const1
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; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load using the load.const intrinsic with the largetst possible
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; immediate offset.
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; CHECK-LABEL: @smrd_load_const2
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; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readnone }
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