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llvm-mirror/test/CodeGen/SPARC/spillsize.ll
Jakob Stoklund Olesen 45496cea60 Always let value types influence register classes.
When creating a virtual register for a def, the value type should be
used to pick the register class. If we only use the register class
constraint on the instruction, we might pick a too large register class.

Some registers can store values of different sizes. For example, the x86
xmm registers can hold f32, f64, and 128-bit vectors. The three
different value sizes are represented by register classes with identical
register sets: FR32, FR64, and VR128. These register classes have
different spill slot sizes, so it is important to use the right one.

The register class constraint on an instruction doesn't necessarily care
about the size of the value its defining. The value type determines
that.

This fixes a problem where InstrEmitter was picking 32-bit register
classes for 64-bit values on SPARC.

llvm-svn: 199187
2014-01-14 06:18:38 +00:00

26 lines
973 B
LLVM

; RUN: llc < %s -verify-machineinstrs | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64-S128"
target triple = "sparcv9"
; CHECK-LABEL: spill4
; This function spills two values: %p and the materialized large constant.
; Both must use 8-byte spill and fill instructions.
; CHECK: stx %{{..}}, [%fp+
; CHECK: stx %{{..}}, [%fp+
; CHECK: ldx [%fp+
; CHECK: ldx [%fp+
define void @spill4(i64* nocapture %p) {
entry:
%val0 = load i64* %p
%cmp0 = icmp ult i64 %val0, 385672958347594845
%cm80 = zext i1 %cmp0 to i64
store i64 %cm80, i64* %p, align 8
tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"()
%arrayidx1 = getelementptr inbounds i64* %p, i64 1
%val = load i64* %arrayidx1
%cmp = icmp ult i64 %val, 385672958347594845
%cm8 = select i1 %cmp, i64 10, i64 20
store i64 %cm8, i64* %arrayidx1, align 8
ret void
}