mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 03:53:04 +02:00
ff030064fb
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
28 lines
682 B
LLVM
28 lines
682 B
LLVM
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
|
|
; RUN: | FileCheck %s -check-prefix=CHECK-NONPIC
|
|
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
|
|
; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
|
|
|
|
@i = external thread_local global i32 ; <i32*> [#uses=2]
|
|
|
|
define i32 @f() {
|
|
; CHECK-NONPIC: f:
|
|
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
|
|
; CHECK-NONPIC: i(gottpoff)
|
|
; CHECK-PIC: f:
|
|
; CHECK-PIC: __tls_get_addr
|
|
entry:
|
|
%tmp1 = load i32* @i ; <i32> [#uses=1]
|
|
ret i32 %tmp1
|
|
}
|
|
|
|
define i32* @g() {
|
|
; CHECK-NONPIC: g:
|
|
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
|
|
; CHECK-NONPIC: i(gottpoff)
|
|
; CHECK-PIC: g:
|
|
; CHECK-PIC: __tls_get_addr
|
|
entry:
|
|
ret i32* @i
|
|
}
|