mirror of
https://github.com/RPCS3/llvm-mirror.git
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302c879f6c
This replicates existing and/or tests to also test variants using select. This should help us get a more accurate view on which optimizations we're missing if we disable the select -> and/or fold.
363 lines
10 KiB
LLVM
363 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; Check simplification of
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; (icmp sgt x, -1) & (icmp sgt/sge n, x) --> icmp ugt/uge n, x
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define i1 @test_and1(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and1(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sge i32 %x, 0
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%b = icmp slt i32 %x, %nn
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @test_and1_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and1_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sge i32 %x, 0
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%b = icmp slt i32 %x, %nn
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @test_and2(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and2(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sgt i32 %x, -1
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%b = icmp sle i32 %x, %nn
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @test_and2_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and2_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sgt i32 %x, -1
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%b = icmp sle i32 %x, %nn
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @test_and3(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and3(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sgt i32 %nn, %x
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%b = icmp sge i32 %x, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @test_and3_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and3_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sgt i32 %nn, %x
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%b = icmp sge i32 %x, 0
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @test_and4(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and4(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sge i32 %nn, %x
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%b = icmp sge i32 %x, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @test_and4_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_and4_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sge i32 %nn, %x
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%b = icmp sge i32 %x, 0
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @test_or1(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or1(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, 0
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%b = icmp sge i32 %x, %nn
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%c = or i1 %a, %b
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ret i1 %c
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}
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define i1 @test_or1_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or1_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, 0
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%b = icmp sge i32 %x, %nn
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%c = select i1 %a, i1 true, i1 %b
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ret i1 %c
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}
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define i1 @test_or2(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or2(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sle i32 %x, -1
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%b = icmp sgt i32 %x, %nn
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%c = or i1 %a, %b
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ret i1 %c
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}
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define i1 @test_or2_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or2_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sle i32 %x, -1
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%b = icmp sgt i32 %x, %nn
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%c = select i1 %a, i1 true, i1 %b
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ret i1 %c
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}
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define i1 @test_or3(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or3(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sle i32 %nn, %x
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%b = icmp slt i32 %x, 0
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%c = or i1 %a, %b
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ret i1 %c
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}
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define i1 @test_or3_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or3_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp sle i32 %nn, %x
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%b = icmp slt i32 %x, 0
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%c = select i1 %a, i1 true, i1 %b
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ret i1 %c
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}
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define i1 @test_or4(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or4(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %nn, %x
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%b = icmp slt i32 %x, 0
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%c = or i1 %a, %b
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ret i1 %c
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}
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define i1 @test_or4_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @test_or4_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %nn, %x
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%b = icmp slt i32 %x, 0
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%c = select i1 %a, i1 true, i1 %b
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ret i1 %c
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}
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; Negative tests
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define i1 @negative1(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative1(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], 0
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, %nn
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%b = icmp sgt i32 %x, 0 ; should be: icmp sge
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @negative1_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative1_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], 0
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, %nn
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%b = icmp sgt i32 %x, 0 ; should be: icmp sge
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @negative2(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative2(
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; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[N:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = icmp slt i32 %x, %n ; n can be negative
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%b = icmp sge i32 %x, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @negative2_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative2_logical(
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; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[N:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = icmp slt i32 %x, %n ; n can be negative
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%b = icmp sge i32 %x, 0
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @negative3(i32 %x, i32 %y, i32 %n) {
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; CHECK-LABEL: @negative3(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, %nn
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%b = icmp sge i32 %y, 0 ; should compare %x and not %y
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @negative3_logical(i32 %x, i32 %y, i32 %n) {
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; CHECK-LABEL: @negative3_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, %nn
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%b = icmp sge i32 %y, 0 ; should compare %x and not %y
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @negative4(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative4(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp ne i32 %x, %nn ; should be: icmp slt/sle
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%b = icmp sge i32 %x, 0
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%c = and i1 %a, %b
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ret i1 %c
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}
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define i1 @negative4_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative4_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1
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; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp ne i32 %x, %nn ; should be: icmp slt/sle
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%b = icmp sge i32 %x, 0
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%c = select i1 %a, i1 %b, i1 false
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ret i1 %c
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}
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define i1 @negative5(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative5(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1
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; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, %nn
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%b = icmp sge i32 %x, 0
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%c = or i1 %a, %b ; should be: and
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ret i1 %c
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}
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define i1 @negative5_logical(i32 %x, i32 %n) {
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; CHECK-LABEL: @negative5_logical(
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; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
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; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[NN]], [[X:%.*]]
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; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1
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; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%nn = and i32 %n, 2147483647
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%a = icmp slt i32 %x, %nn
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%b = icmp sge i32 %x, 0
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%c = select i1 %a, i1 true, i1 %b ; should be: and
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ret i1 %c
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}
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