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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
36 lines
1.0 KiB
LLVM
36 lines
1.0 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-macosx | FileCheck %s
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; PR10221
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;; The registers %x and %y must both spill across the finit call.
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;; Check that they are spilled early enough that not copies are needed for the
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;; fadd and fpext.
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; CHECK: pr10221
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; CHECK-NOT: movaps
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; CHECK: movss
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; CHECK-NEXT: movss
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; CHECK-NEXT: addss
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; CHECK-NEXT: cvtss2sd
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; CHECK-NEXT: finit
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define i32 @pr10221(float %x, float %y, i8** nocapture %_retval) nounwind uwtable ssp {
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entry:
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%add = fadd float %x, %y
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%conv = fpext float %add to double
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%call = tail call i32 @finit(double %conv) nounwind
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%tobool = icmp eq i32 %call, 0
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br i1 %tobool, label %return, label %if.end
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if.end: ; preds = %entry
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tail call void @foo(float %x, float %y) nounwind
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br label %return
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return: ; preds = %entry, %if.end
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%retval.0 = phi i32 [ 0, %if.end ], [ 5, %entry ]
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ret i32 %retval.0
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}
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declare i32 @finit(double)
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declare void @foo(float, float)
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