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18f71dad93
Summary: Avoids duplicating generated static helpers for calling convention analysis. This also means you can modify AArch64CallingConv.td without recompiling the AArch64ISelLowering.cpp monolith, so it provides faster incremental rebuilds. Saves 12K in llc.exe, but adds a new object file, which is large. Reviewers: efriedma, t.p.northover Subscribers: mgorny, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D56948 llvm-svn: 352430
390 lines
18 KiB
TableGen
390 lines
18 KiB
TableGen
//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for AArch64 architecture.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfAlign - Match of the original alignment of the arg
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class CCIfAlign<string Align, CCAction A> :
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CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
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/// CCIfBigEndian - Match only if we're in big endian mode.
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class CCIfBigEndian<CCAction A> :
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CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS64 Calling Convention
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//===----------------------------------------------------------------------===//
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let Entry = 1 in
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def CC_AArch64_AAPCS : CallingConv<[
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CCIfType<[iPTR], CCBitConvertToType<i64>>,
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
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// Big endian vectors must be passed as if they were 1-element vectors so that
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// their lanes are in a consistent order.
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CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
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CCBitConvertToType<f64>>>,
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CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
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CCBitConvertToType<f128>>>,
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// An SRet is passed in X8, not X0 like a normal pointer parameter.
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CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
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// Put ByVal arguments directly on the stack. Minimum size and alignment of a
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// slot is 64-bit.
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CCIfByVal<CCPassByVal<8, 8>>,
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// The 'nest' parameter, if any, is passed in X18.
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// Darwin uses X18 as the platform register and hence 'nest' isn't currently
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// supported there.
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CCIfNest<CCAssignToReg<[X18]>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>,
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// A SwiftError is passed in X21.
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CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
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CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
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// Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
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// up to eight each of GPR and FPR.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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// i128 is split to two i64s, we can't fit half to register X7.
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CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
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[X0, X1, X3, X5]>>>,
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// i128 is split to two i64s, and its stack alignment is 16 bytes.
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CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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// If more than will fit in registers, pass them on the stack instead.
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CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
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CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
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CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
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CCAssignToStack<8, 8>>,
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CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToStack<16, 16>>
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]>;
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let Entry = 1 in
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def RetCC_AArch64_AAPCS : CallingConv<[
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CCIfType<[iPTR], CCBitConvertToType<i64>>,
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
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CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
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// Big endian vectors must be passed as if they were 1-element vectors so that
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// their lanes are in a consistent order.
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CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
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CCBitConvertToType<f64>>>,
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CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
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CCBitConvertToType<f128>>>,
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
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]>;
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// Vararg functions on windows pass floats in integer registers
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let Entry = 1 in
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def CC_AArch64_Win64_VarArg : CallingConv<[
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CCIfType<[f16, f32], CCPromoteToType<f64>>,
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CCIfType<[f64], CCBitConvertToType<i64>>,
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CCDelegateTo<CC_AArch64_AAPCS>
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]>;
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// Darwin uses a calling convention which differs in only two ways
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// from the standard one at this level:
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// + i128s (i.e. split i64s) don't need even registers.
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// + Stack slots are sized as needed rather than being at least 64-bit.
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let Entry = 1 in
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def CC_AArch64_DarwinPCS : CallingConv<[
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CCIfType<[iPTR], CCBitConvertToType<i64>>,
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
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// An SRet is passed in X8, not X0 like a normal pointer parameter.
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CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
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// Put ByVal arguments directly on the stack. Minimum size and alignment of a
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// slot is 64-bit.
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CCIfByVal<CCPassByVal<8, 8>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>,
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// A SwiftError is passed in X21.
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CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
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CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
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// Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
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// up to eight each of GPR and FPR.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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// i128 is split to two i64s, we can't fit half to register X7.
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CCIfType<[i64],
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CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6],
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[W0, W1, W2, W3, W4, W5, W6]>>>,
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// i128 is split to two i64s, and its stack alignment is 16 bytes.
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CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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// If more than will fit in registers, pass them on the stack instead.
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CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,
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CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16", CCAssignToStack<2, 2>>,
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
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CCAssignToStack<8, 8>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToStack<16, 16>>
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]>;
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let Entry = 1 in
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def CC_AArch64_DarwinPCS_VarArg : CallingConv<[
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CCIfType<[iPTR], CCBitConvertToType<i64>>,
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
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CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Stack_Block">>,
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// Handle all scalar types as either i64 or f64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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CCIfType<[f16, f32], CCPromoteToType<f64>>,
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// Everything is on the stack.
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// i128 is split to two i64s, and its stack alignment is 16 bytes.
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CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
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CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToStack<8, 8>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToStack<16, 16>>
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]>;
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// The WebKit_JS calling convention only passes the first argument (the callee)
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// in register and the remaining arguments on stack. We allow 32bit stack slots,
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// so that WebKit can write partial values in the stack and define the other
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// 32bit quantity as undef.
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let Entry = 1 in
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def CC_AArch64_WebKit_JS : CallingConv<[
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// Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
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// Pass the remaining arguments on the stack instead.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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let Entry = 1 in
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def RetCC_AArch64_WebKit_JS : CallingConv<[
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM64 Calling Convention for GHC
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//===----------------------------------------------------------------------===//
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// This calling convention is specific to the Glasgow Haskell Compiler.
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// The only documentation is the GHC source code, specifically the C header
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// file:
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//
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// https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h
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//
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// which defines the registers for the Spineless Tagless G-Machine (STG) that
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// GHC uses to implement lazy evaluation. The generic STG machine has a set of
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// registers which are mapped to appropriate set of architecture specific
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// registers for each CPU architecture.
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//
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// The STG Machine is documented here:
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//
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// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode
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//
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// The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI
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// register mapping".
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let Entry = 1 in
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def CC_AArch64_GHC : CallingConv<[
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CCIfType<[iPTR], CCBitConvertToType<i64>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
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CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>,
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CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>,
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// Promote i8/i16/i32 arguments to i64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
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CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>>
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]>;
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// FIXME: LR is only callee-saved in the sense that *we* preserve it and are
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// presumably a callee to someone. External functions may not do so, but this
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// is currently safe since BL has LR as an implicit-def and what happens after a
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// tail call doesn't matter.
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//
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// It would be better to model its preservation semantics properly (create a
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// vreg on entry, use it in RET & tail call generation; make that vreg def if we
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// end up saving LR as part of a call frame). Watch this space...
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def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
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X23, X24, X25, X26, X27, X28,
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D8, D9, D10, D11,
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D12, D13, D14, D15)>;
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// Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
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// We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
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// and not (LR,FP) pairs.
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def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add FP, LR, X19, X20, X21, X22,
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X23, X24, X25, X26, X27, X28,
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D8, D9, D10, D11,
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D12, D13, D14, D15)>;
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// AArch64 PCS for vector functions (VPCS)
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// must (additionally) preserve full Q8-Q23 registers
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def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
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X23, X24, X25, X26, X27, X28,
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(sequence "Q%u", 8, 23))>;
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// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
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// 'this' and the pointer return value are both passed in X0 in these cases,
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// this can be partially modelled by treating X0 as a callee-saved register;
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// only the resulting RegMask is used; the SaveList is ignored
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//
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// (For generic ARM 64-bit ABI code, clang will not generate constructors or
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// destructors with 'this' returns, so this RegMask will not be used in that
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// case)
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def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
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def CSR_AArch64_AAPCS_SwiftError
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: CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>;
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// The function used by Darwin to obtain the address of a thread-local variable
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// guarantees more than a normal AAPCS function. x16 and x17 are used on the
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// fast path for calculation, but other registers except X0 (argument/return)
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// and LR (it is a call, after all) are preserved.
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def CSR_AArch64_TLS_Darwin
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: CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
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FP,
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(sequence "Q%u", 0, 31))>;
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// We can only handle a register pair with adjacent registers, the register pair
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// should belong to the same class as well. Since the access function on the
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// fast path calls a function that follows CSR_AArch64_TLS_Darwin,
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// CSR_AArch64_CXX_TLS_Darwin should be a subset of CSR_AArch64_TLS_Darwin.
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def CSR_AArch64_CXX_TLS_Darwin
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: CalleeSavedRegs<(add CSR_AArch64_AAPCS,
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(sub (sequence "X%u", 1, 28), X15, X16, X17, X18),
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(sequence "D%u", 0, 31))>;
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// CSRs that are handled by prologue, epilogue.
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def CSR_AArch64_CXX_TLS_Darwin_PE
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: CalleeSavedRegs<(add LR, FP)>;
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// CSRs that are handled explicitly via copies.
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def CSR_AArch64_CXX_TLS_Darwin_ViaCopy
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: CalleeSavedRegs<(sub CSR_AArch64_CXX_TLS_Darwin, LR, FP)>;
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// The ELF stub used for TLS-descriptor access saves every feasible
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// register. Only X0 and LR are clobbered.
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def CSR_AArch64_TLS_ELF
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: CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
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(sequence "Q%u", 0, 31))>;
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def CSR_AArch64_AllRegs
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: CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
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(sequence "X%u", 0, 28), FP, LR, SP,
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(sequence "B%u", 0, 31), (sequence "H%u", 0, 31),
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(sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
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(sequence "Q%u", 0, 31))>;
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def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>;
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def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS,
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(sequence "X%u", 9, 15))>;
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def CSR_AArch64_StackProbe_Windows
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: CalleeSavedRegs<(add (sequence "X%u", 0, 15),
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(sequence "X%u", 18, 28), FP, SP,
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(sequence "Q%u", 0, 31))>;
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// Variants of the standard calling conventions for shadow call stack.
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// These all preserve x18 in addition to any other registers.
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def CSR_AArch64_NoRegs_SCS
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: CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>;
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def CSR_AArch64_AllRegs_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>;
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def CSR_AArch64_CXX_TLS_Darwin_SCS
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: CalleeSavedRegs<(add CSR_AArch64_CXX_TLS_Darwin, X18)>;
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def CSR_AArch64_AAPCS_SwiftError_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>;
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def CSR_AArch64_RT_MostRegs_SCS
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: CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>;
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def CSR_AArch64_AAVPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>;
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def CSR_AArch64_AAPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>;
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