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ff992a6f20
Summary: MIPS32r6/MIPS64r6 support has not been added yet. inlineasm-cnstrnt-reg.ll: Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6 when -integrated-as is the default. We can't change the mnemonic since the LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no instructions that use LO. 2008-08-01-AsmInline.ll: Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit different code and this is a regression test. mips64instrs.ll and mips64muldiv.ll Check registers and the way the multiply is used in m1 divrem.ll Check registers and use multiple filecheck prefixes to limit redundancy Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida Reviewed By: matheusalmeida Subscribers: matheusalmeida Differential Revision: http://reviews.llvm.org/D3894 llvm-svn: 210656
190 lines
4.3 KiB
LLVM
190 lines
4.3 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s
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@gll0 = common global i64 0, align 8
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@gll1 = common global i64 0, align 8
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define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: f0:
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; ALL: daddu $2, ${{[45]}}, ${{[45]}}
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%add = add nsw i64 %a1, %a0
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ret i64 %add
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}
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define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: f1:
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; ALL: dsubu $2, $4, $5
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%sub = sub nsw i64 %a0, %a1
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ret i64 %sub
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}
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define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: f4:
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; ALL: and $2, ${{[45]}}, ${{[45]}}
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%and = and i64 %a1, %a0
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ret i64 %and
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}
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define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: f5:
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; ALL: or $2, ${{[45]}}, ${{[45]}}
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%or = or i64 %a1, %a0
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ret i64 %or
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}
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define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: f6:
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; ALL: xor $2, ${{[45]}}, ${{[45]}}
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%xor = xor i64 %a1, %a0
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ret i64 %xor
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}
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
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; ALL-LABEL: f7:
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; ALL: daddiu $2, $4, 20
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%add = add nsw i64 %a0, 20
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ret i64 %add
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
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; ALL-LABEL: f8:
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; ALL: daddiu $2, $4, -20
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%sub = add nsw i64 %a0, -20
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ret i64 %sub
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}
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define i64 @f9(i64 %a0) nounwind readnone {
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entry:
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; ALL-LABEL: f9:
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; ALL: andi $2, $4, 20
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%and = and i64 %a0, 20
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ret i64 %and
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}
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define i64 @f10(i64 %a0) nounwind readnone {
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entry:
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; ALL-LABEL: f10:
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; ALL: ori $2, $4, 20
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%or = or i64 %a0, 20
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ret i64 %or
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}
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define i64 @f11(i64 %a0) nounwind readnone {
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entry:
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; ALL-LABEL: f11:
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; ALL: xori $2, $4, 20
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%xor = xor i64 %a0, 20
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ret i64 %xor
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}
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define i64 @f12(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f12:
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; ALL: mult ${{[45]}}, ${{[45]}}
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%mul = mul nsw i64 %b, %a
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ret i64 %mul
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}
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define i64 @f13(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f13:
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; ALL: mult ${{[45]}}, ${{[45]}}
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%mul = mul i64 %b, %a
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ret i64 %mul
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}
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define i64 @f14(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f14:
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; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
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; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
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; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
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; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
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; ALL: ddiv $zero, $[[T0]], $[[T1]]
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; ALL: teq $[[T1]], $zero, 7
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; ALL: mflo $2
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%0 = load i64* @gll0, align 8
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%1 = load i64* @gll1, align 8
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%div = sdiv i64 %0, %1
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ret i64 %div
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}
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define i64 @f15() nounwind readnone {
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entry:
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; ALL-LABEL: f15:
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; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
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; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
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; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
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; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
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; ALL: ddivu $zero, $[[T0]], $[[T1]]
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; ALL: teq $[[T1]], $zero, 7
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; ALL: mflo $2
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%0 = load i64* @gll0, align 8
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%1 = load i64* @gll1, align 8
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%div = udiv i64 %0, %1
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ret i64 %div
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}
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define i64 @f16(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f16:
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; ALL: ddiv $zero, $4, $5
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; ALL: teq $5, $zero, 7
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; ALL: mfhi $2
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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define i64 @f17(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f17:
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; ALL: ddivu $zero, $4, $5
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; ALL: teq $5, $zero, 7
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; ALL: mfhi $2
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @f18(i64 %X) nounwind readnone {
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entry:
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; ALL-LABEL: f18:
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; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
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; MIPS4-NOT: dclz
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; MIPS64: dclz $2, $4
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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define i64 @f19(i64 %X) nounwind readnone {
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entry:
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; ALL-LABEL: f19:
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; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
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; MIPS4-NOT: dclo
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; MIPS64: dclo $2, $4
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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}
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define i64 @f20(i64 %a, i64 %b) nounwind readnone {
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entry:
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; ALL-LABEL: f20:
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; ALL: nor $2, ${{[45]}}, ${{[45]}}
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%or = or i64 %b, %a
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%neg = xor i64 %or, -1
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ret i64 %neg
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}
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