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Summary: MIPS32r6/MIPS64r6 support has not been added yet. inlineasm-cnstrnt-reg.ll: Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6 when -integrated-as is the default. We can't change the mnemonic since the LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no instructions that use LO. 2008-08-01-AsmInline.ll: Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit different code and this is a regression test. mips64instrs.ll and mips64muldiv.ll Check registers and the way the multiply is used in m1 divrem.ll Check registers and use multiple filecheck prefixes to limit redundancy Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida Reviewed By: matheusalmeida Subscribers: matheusalmeida Differential Revision: http://reviews.llvm.org/D3894 llvm-svn: 210656
65 lines
1.6 KiB
LLVM
65 lines
1.6 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL
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define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: m0:
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; ALL: dmult ${{[45]}}, ${{[45]}}
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; ALL: mflo $2
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%mul = mul i64 %a1, %a0
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ret i64 %mul
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}
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define i64 @m1(i64 %a) nounwind readnone {
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entry:
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; ALL-LABEL: m1:
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; ALL: lui $[[T0:[0-9]+]], 21845
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; ALL: addiu $[[T0]], $[[T0]], 21845
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; ALL: dsll $[[T0]], $[[T0]], 16
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; ALL: addiu $[[T0]], $[[T0]], 21845
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; ALL: dsll $[[T0]], $[[T0]], 16
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; ALL: addiu $[[T0]], $[[T0]], 21846
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; ALL: dmult ${{[45]}}, $[[T0]]
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; ALL: mfhi $[[T1:[0-9]+]]
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; ALL: dsrl $2, $[[T1]], 63
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; ALL: daddu $2, $[[T1]], $2
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%div = sdiv i64 %a, 3
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ret i64 %div
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}
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define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d0:
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; ALL: ddivu $zero, $4, $5
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; ALL: mflo $2
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%div = udiv i64 %a0, %a1
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ret i64 %div
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}
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define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d1:
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; ALL: ddiv $zero, $4, $5
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; ALL: mflo $2
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%div = sdiv i64 %a0, %a1
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ret i64 %div
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}
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define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d2:
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; ALL: ddivu $zero, $4, $5
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; ALL: mfhi $2
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%rem = urem i64 %a0, %a1
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ret i64 %rem
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}
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define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d3:
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; ALL: ddiv $zero, $4, $5
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; ALL: mfhi $2
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%rem = srem i64 %a0, %a1
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ret i64 %rem
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}
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