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620 lines
15 KiB
LLVM
620 lines
15 KiB
LLVM
; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck -check-prefix=CHECK-ORIGINS %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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; Check the presence of __msan_init
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; CHECK: @llvm.global_ctors {{.*}} @__msan_init
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; Check the presence and the linkage type of __msan_track_origins
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; CHECK: @__msan_track_origins = weak_odr constant i32 0
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; Check instrumentation of stores
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define void @Store(i32* nocapture %p, i32 %x) nounwind uwtable {
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entry:
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store i32 %x, i32* %p, align 4
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ret void
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}
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; CHECK: @Store
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; CHECK: load {{.*}} @__msan_param_tls
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; CHECK: store
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; CHECK: store
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; CHECK: ret void
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; CHECK-ORIGINS: @Store
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; CHECK-ORIGINS: load {{.*}} @__msan_param_tls
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; CHECK-ORIGINS: store
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; CHECK-ORIGINS: icmp
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; CHECK-ORIGINS: br i1
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; CHECK-ORIGINS: <label>
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; CHECK-ORIGINS: store
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; CHECK-ORIGINS: br label
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; CHECK-ORIGINS: <label>
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; CHECK-ORIGINS: store
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; CHECK-ORIGINS: ret void
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; Check instrumentation of aligned stores
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; Shadow store has the same alignment as the original store; origin store
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; does not specify explicit alignment.
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define void @AlignedStore(i32* nocapture %p, i32 %x) nounwind uwtable {
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entry:
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store i32 %x, i32* %p, align 32
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ret void
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}
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; CHECK: @AlignedStore
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; CHECK: load {{.*}} @__msan_param_tls
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; CHECK: store {{.*}} align 32
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; CHECK: store {{.*}} align 32
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; CHECK: ret void
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; CHECK-ORIGINS: @AlignedStore
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; CHECK-ORIGINS: load {{.*}} @__msan_param_tls
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; CHECK-ORIGINS: store {{.*}} align 32
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; CHECK-ORIGINS: icmp
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; CHECK-ORIGINS: br i1
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; CHECK-ORIGINS: <label>
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; CHECK-ORIGINS: store {{.*}} align 32
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; CHECK-ORIGINS: br label
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; CHECK-ORIGINS: <label>
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; CHECK-ORIGINS: store {{.*}} align 32
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; CHECK-ORIGINS: ret void
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; load followed by cmp: check that we load the shadow and call __msan_warning.
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define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable {
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entry:
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%0 = load i32* %a, align 4
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%tobool = icmp eq i32 %0, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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tail call void (...)* @foo() nounwind
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br label %if.end
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if.end: ; preds = %entry, %if.then
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ret void
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}
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declare void @foo(...)
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; CHECK: @LoadAndCmp
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; CHECK: = load
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; CHECK: = load
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; CHECK: call void @__msan_warning_noreturn()
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; CHECK-NEXT: call void asm sideeffect
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; CHECK-NEXT: unreachable
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; CHECK: ret void
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; Check that we store the shadow for the retval.
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define i32 @ReturnInt() nounwind uwtable readnone {
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entry:
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ret i32 123
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}
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; CHECK: @ReturnInt
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; CHECK: store i32 0,{{.*}}__msan_retval_tls
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; CHECK: ret i32
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; Check that we get the shadow for the retval.
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define void @CopyRetVal(i32* nocapture %a) nounwind uwtable {
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entry:
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%call = tail call i32 @ReturnInt() nounwind
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store i32 %call, i32* %a, align 4
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ret void
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}
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; CHECK: @CopyRetVal
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; CHECK: load{{.*}}__msan_retval_tls
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; CHECK: store
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; CHECK: store
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; CHECK: ret void
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; Check that we generate PHIs for shadow.
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define void @FuncWithPhi(i32* nocapture %a, i32* %b, i32* nocapture %c) nounwind uwtable {
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entry:
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%tobool = icmp eq i32* %b, null
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%0 = load i32* %b, align 4
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br label %if.end
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if.else: ; preds = %entry
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%1 = load i32* %c, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%t.0 = phi i32 [ %0, %if.then ], [ %1, %if.else ]
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store i32 %t.0, i32* %a, align 4
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ret void
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}
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; CHECK: @FuncWithPhi
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; CHECK: = phi
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; CHECK-NEXT: = phi
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; CHECK: store
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; CHECK: store
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; CHECK: ret void
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; Compute shadow for "x << 10"
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define void @ShlConst(i32* nocapture %x) nounwind uwtable {
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entry:
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%0 = load i32* %x, align 4
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%1 = shl i32 %0, 10
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store i32 %1, i32* %x, align 4
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ret void
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}
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; CHECK: @ShlConst
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; CHECK: = load
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; CHECK: = load
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; CHECK: shl
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; CHECK: shl
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; CHECK: store
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; CHECK: store
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; CHECK: ret void
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; Compute shadow for "10 << x": it should have 'sext i1'.
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define void @ShlNonConst(i32* nocapture %x) nounwind uwtable {
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entry:
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%0 = load i32* %x, align 4
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%1 = shl i32 10, %0
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store i32 %1, i32* %x, align 4
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ret void
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}
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; CHECK: @ShlNonConst
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; CHECK: = load
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; CHECK: = load
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; CHECK: = sext i1
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; CHECK: store
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; CHECK: store
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; CHECK: ret void
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; SExt
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define void @SExt(i32* nocapture %a, i16* nocapture %b) nounwind uwtable {
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entry:
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%0 = load i16* %b, align 2
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%1 = sext i16 %0 to i32
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store i32 %1, i32* %a, align 4
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ret void
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}
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; CHECK: @SExt
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; CHECK: = load
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; CHECK: = load
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; CHECK: = sext
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; CHECK: = sext
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; CHECK: store
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; CHECK: store
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; CHECK: ret void
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; memset
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define void @MemSet(i8* nocapture %x) nounwind uwtable {
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entry:
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call void @llvm.memset.p0i8.i64(i8* %x, i8 42, i64 10, i32 1, i1 false)
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ret void
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}
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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; CHECK: @MemSet
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; CHECK: call i8* @__msan_memset
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; CHECK: ret void
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; memcpy
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define void @MemCpy(i8* nocapture %x, i8* nocapture %y) nounwind uwtable {
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entry:
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i32 1, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; CHECK: @MemCpy
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; CHECK: call i8* @__msan_memcpy
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; CHECK: ret void
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; memmove is lowered to a call
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define void @MemMove(i8* nocapture %x, i8* nocapture %y) nounwind uwtable {
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entry:
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call void @llvm.memmove.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i32 1, i1 false)
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ret void
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}
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declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; CHECK: @MemMove
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; CHECK: call i8* @__msan_memmove
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; CHECK: ret void
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; Check that we propagate shadow for "select"
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define i32 @Select(i32 %a, i32 %b, i32 %c) nounwind uwtable readnone {
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entry:
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%tobool = icmp ne i32 %c, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; CHECK: @Select
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; CHECK: select
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; CHECK-NEXT: select
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; CHECK: ret i32
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; Check that we propagate origin for "select" with vector condition.
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; Select condition is flattened to i1, which is then used to select one of the
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; argument origins.
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define <8 x i16> @SelectVector(<8 x i16> %a, <8 x i16> %b, <8 x i1> %c) nounwind uwtable readnone {
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entry:
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%cond = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %cond
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}
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; CHECK-ORIGINS: @SelectVector
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; CHECK-ORIGINS: bitcast <8 x i1> {{.*}} to i8
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; CHECK-ORIGINS: icmp ne i8
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; CHECK-ORIGINS: select i1
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; CHECK-ORIGINS: ret <8 x i16>
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define i8* @IntToPtr(i64 %x) nounwind uwtable readnone {
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entry:
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%0 = inttoptr i64 %x to i8*
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ret i8* %0
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}
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; CHECK: @IntToPtr
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; CHECK: load i64*{{.*}}__msan_param_tls
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; CHECK-NEXT: inttoptr
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; CHECK-NEXT: store i64{{.*}}__msan_retval_tls
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; CHECK: ret i8
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define i8* @IntToPtr_ZExt(i16 %x) nounwind uwtable readnone {
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entry:
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%0 = inttoptr i16 %x to i8*
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ret i8* %0
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}
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; CHECK: @IntToPtr_ZExt
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; CHECK: zext
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; CHECK-NEXT: inttoptr
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; CHECK: ret i8
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; Check that we insert exactly one check on udiv
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; (2nd arg shadow is checked, 1st arg shadow is propagated)
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define i32 @Div(i32 %a, i32 %b) nounwind uwtable readnone {
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entry:
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%div = udiv i32 %a, %b
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ret i32 %div
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}
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; CHECK: @Div
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; CHECK: icmp
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; CHECK: call void @__msan_warning
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; CHECK-NOT: icmp
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; CHECK: udiv
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; CHECK-NOT: icmp
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; CHECK: ret i32
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; Check that we propagate shadow for x<0, x>=0, etc (i.e. sign bit tests)
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define zeroext i1 @ICmpSLT(i32 %x) nounwind uwtable readnone {
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%1 = icmp slt i32 %x, 0
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ret i1 %1
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}
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; CHECK: @ICmpSLT
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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define zeroext i1 @ICmpSGE(i32 %x) nounwind uwtable readnone {
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%1 = icmp sge i32 %x, 0
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ret i1 %1
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}
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; CHECK: @ICmpSGE
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sge
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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define zeroext i1 @ICmpSGT(i32 %x) nounwind uwtable readnone {
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%1 = icmp sgt i32 0, %x
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ret i1 %1
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}
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; CHECK: @ICmpSGT
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sgt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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define zeroext i1 @ICmpSLE(i32 %x) nounwind uwtable readnone {
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%1 = icmp sle i32 0, %x
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ret i1 %1
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}
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; CHECK: @ICmpSLE
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; CHECK: icmp slt
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp sle
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i1
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; Check that we propagate shadow for x<0, x>=0, etc (i.e. sign bit tests)
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; of the vector arguments.
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define <2 x i1> @ICmpSLT_vector(<2 x i32*> %x) nounwind uwtable readnone {
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%1 = icmp slt <2 x i32*> %x, zeroinitializer
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ret <2 x i1> %1
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}
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; CHECK: @ICmpSLT_vector
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; CHECK: icmp slt <2 x i64>
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; CHECK-NOT: call void @__msan_warning
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; CHECK: icmp slt <2 x i32*>
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret <2 x i1>
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; Check that we propagate shadow for x == y comparison.
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; This is a bit complex. See the comment in handleEqualityComparison.
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define i1 @ICmpEQ(i32 %x, i32 %y) nounwind uwtable readnone {
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%1 = icmp eq i32 %x, %y
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ret i1 %1
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}
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; CHECK: @ICmpEQ
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; CHECK: xor i32 %x, %y
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; CHECK: or i32
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; CHECK: xor i32
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; CHECK: and i32
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; CHECK: icmp eq i32
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; CHECK: icmp ne i32
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; CHECK: and i1
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; CHECK: icmp eq i32 %x, %y
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; CHECK: ret i1
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define <2 x i1> @ICmpEQ_vector(<2 x i32> %x, <2 x i32> %y) nounwind uwtable readnone {
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%1 = icmp eq <2 x i32> %x, %y
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ret <2 x i1> %1
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}
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; CHECK: @ICmpEQ_vector
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; CHECK: xor <2 x i32> %x, %y
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; CHECK: or <2 x i32>
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; CHECK: xor <2 x i32>
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; CHECK: and <2 x i32>
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; CHECK: icmp eq <2 x i32>
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; CHECK: icmp ne <2 x i32>
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; CHECK: and <2 x i1>
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; CHECK: icmp eq <2 x i32> %x, %y
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; CHECK: ret <2 x i1>
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define <2 x i1> @ICmpEQ_pointer_vector(<2 x i32*> %x, <2 x i32*> %y) nounwind uwtable readnone {
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%1 = icmp eq <2 x i32*> %x, %y
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ret <2 x i1> %1
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}
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; CHECK: @ICmpEQ_pointer_vector
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; CHECK: ptrtoint <2 x i32*> %x to <2 x i64>
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; CHECK: ptrtoint <2 x i32*> %y to <2 x i64>
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; CHECK: xor <2 x i64>
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; CHECK: or <2 x i64>
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; CHECK: xor <2 x i64>
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; CHECK: and <2 x i64>
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; CHECK: icmp eq <2 x i64>
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; CHECK: icmp ne <2 x i64>
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; CHECK: and <2 x i1>
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; CHECK: icmp eq <2 x i32*> %x, %y
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; CHECK: ret <2 x i1>
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; Check that loads of shadow have the same aligment as the original loads.
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; Check that loads of origin have the aligment of max(4, original alignment).
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define i32 @ShadowLoadAlignmentLarge() nounwind uwtable {
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%y = alloca i32, align 64
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%1 = load volatile i32* %y, align 64
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ret i32 %1
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}
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; CHECK: @ShadowLoadAlignmentLarge
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; CHECK: load i32* {{.*}} align 64
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; CHECK: load volatile i32* {{.*}} align 64
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; CHECK: ret i32
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define i32 @ShadowLoadAlignmentSmall() nounwind uwtable {
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%y = alloca i32, align 2
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%1 = load volatile i32* %y, align 2
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ret i32 %1
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}
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; CHECK: @ShadowLoadAlignmentSmall
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; CHECK: load i32* {{.*}} align 2
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; CHECK: load volatile i32* {{.*}} align 2
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; CHECK: ret i32
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; CHECK-ORIGINS: @ShadowLoadAlignmentSmall
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; CHECK-ORIGINS: load i32* {{.*}} align 2
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; CHECK-ORIGINS: load i32* {{.*}} align 4
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; CHECK-ORIGINS: load volatile i32* {{.*}} align 2
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; CHECK-ORIGINS: ret i32
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; Test vector manipulation instructions.
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; Check that the same bit manipulation is applied to the shadow values.
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; Check that there is a zero test of the shadow of %idx argument, where present.
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define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) {
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%x = extractelement <4 x i32> %vec, i32 %idx
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ret i32 %x
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}
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; CHECK: @ExtractElement
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; CHECK: extractelement
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; CHECK: call void @__msan_warning
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; CHECK: extractelement
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; CHECK: ret i32
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define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) {
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%vec1 = insertelement <4 x i32> %vec, i32 %x, i32 %idx
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ret <4 x i32> %vec1
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}
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; CHECK: @InsertElement
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; CHECK: insertelement
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; CHECK: call void @__msan_warning
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; CHECK: insertelement
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; CHECK: ret <4 x i32>
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define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) {
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%vec2 = shufflevector <4 x i32> %vec, <4 x i32> %vec1,
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<4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
|
ret <4 x i32> %vec2
|
|
}
|
|
|
|
; CHECK: @ShuffleVector
|
|
; CHECK: shufflevector
|
|
; CHECK-NOT: call void @__msan_warning
|
|
; CHECK: shufflevector
|
|
; CHECK: ret <4 x i32>
|
|
|
|
|
|
; Test bswap intrinsic instrumentation
|
|
define i32 @BSwap(i32 %x) nounwind uwtable readnone {
|
|
%y = tail call i32 @llvm.bswap.i32(i32 %x)
|
|
ret i32 %y
|
|
}
|
|
|
|
declare i32 @llvm.bswap.i32(i32) nounwind readnone
|
|
|
|
; CHECK: @BSwap
|
|
; CHECK-NOT: call void @__msan_warning
|
|
; CHECK: @llvm.bswap.i32
|
|
; CHECK-NOT: call void @__msan_warning
|
|
; CHECK: @llvm.bswap.i32
|
|
; CHECK-NOT: call void @__msan_warning
|
|
; CHECK: ret i32
|
|
|
|
|
|
; Store intrinsic.
|
|
|
|
define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable {
|
|
call void @llvm.x86.sse.storeu.ps(i8* %p, <4 x float> %x)
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
|
|
|
|
; CHECK: @StoreIntrinsic
|
|
; CHECK-NOT: br
|
|
; CHECK-NOT: = or
|
|
; CHECK: store <4 x i32> {{.*}} align 1
|
|
; CHECK: call void @llvm.x86.sse.storeu.ps
|
|
; CHECK: ret void
|
|
|
|
|
|
; Load intrinsic.
|
|
|
|
define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable {
|
|
%call = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p)
|
|
ret <16 x i8> %call
|
|
}
|
|
|
|
declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
|
|
|
|
; CHECK: @LoadIntrinsic
|
|
; CHECK: load <16 x i8>* {{.*}} align 1
|
|
; CHECK-NOT: br
|
|
; CHECK-NOT: = or
|
|
; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq
|
|
; CHECK: store <16 x i8> {{.*}} @__msan_retval_tls
|
|
; CHECK: ret <16 x i8>
|
|
|
|
; CHECK-ORIGINS: @LoadIntrinsic
|
|
; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32* {{.*}}
|
|
; CHECK-ORIGINS: call <16 x i8> @llvm.x86.sse3.ldu.dq
|
|
; CHECK-ORIGINS: store i32 {{.*}}[[ORIGIN]], i32* @__msan_retval_origin_tls
|
|
; CHECK-ORIGINS: ret <16 x i8>
|
|
|
|
|
|
; Simple NoMem intrinsic
|
|
; Check that shadow is OR'ed, and origin is Select'ed
|
|
; And no shadow checks!
|
|
|
|
define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable {
|
|
%call = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b)
|
|
ret <8 x i16> %call
|
|
}
|
|
|
|
declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
|
|
|
|
; CHECK: @Paddsw128
|
|
; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
|
|
; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
|
|
; CHECK-NEXT: = or <8 x i16>
|
|
; CHECK-NEXT: call <8 x i16> @llvm.x86.sse2.padds.w
|
|
; CHECK-NEXT: store <8 x i16> {{.*}} @__msan_retval_tls
|
|
; CHECK-NEXT: ret <8 x i16>
|
|
|
|
; CHECK-ORIGINS: @Paddsw128
|
|
; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
|
|
; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
|
|
; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128
|
|
; CHECK-ORIGINS-NEXT: = icmp ne i128 {{.*}}, 0
|
|
; CHECK-ORIGINS-NEXT: = select i1 {{.*}}, i32 {{.*}}, i32
|
|
; CHECK-ORIGINS: call <8 x i16> @llvm.x86.sse2.padds.w
|
|
; CHECK-ORIGINS: store i32 {{.*}} @__msan_retval_origin_tls
|
|
; CHECK-ORIGINS: ret <8 x i16>
|
|
|
|
|
|
; Test handling of vectors of pointers.
|
|
; Check that shadow of such vector is a vector of integers.
|
|
|
|
define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable {
|
|
%x = load <8 x i8*>* %p
|
|
ret <8 x i8*> %x
|
|
}
|
|
|
|
; CHECK: @VectorOfPointers
|
|
; CHECK: load <8 x i64>*
|
|
; CHECK: load <8 x i8*>*
|
|
; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls
|
|
; CHECK: ret <8 x i8*>
|
|
|
|
; Test handling of va_copy.
|
|
|
|
declare void @llvm.va_copy(i8*, i8*) nounwind
|
|
|
|
define void @VACopy(i8* %p1, i8* %p2) nounwind uwtable {
|
|
call void @llvm.va_copy(i8* %p1, i8* %p2) nounwind
|
|
ret void
|
|
}
|
|
|
|
; CHECK: @VACopy
|
|
; CHECK: call void @llvm.memset.p0i8.i64({{.*}}, i8 0, i64 24, i32 8, i1 false)
|
|
; CHECK: ret void
|