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3daeb462cb
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Enable these fp vmlx codegen changes for Cortex-A9.
llvm-svn: 129775
121 lines
3.8 KiB
C++
121 lines
3.8 KiB
C++
//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMHazardRecognizer.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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const TargetRegisterInfo &TRI) {
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// FIXME: Detect integer instructions properly.
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned Domain = TID.TSFlags & ARMII::DomainMask;
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if (TID.mayStore())
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return false;
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unsigned Opcode = TID.getOpcode();
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if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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return false;
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}
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ScheduleHazardRecognizer::HazardType
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ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugValue()) {
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if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
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return Hazard;
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// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
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// a VMLA / VMLS will cause 4 cycle stall.
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const TargetInstrDesc &TID = MI->getDesc();
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if (LastMI && (TID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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MachineInstr *DefMI = LastMI;
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const TargetInstrDesc &LastTID = LastMI->getDesc();
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// Skip over one non-VFP / NEON instruction.
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if (!LastTID.isBarrier() &&
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// On A9, AGU and NEON/FPU are muxed.
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!(STI.isCortexA9() && (LastTID.mayLoad() || LastTID.mayStore())) &&
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(LastTID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
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MachineBasicBlock::iterator I = LastMI;
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if (I != LastMI->getParent()->begin()) {
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I = llvm::prior(I);
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DefMI = &*I;
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}
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}
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if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
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(TII.canCauseFpMLxStall(MI->getOpcode()) ||
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hasRAWHazard(DefMI, MI, TRI))) {
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// Try to schedule another instruction for the next 4 cycles.
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if (FpMLxStalls == 0)
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FpMLxStalls = 4;
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return Hazard;
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}
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}
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}
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return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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void ARMHazardRecognizer::Reset() {
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LastMI = 0;
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FpMLxStalls = 0;
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ITBlockSize = 0;
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ScoreboardHazardRecognizer::Reset();
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}
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void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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unsigned Opcode = MI->getOpcode();
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if (ITBlockSize) {
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--ITBlockSize;
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} else if (Opcode == ARM::t2IT) {
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unsigned Mask = MI->getOperand(1).getImm();
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unsigned NumTZ = CountTrailingZeros_32(Mask);
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assert(NumTZ <= 3 && "Invalid IT mask!");
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ITBlockSize = 4 - NumTZ;
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MachineBasicBlock::iterator I = MI;
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for (unsigned i = 0; i < ITBlockSize; ++i) {
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// Advance to the next instruction, skipping any dbg_value instructions.
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do {
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++I;
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} while (I->isDebugValue());
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ITBlockMIs[ITBlockSize-1-i] = &*I;
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}
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}
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if (!MI->isDebugValue()) {
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LastMI = MI;
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FpMLxStalls = 0;
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}
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ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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void ARMHazardRecognizer::AdvanceCycle() {
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if (FpMLxStalls && --FpMLxStalls == 0)
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// Stalled for 4 cycles but still can't schedule any other instructions.
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LastMI = 0;
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ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void ARMHazardRecognizer::RecedeCycle() {
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llvm_unreachable("reverse ARM hazard checking unsupported");
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}
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