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- Fixed PPU G_3f_0 Decoder.
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@ -70,18 +70,6 @@ namespace PPU_instr
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//This field is used to specify a bit in the CR, or in the FPSCR, as the destination of the result of an instruction
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//This field is used to specify a bit in the CR, or in the FPSCR, as the destination of the result of an instruction
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static CodeField<6, 10> CRBD(FIELD_R_CR);
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static CodeField<6, 10> CRBD(FIELD_R_CR);
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//
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static CodeField<6, 10> BT;
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//
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static CodeField<11, 15> BA;
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//
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static CodeField<16, 20> BB;
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//
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static CodeField<6, 10> BF;
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//This field is used to specify options for the branch conditional instructions
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//This field is used to specify options for the branch conditional instructions
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static CodeField<6, 10> BO;
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static CodeField<6, 10> BO;
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@ -158,7 +146,7 @@ namespace PPU_instr
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static CodeField<6, 10> FRS;
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static CodeField<6, 10> FRS;
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//
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//
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static CodeField<7, 14> FLM;
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static CodeField<7, 14> FM;
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//This field is used to specify an FPR as a source
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//This field is used to specify an FPR as a source
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static CodeField<11, 15> FRA(FIELD_R_FPR);
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static CodeField<11, 15> FRA(FIELD_R_FPR);
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@ -602,12 +590,12 @@ namespace PPU_instr
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bind_instr(g3f_0_list, FCTID, FRD, FRB, RC);
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bind_instr(g3f_0_list, FCTID, FRD, FRB, RC);
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bind_instr(g3f_0_list, FCTIDZ, FRD, FRB, RC);
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bind_instr(g3f_0_list, FCTIDZ, FRD, FRB, RC);
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bind_instr(g3f_0_list, MTFSB1, BT, RC);
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bind_instr(g3f_0_list, MTFSB1, CRBD, RC);
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bind_instr(g3f_0_list, MCRFS, BF, BFA);
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bind_instr(g3f_0_list, MCRFS, CRFD, CRFS);
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bind_instr(g3f_0_list, MTFSB0, BT, RC);
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bind_instr(g3f_0_list, MTFSB0, CRBD, RC);
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bind_instr(g3f_0_list, MTFSFI, CRFD, I, RC);
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bind_instr(g3f_0_list, MTFSFI, CRBD, I, RC);
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bind_instr(g3f_0_list, MFFS, FRD, RC);
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bind_instr(g3f_0_list, MFFS, FRD, RC);
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bind_instr(g3f_0_list, MTFSF, FLM, FRB, RC);
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bind_instr(g3f_0_list, MTFSF, FM, FRB, RC);
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#undef bind_instr
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#undef bind_instr
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};
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};
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@ -3286,26 +3286,42 @@ private:
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Memory.Write64(addr, CPU.GPR[rs]);
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Memory.Write64(addr, CPU.GPR[rs]);
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CPU.GPR[ra] = addr;
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CPU.GPR[ra] = addr;
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}
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}
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void MTFSB1(u32 bt, bool rc)
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void MTFSB1(u32 crbd, bool rc)
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{
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{
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UNIMPLEMENTED();
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u64 mask = (1ULL << crbd);
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CPU.FPSCR.FPSCR |= mask;
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if(rc) UNIMPLEMENTED();
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}
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}
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void MCRFS(u32 bf, u32 bfa)
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void MCRFS(u32 crbd, u32 crbs)
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{
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{
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UNIMPLEMENTED();
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u64 mask = (1ULL << crbd);
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CPU.CR.CR &= ~mask;
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CPU.CR.CR |= CPU.FPSCR.FPSCR & mask;
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}
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}
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void MTFSB0(u32 bt, bool rc)
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void MTFSB0(u32 crbd, bool rc)
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{
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{
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UNIMPLEMENTED();
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u64 mask = (1ULL << crbd);
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CPU.FPSCR.FPSCR &= ~mask;
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if(rc) UNIMPLEMENTED();
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}
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}
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void MTFSFI(u32 crfd, u32 i, bool rc)
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void MTFSFI(u32 crfd, u32 i, bool rc)
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{
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{
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UNIMPLEMENTED();
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u64 mask = (1ULL << crfd);
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if(i)
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{
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CPU.FPSCR.FPSCR |= mask;
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}
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else
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{
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CPU.FPSCR.FPSCR &= ~mask;
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}
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if(rc) UNIMPLEMENTED();
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}
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}
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void MFFS(u32 frd, bool rc)
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void MFFS(u32 frd, bool rc)
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{
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{
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(u64&)CPU.FPR[frd] = CPU.FPSCR.FPSCR;
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(u64&)CPU.FPR[frd] = CPU.FPSCR.FPSCR;
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if(rc) UNK("mffs.");
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if(rc) UNIMPLEMENTED();
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}
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}
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void MTFSF(u32 flm, u32 frb, bool rc)
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void MTFSF(u32 flm, u32 frb, bool rc)
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{
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{
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@ -3493,17 +3509,17 @@ private:
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CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc];
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CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc];
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CPU.FPSCR.FI = 0;
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CPU.FPSCR.FI = 0;
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CPU.FPSCR.FR = 0;
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CPU.FPSCR.FR = 0;
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CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType();
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) UNK("fmul.");//CPU.UpdateCR1(CPU.FPR[frd]);
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if(rc) UNK("fmul.");//CPU.UpdateCR1(CPU.FPR[frd]);
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}
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}
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void FRSQRTE(u32 frd, u32 frb, bool rc)
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void FRSQRTE(u32 frd, u32 frb, bool rc)
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{
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{
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UNIMPLEMENTED();
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//if(CPU.FPR[frb].
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}
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}
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void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc)
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void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc)
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{
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{
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CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb];
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CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb];
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CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType();
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) UNK("fmsub.");//CPU.UpdateCR1(CPU.FPR[frd]);
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if(rc) UNK("fmsub.");//CPU.UpdateCR1(CPU.FPR[frd]);
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}
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}
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void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc)
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void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc)
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