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https://github.com/RPCS3/rpcs3.git
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Set host FP rounding mode for PPU floating-point instructions.
This commit is contained in:
Andrew Church
parent
6627cc9666
commit
04902965fe
@ -17,6 +17,8 @@
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#define _rotl64(x,r) (((u64)(x) << (r)) | ((u64)(x) >> (64 - (r))))
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#endif
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#include <fenv.h>
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#if 0//def _DEBUG
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#define HLE_CALL_DEBUG
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#endif
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@ -60,6 +62,25 @@ static double SilenceNaN(double x)
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return (double&)bits;
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}
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static void SetHostRoundingMode(u32 rn)
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{
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switch (rn)
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{
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case FPSCR_RN_NEAR:
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fesetround(FE_TONEAREST);
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break;
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case FPSCR_RN_ZERO:
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fesetround(FE_TOWARDZERO);
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break;
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case FPSCR_RN_PINF:
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fesetround(FE_UPWARD);
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break;
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case FPSCR_RN_MINF:
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fesetround(FE_DOWNWARD);
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break;
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}
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}
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namespace ppu_recompiler_llvm {
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class Compiler;
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}
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@ -245,6 +266,7 @@ private:
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}
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void VADDFP(u32 vd, u32 va, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -441,6 +463,7 @@ private:
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}
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void VCFSX(u32 vd, u32 uimm5, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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u32 scale = 1 << uimm5;
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for (uint w = 0; w < 4; w++)
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@ -450,6 +473,7 @@ private:
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}
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void VCFUX(u32 vd, u32 uimm5, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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u32 scale = 1 << uimm5;
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for (uint w = 0; w < 4; w++)
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@ -786,8 +810,8 @@ private:
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CPU.VPR[vd]._s32[w] = (int)0x80000000;
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CPU.VSCR.SAT = 1;
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}
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else // C rounding = Round towards 0
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CPU.VPR[vd]._s32[w] = (int)result;
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else
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CPU.VPR[vd]._s32[w] = (int)trunc(result);
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}
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}
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}
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@ -804,7 +828,6 @@ private:
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}
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else
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{
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// C rounding = Round towards 0
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double result = (double)b * nScale;
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if (result > 0xffffffffu)
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{
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@ -817,7 +840,7 @@ private:
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CPU.VSCR.SAT = 1;
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}
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else
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CPU.VPR[vd]._u32[w] = (u32)result;
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CPU.VPR[vd]._u32[w] = (u32)trunc(result);
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}
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}
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}
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@ -826,6 +849,7 @@ private:
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// vd = 2^x
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// ISA : Note that the value placed into the element of vD may vary between implementations
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// and between different executions on the same implementation.
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float b = CheckVSCR_NJ(CPU.VPR[vb]._f[w]);
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@ -839,6 +863,7 @@ private:
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{
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// ISA : Note that the value placed into the element of vD may vary between implementations
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// and between different executions on the same implementation.
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float b = CheckVSCR_NJ(CPU.VPR[vb]._f[w]);
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@ -850,6 +875,7 @@ private:
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}
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void VMADDFP(u32 vd, u32 va, u32 vc, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -1275,6 +1301,7 @@ private:
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}
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void VNMSUBFP(u32 vd, u32 va, u32 vc, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -1568,6 +1595,7 @@ private:
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}
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void VREFP(u32 vd, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float b = CheckVSCR_NJ(CPU.VPR[vb]._f[w]);
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@ -1596,7 +1624,10 @@ private:
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if (std::isnan(b))
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CPU.VPR[vd]._f[w] = SilenceNaN(b);
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else
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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CPU.VPR[vd]._f[w] = nearbyintf(CPU.VPR[vb]._f[w]);
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}
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}
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}
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void VRFIP(u32 vd, u32 vb)
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@ -1646,6 +1677,7 @@ private:
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}
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void VRSQRTEFP(u32 vd, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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//TODO: accurate div
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@ -1846,6 +1878,7 @@ private:
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}
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void VSUBFP(u32 vd, u32 va, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -3663,6 +3696,7 @@ private:
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void FSQRTS(u32 frd, u32 frb, bool rc) {FSQRT(frd, frb, rc, true);}
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void FRES(u32 frd, u32 frb, bool rc)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(b))
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{
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@ -3797,6 +3831,7 @@ private:
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}
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void FRSP(u32 frd, u32 frb, bool rc)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if (FPRdouble::IsSNaN(b))
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{
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@ -3869,6 +3904,7 @@ private:
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switch(rn)
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{
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case FPSCR_RN_NEAR:
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SetHostRoundingMode(FPSCR_RN_NEAR);
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i = (s32)nearbyint(b);
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break;
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case FPSCR_RN_ZERO:
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@ -3902,6 +3938,7 @@ private:
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void FDIV(u32 frd, u32 fra, u32 frb, bool rc) {FDIV(frd, fra, frb, rc, false);}
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void FDIV(u32 frd, u32 fra, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(b))
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@ -3971,6 +4008,7 @@ private:
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void FSUB(u32 frd, u32 fra, u32 frb, bool rc) {FSUB(frd, fra, frb, rc, false);}
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void FSUB(u32 frd, u32 fra, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(b))
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@ -4016,6 +4054,7 @@ private:
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void FADD(u32 frd, u32 fra, u32 frb, bool rc) {FADD(frd, fra, frb, rc, false);}
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void FADD(u32 frd, u32 fra, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(b))
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@ -4061,6 +4100,7 @@ private:
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void FSQRT(u32 frd, u32 frb, bool rc) {FSQRT(frd, frb, rc, false);}
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void FSQRT(u32 frd, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(b))
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{
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@ -4106,6 +4146,7 @@ private:
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void FMUL(u32 frd, u32 fra, u32 frc, bool rc) {FMUL(frd, fra, frc, rc, false);}
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void FMUL(u32 frd, u32 fra, u32 frc, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double c = CPU.FPR[frc];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(c))
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@ -4150,6 +4191,7 @@ private:
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}
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void FRSQRTE(u32 frd, u32 frb, bool rc)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(b))
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{
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@ -4201,6 +4243,7 @@ private:
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void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, false, false, false);}
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void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc, bool neg, bool sub, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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const double c = CPU.FPR[frc];
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@ -4344,6 +4387,7 @@ private:
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switch(rn)
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{
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case FPSCR_RN_NEAR:
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SetHostRoundingMode(FPSCR_RN_NEAR);
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i = (s64)nearbyint(b);
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break;
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case FPSCR_RN_ZERO:
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