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PPU: redesign LVSL, LVSR instructions
This commit is contained in:
Nekotekina
parent
d3198ddf60
commit
140a581d23
@ -94,24 +94,24 @@ extern __m128i sse_altivec_vperm(__m128i A, __m128i B, __m128i C)
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extern __m128i sse_altivec_lvsl(u64 addr)
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{
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alignas(16) static const u64 lvsl_values[0x10][2] =
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alignas(16) static const u8 lvsl_values[0x10][0x10] =
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{
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{ 0x08090A0B0C0D0E0F, 0x0001020304050607 },
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{ 0x090A0B0C0D0E0F10, 0x0102030405060708 },
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{ 0x0A0B0C0D0E0F1011, 0x0203040506070809 },
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{ 0x0B0C0D0E0F101112, 0x030405060708090A },
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{ 0x0C0D0E0F10111213, 0x0405060708090A0B },
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{ 0x0D0E0F1011121314, 0x05060708090A0B0C },
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{ 0x0E0F101112131415, 0x060708090A0B0C0D },
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{ 0x0F10111213141516, 0x0708090A0B0C0D0E },
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{ 0x1011121314151617, 0x08090A0B0C0D0E0F },
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{ 0x1112131415161718, 0x090A0B0C0D0E0F10 },
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{ 0x1213141516171819, 0x0A0B0C0D0E0F1011 },
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{ 0x131415161718191A, 0x0B0C0D0E0F101112 },
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{ 0x1415161718191A1B, 0x0C0D0E0F10111213 },
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{ 0x15161718191A1B1C, 0x0D0E0F1011121314 },
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{ 0x161718191A1B1C1D, 0x0E0F101112131415 },
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{ 0x1718191A1B1C1D1E, 0x0F10111213141516 },
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{ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 },
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{ 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01 },
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{ 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02 },
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{ 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03 },
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{ 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04 },
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{ 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05 },
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{ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06 },
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{ 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07 },
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{ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08 },
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{ 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09 },
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{ 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a },
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{ 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b },
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{ 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c },
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{ 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d },
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{ 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e },
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{ 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f },
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};
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return _mm_load_si128((__m128i*)lvsl_values[addr & 0xf]);
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@ -119,24 +119,24 @@ extern __m128i sse_altivec_lvsl(u64 addr)
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extern __m128i sse_altivec_lvsr(u64 addr)
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{
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alignas(16) static const u64 lvsr_values[0x10][2] =
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alignas(16) static const u8 lvsr_values[0x10][0x10] =
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{
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{ 0x18191A1B1C1D1E1F, 0x1011121314151617 },
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{ 0x1718191A1B1C1D1E, 0x0F10111213141516 },
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{ 0x161718191A1B1C1D, 0x0E0F101112131415 },
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{ 0x15161718191A1B1C, 0x0D0E0F1011121314 },
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{ 0x1415161718191A1B, 0x0C0D0E0F10111213 },
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{ 0x131415161718191A, 0x0B0C0D0E0F101112 },
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{ 0x1213141516171819, 0x0A0B0C0D0E0F1011 },
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{ 0x1112131415161718, 0x090A0B0C0D0E0F10 },
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{ 0x1011121314151617, 0x08090A0B0C0D0E0F },
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{ 0x0F10111213141516, 0x0708090A0B0C0D0E },
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{ 0x0E0F101112131415, 0x060708090A0B0C0D },
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{ 0x0D0E0F1011121314, 0x05060708090A0B0C },
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{ 0x0C0D0E0F10111213, 0x0405060708090A0B },
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{ 0x0B0C0D0E0F101112, 0x030405060708090A },
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{ 0x0A0B0C0D0E0F1011, 0x0203040506070809 },
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{ 0x090A0B0C0D0E0F10, 0x0102030405060708 },
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{ 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10 },
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{ 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f },
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{ 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e },
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{ 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d },
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{ 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c },
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{ 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b },
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{ 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a },
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{ 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09 },
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{ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08 },
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{ 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07 },
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{ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06 },
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{ 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05 },
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{ 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04 },
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{ 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03 },
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{ 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02 },
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{ 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01 },
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};
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return _mm_load_si128((__m128i*)lvsr_values[addr & 0xf]);
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@ -2050,7 +2050,7 @@ bool ppu_interpreter::VSRB(ppu_thread& ppu, ppu_opcode_t op)
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auto& d = ppu.vr[op.vd];
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const auto& a = ppu.vr[op.va];
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const auto& b = ppu.vr[op.vb];
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for (uint i = 0; i < 16; i++)
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{
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d._u8[i] = a._u8[i] >> (b._u8[i] & 0x7);
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@ -2964,7 +2964,7 @@ bool ppu_interpreter::BCCTR(ppu_thread& ppu, ppu_opcode_t op)
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if (op.lk) ppu.lr = link;
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return false;
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}
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return true;
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}
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@ -3163,7 +3163,7 @@ bool ppu_interpreter::MFOCRF(ppu_thread& ppu, ppu_opcode_t op)
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const u32 n = cntlz32(op.crm) & 7;
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const u32 p = n * 4;
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const u32 v = ppu.cr[p + 0] << 3 | ppu.cr[p + 1] << 2 | ppu.cr[p + 2] << 1 | ppu.cr[p + 3] << 0;
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ppu.gpr[op.rd] = v << (p ^ 0x1c);
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}
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else
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@ -122,7 +122,7 @@ Type* PPUTranslator::GetContextType()
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Function* PPUTranslator::Translate(const ppu_function& info)
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{
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m_function = m_module->getFunction(info.name);
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std::fill(std::begin(m_globals), std::end(m_globals), nullptr);
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std::fill(std::begin(m_locals), std::end(m_locals), nullptr);
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@ -207,7 +207,7 @@ Value* PPUTranslator::GetAddr(u64 _add)
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// Load segment address from global variable, compute actual instruction address
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return m_ir->CreateAdd(m_ir->getInt64(m_addr + _add), m_ir->CreateLoad(m_segs[m_reloc - m_info.segs.data()]));
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}
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return m_ir->getInt64(m_addr + _add);
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}
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@ -342,7 +342,7 @@ Value* PPUTranslator::Solid(Value* value)
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const u32 size = value->getType()->getPrimitiveSizeInBits();
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/* Workarounds (casting bool vectors directly may produce invalid code) */
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if (value->getType() == GetType<bool[4]>())
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{
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return m_ir->CreateBitCast(SExt(value, GetType<u32[4]>()), m_ir->getIntNTy(128));
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@ -1759,7 +1759,7 @@ void PPUTranslator::B(ppu_opcode_t op)
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{
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RegStore(GetAddr(+4), m_lr);
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}
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FlushRegisters();
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CallFunction(target);
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}
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@ -1972,7 +1972,7 @@ void PPUTranslator::RLWNM(ppu_opcode_t op)
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// Generic op
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result = m_ir->CreateAnd(RotateLeft(GetGpr(op.rs, 32), GetGpr(op.rb, 32)), mask);
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}
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// Extend 32-bit op result
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result = ZExt(result);
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}
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@ -2064,7 +2064,7 @@ void PPUTranslator::RLDICL(ppu_opcode_t op)
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// Generic op, including CLRLDI mnemonic
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result = m_ir->CreateAnd(RotateLeft(GetGpr(op.rs), sh), mask);
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}
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SetGpr(op.ra, result);
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if (op.rc) SetCrFieldSignedCmp(0, result, m_ir->getInt64(0));
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}
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@ -2196,6 +2196,9 @@ void PPUTranslator::TW(ppu_opcode_t op)
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void PPUTranslator::LVSL(ppu_opcode_t op)
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{
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const auto addr = op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb);
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//const auto _add = m_ir->CreateInsertElement(ConstantVector::getSplat(16, m_ir->getInt8(0)), Trunc(m_ir->CreateAnd(addr, 0xf), GetType<u8>()), m_ir->getInt32(0));
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//const auto base = ConstantDataVector::get(m_context, std::vector<u8>{15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
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//SetVr(op.vd, m_ir->CreateAdd(base, Shuffle(_add, nullptr, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0})));
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SetVr(op.vd, Call(GetType<u8[16]>(), m_pure_attr, "__lvsl", addr));
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}
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@ -2351,6 +2354,9 @@ void PPUTranslator::CMPL(ppu_opcode_t op)
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void PPUTranslator::LVSR(ppu_opcode_t op)
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{
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const auto addr = op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb);
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//const auto _add = m_ir->CreateInsertElement(ConstantVector::getSplat(16, m_ir->getInt8(0)), Trunc(m_ir->CreateAnd(addr, 0xf), GetType<u8>()), m_ir->getInt32(0));
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//const auto base = ConstantDataVector::get(m_context, std::vector<u8>{31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16});
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//SetVr(op.vd, m_ir->CreateSub(base, Shuffle(_add, nullptr, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0})));
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SetVr(op.vd, Call(GetType<u8[16]>(), m_pure_attr, "__lvsr", addr));
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}
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