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https://github.com/RPCS3/rpcs3.git
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Initial SPU bringup
This commit is contained in:
kd-11
kd-11
parent
bc1b0eb41b
commit
140fddbba8
@ -58,19 +58,13 @@ static void ghc_cpp_trampoline(u64 fn_target, native_asm& c, auto& args)
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{
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using namespace asmjit;
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Label target = c.newLabel();
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c.mov(args[0], a64::x19);
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c.mov(args[1], a64::x20);
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c.mov(args[2], a64::x21);
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c.mov(args[3], a64::x22);
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c.ldr(a64::x15, arm::Mem(target));
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c.mov(a64::x15, Imm(fn_target));
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c.br(a64::x15);
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c.brk(Imm(0x42)); // Unreachable
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c.bind(target);
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c.embedUInt64(fn_target);
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}
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#endif
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@ -97,8 +91,6 @@ DECLARE(spu_runtime::tr_dispatch) = []
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{
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c.yield();
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ghc_cpp_trampoline(reinterpret_cast<u64>(&spu_recompiler_base::dispatch), c, args);
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c.embed("tr_dispatch", 11);
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});
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return trptr;
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#else
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@ -124,8 +116,6 @@ DECLARE(spu_runtime::tr_branch) = []
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[](native_asm& c, auto& args)
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{
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ghc_cpp_trampoline(reinterpret_cast<u64>(&spu_recompiler_base::branch), c, args);
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c.embed("tr_branch", 9);
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});
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return trptr;
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#else
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@ -149,10 +139,9 @@ DECLARE(spu_runtime::tr_interpreter) = []
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[](native_asm& c, auto& args)
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{
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ghc_cpp_trampoline(reinterpret_cast<u64>(&spu_recompiler_base::old_interpreter), c, args);
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c.embed("tr_interpreter", 14);
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});
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return trptr;
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return trptr;
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#endif
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}();
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@ -228,13 +217,15 @@ DECLARE(spu_runtime::tr_all) = []
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{
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using namespace asmjit;
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// w1: PC (eax in x86 SPU)
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// x7: lsa (rcx in x86 SPU)
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// Inputs:
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// x19 = m_thread a.k.a arg[0]
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// x20 = ls_base
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// x21 - x22 = args[2 - 3]
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//ensure(::offset32(&spu_thread::pc) <= 32760);
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//ensure(::offset32(&spu_thread::block_hash) <= 32760);
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// Load PC
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Label pc_offset = c.newLabel();
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c.ldr(a64::x0, arm::Mem(pc_offset));
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c.ldr(a64::w1, arm::Mem(a64::x19, a64::x0)); // REG_Base + offset(spu_thread::pc)
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c.ldr(a64::w1, arm::Mem(a64::x19, ::offset32(&spu_thread::pc))); // REG_Base + offset(spu_thread::pc)
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// Compute LS address = REG_Sp + PC, store into x7 (use later)
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c.add(a64::x7, a64::x20, a64::x1);
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// Load 32b from LS address
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@ -242,27 +233,18 @@ DECLARE(spu_runtime::tr_all) = []
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// shr (32 - 20)
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c.lsr(a64::w3, a64::w3, Imm(32 - 20));
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// Load g_dispatcher
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Label g_dispatcher_offset = c.newLabel();
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c.ldr(a64::x4, arm::Mem(g_dispatcher_offset));
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c.mov(a64::x4, Imm(reinterpret_cast<u64>(g_dispatcher)));
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// Update block hash
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Label block_hash_offset = c.newLabel();
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c.mov(a64::x5, Imm(0));
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c.ldr(a64::x6, arm::Mem(block_hash_offset));
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c.str(a64::x5, arm::Mem(a64::x19, a64::x6)); // REG_Base + offset(spu_thread::block_hash)
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c.str(a64::x5, arm::Mem(a64::x19, ::offset32(&spu_thread::block_hash))); // REG_Base + offset(spu_thread::block_hash)
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// Jump to [g_dispatcher + idx * 8]
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c.mov(a64::x6, Imm(8));
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c.mul(a64::x6, a64::x3, a64::x6);
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c.add(a64::x4, a64::x4, a64::x6);
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c.ldr(a64::x4, arm::Mem(a64::x4));
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c.br(a64::x4);
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c.bind(pc_offset);
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c.embedUInt64(::offset32(&spu_thread::pc));
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c.bind(g_dispatcher_offset);
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c.embedUInt64(reinterpret_cast<u64>(g_dispatcher));
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c.bind(block_hash_offset);
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c.embedUInt64(::offset32(&spu_thread::block_hash));
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c.embed("tr_all", 6);
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// Unreachable guard
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c.brk(0x42);
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});
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return trptr;
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#else
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@ -307,7 +289,7 @@ DECLARE(spu_runtime::g_gateway) = build_function_asm<spu_function_t>("spu_gatewa
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#endif
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// Save native stack pointer for longjmp emulation
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c.mov(x86::qword_ptr(args[0], ::offset32(&spu_thread::saved_native_sp)), x86::rsp);
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c.mov(x86::qword_ptr(args[0], ::offset32(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs)), x86::rsp);
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// Move 4 args (despite spu_function_t def)
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c.mov(x86::r13, args[0]);
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@ -359,23 +341,28 @@ DECLARE(spu_runtime::g_gateway) = build_function_asm<spu_function_t>("spu_gatewa
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c.ret();
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#elif defined(ARCH_ARM64)
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// Push callee saved registers to the stack
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// We need to save x18-x30 = 13 x 8B each + 8 bytes for 16B alignment = 112B
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c.sub(a64::sp, a64::sp, Imm(112));
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c.stp(a64::x18, a64::x19, arm::Mem(a64::sp));
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c.stp(a64::x20, a64::x21, arm::Mem(a64::sp, 16));
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c.stp(a64::x22, a64::x23, arm::Mem(a64::sp, 32));
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c.stp(a64::x24, a64::x25, arm::Mem(a64::sp, 48));
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c.stp(a64::x26, a64::x27, arm::Mem(a64::sp, 64));
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c.stp(a64::x28, a64::x29, arm::Mem(a64::sp, 80));
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c.str(a64::x30, arm::Mem(a64::sp, 96));
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// Save native stack pointer for longjmp emulation
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Label sp_offset = c.newLabel();
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c.ldr(a64::x26, arm::Mem(sp_offset));
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// sp not allowed to be used in load/stores directly
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c.mov(a64::x15, a64::sp);
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c.str(a64::x15, arm::Mem(args[0], a64::x26));
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// Save non-volatile regs. We do this within the thread context instead of normal stack
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const u32 hv_regs_base = ::offset32(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs);
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// NOTE: A64 gp-gp-imm add only takes immediates of upto 4095. Larger numbers can work, but need to be multiples of 2 for lowering to replace the instruction correctly
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// Unfortunately asmjit fails silently on these patterns which can generate incorrect code
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c.mov(a64::x15, args[0]);
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c.mov(a64::x14, Imm(hv_regs_base));
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c.add(a64::x14, a64::x14, a64::x15); // Reg context offset
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// Return address of escape should jump to the restore block
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auto epilogue_addr = c.newLabel();
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c.adr(a64::x15, epilogue_addr);
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c.mov(a64::x16, a64::sp);
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c.stp(a64::x15, a64::x16, arm::Mem(a64::x14));
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c.stp(a64::x18, a64::x19, arm::Mem(a64::x14, 16));
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c.stp(a64::x20, a64::x21, arm::Mem(a64::x14, 32));
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c.stp(a64::x22, a64::x23, arm::Mem(a64::x14, 48));
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c.stp(a64::x24, a64::x25, arm::Mem(a64::x14, 64));
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c.stp(a64::x26, a64::x27, arm::Mem(a64::x14, 80));
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c.stp(a64::x28, a64::x29, arm::Mem(a64::x14, 96));
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c.str(a64::x30, arm::Mem(a64::x14, 112));
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// Move 4 args (despite spu_function_t def)
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c.mov(a64::x19, args[0]);
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@ -383,42 +370,34 @@ DECLARE(spu_runtime::g_gateway) = build_function_asm<spu_function_t>("spu_gatewa
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c.mov(a64::x21, args[2]);
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c.mov(a64::x22, args[3]);
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// Save ret address to stack
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// since non-tail calls to cpp fns may corrupt lr and
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// g_tail_escape may jump out of a fn before the epilogue can restore lr
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Label ret_addr = c.newLabel();
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c.adr(a64::x0, ret_addr);
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c.str(a64::x0, arm::Mem(a64::sp, 104));
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// Inject stack frame for scratchpad. Alternatively use per-function frames but that adds some overhead
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c.sub(a64::sp, a64::sp, Imm(8192));
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Label call_target = c.newLabel();
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c.ldr(a64::x0, arm::Mem(call_target));
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c.mov(a64::x0, Imm(reinterpret_cast<u64>(spu_runtime::tr_all)));
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c.blr(a64::x0);
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c.bind(ret_addr);
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// This is the return point for the far ret. Never jump back into host code without coming through this exit
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c.bind(epilogue_addr);
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// Restore stack ptr
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c.ldr(a64::x26, arm::Mem(sp_offset));
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c.ldr(a64::x15, arm::Mem(a64::x19, a64::x26));
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c.mov(a64::sp, a64::x15);
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// Cleanup scratchpad (not needed, we'll reload sp shortly)
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// c.add(a64::sp, a64::sp, Imm(8192));
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// Restore thread context
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c.mov(a64::x14, Imm(hv_regs_base));
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c.add(a64::x14, a64::x14, a64::x19);
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c.ldr(a64::x16, arm::Mem(a64::x14, 8));
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c.ldp(a64::x18, a64::x19, arm::Mem(a64::x14, 16));
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c.ldp(a64::x20, a64::x21, arm::Mem(a64::x14, 32));
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c.ldp(a64::x22, a64::x23, arm::Mem(a64::x14, 48));
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c.ldp(a64::x24, a64::x25, arm::Mem(a64::x14, 64));
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c.ldp(a64::x26, a64::x27, arm::Mem(a64::x14, 80));
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c.ldp(a64::x28, a64::x29, arm::Mem(a64::x14, 96));
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c.ldr(a64::x30, arm::Mem(a64::x14, 112));
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// Restore registers from the stack
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c.ldp(a64::x18, a64::x19, arm::Mem(a64::sp));
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c.ldp(a64::x20, a64::x21, arm::Mem(a64::sp, 16));
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c.ldp(a64::x22, a64::x23, arm::Mem(a64::sp, 32));
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c.ldp(a64::x24, a64::x25, arm::Mem(a64::sp, 48));
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c.ldp(a64::x26, a64::x27, arm::Mem(a64::sp, 64));
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c.ldp(a64::x28, a64::x29, arm::Mem(a64::sp, 80));
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c.ldr(a64::x30, arm::Mem(a64::sp, 96));
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// Restore stack ptr
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c.add(a64::sp, a64::sp, Imm(112));
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// Return
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c.mov(a64::sp, a64::x16);
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c.ret(a64::x30);
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c.bind(sp_offset);
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c.embedUInt64(::offset32(&spu_thread::saved_native_sp));
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c.bind(call_target);
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c.embedUInt64(reinterpret_cast<u64>(spu_runtime::tr_all));
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c.embed("spu_gateway", 11);
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#else
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#error "Unimplemented"
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#endif
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@ -430,25 +409,19 @@ DECLARE(spu_runtime::g_escape) = build_function_asm<void(*)(spu_thread*)>("spu_e
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#if defined(ARCH_X64)
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// Restore native stack pointer (longjmp emulation)
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c.mov(x86::rsp, x86::qword_ptr(args[0], ::offset32(&spu_thread::saved_native_sp)));
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c.mov(x86::rsp, x86::qword_ptr(args[0], ::offset32(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs)));
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// Return to the return location
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c.sub(x86::rsp, 8);
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c.ret();
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#elif defined(ARCH_ARM64)
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// Restore native stack pointer (longjmp emulation)
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Label sp_offset = c.newLabel();
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c.ldr(a64::x15, arm::Mem(sp_offset));
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c.ldr(a64::x15, arm::Mem(args[0], a64::x15));
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c.mov(a64::sp, a64::x15);
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c.ldr(a64::x30, arm::Mem(a64::sp, 104));
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// Far ret, jumps to gateway epilogue
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const u32 reg_base = ::offset32(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs);
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c.mov(a64::x19, args[0]);
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c.mov(a64::x15, Imm(reg_base));
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c.add(a64::x15, a64::x15, args[0]);
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c.ldr(a64::x30, arm::Mem(a64::x15));
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c.ret(a64::x30);
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c.bind(sp_offset);
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c.embedUInt64(::offset32(&spu_thread::saved_native_sp));
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c.embed("spu_escape", 10);
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#else
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#error "Unimplemented"
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#endif
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@ -460,7 +433,7 @@ DECLARE(spu_runtime::g_tail_escape) = build_function_asm<void(*)(spu_thread*, sp
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#if defined(ARCH_X64)
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// Restore native stack pointer (longjmp emulation)
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c.mov(x86::rsp, x86::qword_ptr(args[0], ::offset32(&spu_thread::saved_native_sp)));
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c.mov(x86::rsp, x86::qword_ptr(args[0], ::offset32(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs)));
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// Adjust stack for initial call instruction in the gateway
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c.sub(x86::rsp, 16);
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@ -473,32 +446,47 @@ DECLARE(spu_runtime::g_tail_escape) = build_function_asm<void(*)(spu_thread*, sp
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c.mov(x86::qword_ptr(x86::rsp), args[1]);
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c.ret();
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#elif defined(ARCH_ARM64)
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// Restore native stack pointer (longjmp emulation)
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Label sp_offset = c.newLabel();
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c.ldr(a64::x15, arm::Mem(sp_offset));
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c.ldr(a64::x15, arm::Mem(args[0], a64::x15));
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c.mov(a64::sp, a64::x15);
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// Reload lr, since it might've been clobbered by a cpp fn
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// and g_tail_escape runs before epilogue
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c.ldr(a64::x30, arm::Mem(a64::sp, 104));
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// HV pointer
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const u32 reg_base = ::offset32(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs);
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// Tail call, GHC CC
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c.mov(a64::x19, args[0]); // REG_Base
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Label ls_offset = c.newLabel();
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c.ldr(a64::x20, arm::Mem(ls_offset));
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c.ldr(a64::x20, arm::Mem(args[0], a64::x20)); // REG_Sp
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c.mov(a64::x21, args[2]); // REG_Hp
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c.eor(a64::w22, a64::w22, a64::w22); // REG_R1
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c.mov(a64::x15, Imm(::offset32(&spu_thread::ls))); // SPU::ls offset cannot be correctly encoded for ldr as it is too large
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c.ldr(a64::x20, arm::Mem(a64::x19, a64::x15)); // REG_Sp
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c.mov(a64::x21, args[2]); // REG_Hp
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c.mov(a64::x22, a64::xzr); // REG_R1
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c.br(args[1]);
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// Reset sp to patch leaks. Calls to tail escape may leave their stack "dirty" due to optimizations.
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c.mov(a64::x14, Imm(reg_base + 8));
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c.ldr(a64::x15, arm::Mem(a64::x19, a64::x14));
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c.mov(a64::sp, a64::x15);
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c.bind(ls_offset);
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c.embedUInt64(::offset32(&spu_thread::ls));
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c.bind(sp_offset);
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c.embedUInt64(::offset32(&spu_thread::saved_native_sp));
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// Push context. This gateway can be returned to normally through a ret chain.
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// FIXME: Push the current PC and "this" as part of the pseudo-frame and return here directly.
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c.sub(a64::sp, a64::sp, Imm(16));
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c.str(args[0], arm::Mem(a64::sp));
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c.embed("spu_tail_escape", 15);
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// Allocate scratchpad. Not needed if using per-function frames, or if we just don't care about returning to C++ (jump to gw exit instead)
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c.sub(a64::sp, a64::sp, Imm(8192));
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// Make the far jump
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c.mov(a64::x15, args[1]);
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c.blr(a64::x15);
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// Clear scratch allocation
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c.add(a64::sp, a64::sp, Imm(8192));
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// Restore context. Escape point expects the current thread pointer at x19
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c.ldr(a64::x19, arm::Mem(a64::sp));
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c.add(a64::sp, a64::sp, Imm(16));
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// <Optional> We could technically just emit a return here, but we may not want to for now until support is more mature.
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// Should we attempt a normal return after this point, we'd be going back to C++ code which we really don't want.
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// We can't guarantee stack sanity for the C++ code and it's cookies since we're basically treating stack as a scratch playground since we entered the main gateway.
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// Instead, just fall back to hypervisor here. It also makes debugging easier.
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c.mov(a64::x15, Imm(reg_base));
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c.ldr(a64::x30, arm::Mem(a64::x19, a64::x15));
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c.ret(a64::x30);
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#else
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#error "Unimplemented"
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#endif
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@ -7628,6 +7616,10 @@ struct spu_fast : public spu_recompiler_base
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virtual spu_function_t compile(spu_program&& _func) override
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{
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#ifndef ARCH_X64
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fmt::throw_exception("Fast LLVM recompiler is unimplemented for architectures other than X86-64");
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#endif
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const auto add_loc = m_spurt->add_empty(std::move(_func));
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if (!add_loc)
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@ -67,6 +67,10 @@ const extern spu_decoder<spu_iflag> g_spu_iflag;
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#ifdef ARCH_ARM64
|
||||
#include "Emu/CPU/Backends/AArch64JIT.h"
|
||||
#endif
|
||||
|
||||
class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
|
||||
{
|
||||
// JIT Instance
|
||||
@ -1485,6 +1489,26 @@ public:
|
||||
// Metadata for branch weights
|
||||
m_md_likely = llvm::MDTuple::get(m_context, {md_name, md_high, md_low});
|
||||
m_md_unlikely = llvm::MDTuple::get(m_context, {md_name, md_low, md_high});
|
||||
|
||||
// Initialize transform passes
|
||||
#ifdef ARCH_ARM64
|
||||
{
|
||||
aarch64::GHC_frame_preservation_pass::config_t config =
|
||||
{
|
||||
.debug_info = false, // Set to "true" to insert debug frames on x27
|
||||
.use_stack_frames = false, // We don't need this since the SPU GW allocates global scratch on the stack
|
||||
.hypervisor_context_offset = ::offset32(&spu_thread::hv_ctx),
|
||||
.exclusion_callback = {}, // Unused
|
||||
.base_register_lookup = {} // Unused, always x19 on SPU
|
||||
};
|
||||
|
||||
// Create transform pass
|
||||
std::unique_ptr<translator_pass> ghc_fixup_pass = std::make_unique<aarch64::GHC_frame_preservation_pass>(config);
|
||||
|
||||
// Register it
|
||||
register_transform_pass(ghc_fixup_pass);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@ -2806,7 +2830,7 @@ public:
|
||||
m_interp_regs = _ptr(m_thread, get_reg_offset(0));
|
||||
|
||||
// Save host thread's stack pointer
|
||||
const auto native_sp = spu_ptr<u64>(&spu_thread::saved_native_sp);
|
||||
const auto native_sp = spu_ptr<u64>(&spu_thread::hv_ctx, &rpcs3::hypervisor_context_t::regs);
|
||||
#if defined(ARCH_X64)
|
||||
const auto rsp_name = MetadataAsValue::get(m_context, MDNode::get(m_context, {MDString::get(m_context, "rsp")}));
|
||||
#elif defined(ARCH_ARM64)
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#pragma once
|
||||
|
||||
#include "Emu/CPU/CPUThread.h"
|
||||
#include "Emu/CPU/Hypervisor.h"
|
||||
#include "Emu/Cell/SPUInterpreter.h"
|
||||
#include "Emu/Memory/vm.h"
|
||||
#include "MFC.h"
|
||||
@ -778,7 +779,7 @@ public:
|
||||
u64 block_recover = 0;
|
||||
u64 block_failure = 0;
|
||||
|
||||
u64 saved_native_sp = 0; // Host thread's stack pointer for emulated longjmp
|
||||
alignas(16) rpcs3::hypervisor_context_t hv_ctx; // NOTE: The offset within the class must be within the first 1MiB
|
||||
|
||||
u64 ftx = 0; // Failed transactions
|
||||
u64 stx = 0; // Succeeded transactions (pure counters)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user