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Do not use negative unsigned literals
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parent
13a557fe67
commit
146e43b6ec
@ -967,9 +967,9 @@ struct ppu_acontext
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// Bit range: constant 0 = (0;0), constant 1 = (1;1), normalized undef = (0;1), unnormalized undef = (1;0)
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u64 imin = 0ull; // Integral range begin
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u64 imax = -1ull; // Integral range end
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u64 imax = ~0ull; // Integral range end
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u64 bmin = 0ull; // Bit range begin
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u64 bmax = -1ull; // Bit range end
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u64 bmax = ~0ull; // Bit range end
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void set_undef()
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{
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@ -1390,7 +1390,7 @@ void spu_thread::do_dma_transfer(const spu_mfc_cmd& args)
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break;
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}
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auto lock = vm::passive_lock(eal & -128u, ::align(eal + size, 128));
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auto lock = vm::passive_lock(eal & -128, ::align(eal + size, 128));
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while (size >= 128)
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{
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@ -1578,7 +1578,7 @@ bool spu_thread::do_list_transfer(spu_mfc_cmd& args)
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void spu_thread::do_putlluc(const spu_mfc_cmd& args)
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{
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const u32 addr = args.eal & -128u;
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const u32 addr = args.eal & -128;
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if (raddr && addr == raddr)
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{
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@ -1777,7 +1777,7 @@ bool spu_thread::process_mfc_cmd()
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{
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case MFC_GETLLAR_CMD:
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{
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const u32 addr = ch_mfc_cmd.eal & -128u;
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const u32 addr = ch_mfc_cmd.eal & -128;
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auto& data = vm::_ref<decltype(rdata)>(addr);
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auto& dst = _ref<decltype(rdata)>(ch_mfc_cmd.lsa & 0x3ff80);
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u64 ntime;
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@ -1888,7 +1888,7 @@ bool spu_thread::process_mfc_cmd()
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case MFC_PUTLLC_CMD:
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{
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// Store conditionally
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const u32 addr = ch_mfc_cmd.eal & -128u;
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const u32 addr = ch_mfc_cmd.eal & -128;
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u32 result = 0;
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if (raddr == addr)
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@ -190,7 +190,7 @@ namespace rsx
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// Pipeline barrier seems to be equivalent to a SHADER_READ stage barrier
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// lle-gcm likes to inject system reserved semaphores, presumably for system/vsh usage
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// Avoid calling render to avoid any havoc(flickering) they may cause from invalid flush/write
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const u32 offset = method_registers.semaphore_offset_4097() & -16u;
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const u32 offset = method_registers.semaphore_offset_4097() & -16;
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if (offset > 63 * 4 && !rsx->do_method(NV4097_TEXTURE_READ_SEMAPHORE_RELEASE, arg))
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{
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//
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@ -205,7 +205,7 @@ namespace rsx
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void back_end_write_semaphore_release(thread* rsx, u32 _reg, u32 arg)
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{
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// Full pipeline barrier
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const u32 offset = method_registers.semaphore_offset_4097() & -16u;
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const u32 offset = method_registers.semaphore_offset_4097() & -16;
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if (offset > 63 * 4 && !rsx->do_method(NV4097_BACK_END_WRITE_SEMAPHORE_RELEASE, arg))
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{
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//
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