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https://github.com/RPCS3/rpcs3.git
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SPU LLVM: move reg origin search to analyser
Refactor SPU analyser (block_info struct). Fill register use info (currently unused).
This commit is contained in:
Nekotekina
parent
1294e0d189
commit
1bc5e27507
@ -918,6 +918,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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m_targets.clear();
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m_preds.clear();
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m_preds[entry_point];
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m_bbs.clear();
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// Value flags (TODO)
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enum class vf : u32
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@ -1448,6 +1449,11 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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m_regmod[pos / 4] = s_reg_mfc_size;
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break;
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}
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case MFC_Cmd:
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{
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m_use_rb[pos / 4] = s_reg_mfc_eal;
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break;
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}
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}
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break;
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@ -1940,7 +1946,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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it++;
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}
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// Fill holes which contain only NOP and LNOP instructions
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// Fill holes which contain only NOP and LNOP instructions (TODO: compile)
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for (u32 i = 1, nnop = 0, vsize = 0; i <= result.size(); i++)
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{
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if (i >= result.size() || result[i])
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@ -1969,28 +1975,96 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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}
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}
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// Fill entry map, add entry points
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// Fill block info
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for (auto& pred : m_preds)
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{
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auto& block = m_bbs[pred.first];
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// Copy predeccessors (wrong at this point, needs a fixup later)
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block.preds = pred.second;
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// Fill register usage info
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for (u32 ia = pred.first; ia < 0x40000; ia += 4)
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{
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block.size++;
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for (auto* _use : {&m_use_ra, &m_use_rb, &m_use_rc})
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{
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if (u8 reg = (*_use)[ia / 4]; reg < s_reg_max)
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{
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// Register reg use only if it happens before reg mod
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if (!block.reg_mod[reg])
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block.reg_use.set(reg);
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}
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}
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if (m_use_rb[ia / 4] == s_reg_mfc_eal)
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{
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// Expand MFC_Cmd reg use
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for (u8 reg : {s_reg_mfc_lsa, s_reg_mfc_tag, s_reg_mfc_size})
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{
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if (!block.reg_mod[reg])
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block.reg_use.set(reg);
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}
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}
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// Register reg modification
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if (u8 reg = m_regmod[ia / 4]; reg < s_reg_max)
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{
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block.reg_mod.set(reg);
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}
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// Find targets (also means end of the block)
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const auto tfound = m_targets.find(ia);
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if (tfound != m_targets.end())
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{
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// Copy targets
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block.targets = tfound->second;
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break;
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}
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}
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block.reg_origin[0] = 0x80000000;
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block.reg_origin_abs[0] = 0x80000000;
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}
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// Fixup block predeccessors to point to basic blocks, not last instructions
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for (auto& bb : m_bbs)
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{
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for (u32& pred : bb.second.preds)
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{
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pred = std::prev(m_bbs.upper_bound(pred))->first;
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}
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}
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// Fill entry map, add chunk addresses
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while (true)
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{
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workload.clear();
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workload.push_back(entry_point);
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std::memset(m_entry_map.data(), 0, sizeof(m_entry_map));
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std::basic_string<u32> new_entries;
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for (u32 wi = 0; wi < workload.size(); wi++)
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{
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const u32 addr = workload[wi];
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const u16 _new = m_entry_map[addr / 4];
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auto& block = m_bbs.at(addr);
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const u32 _new = block.chunk;
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if (!m_entry_info[addr / 4])
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if (m_entry_info[addr / 4])
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{
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// Register empty chunk
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m_chunks[addr];
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}
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else
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{
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// Check block predecessors
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for (u32 pred : m_preds[addr])
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for (u32 pred : block.preds)
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{
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const u16 _old = m_entry_map[pred / 4];
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const u32 _old = m_bbs[pred].chunk;
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if (_old && _old != _new)
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if (_old < 0x40000 && _old != _new)
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{
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// If block has multiple 'entry' points, it becomes an entry point itself
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new_entries.push_back(addr);
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@ -1998,42 +2072,27 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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}
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}
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// Fill value
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const u16 root = m_entry_info[addr / 4] ? ::narrow<u16>(addr / 4) : _new;
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// Update chunk address
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block.chunk = m_entry_info[addr / 4] ? addr : _new;
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for (u32 wa = addr; wa < limit && result[(wa - lsa) / 4 + 1]; wa += 4)
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// Process block targets
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for (u32 target : block.targets)
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{
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// Fill entry address for the instruction
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m_entry_map[wa / 4] = root;
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const u32 value = m_entry_info[target / 4] ? target : block.chunk;
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// Find targets (also means end of the block)
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const auto tfound = m_targets.find(wa);
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if (tfound == m_targets.end())
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if (u32& tval = m_bbs[target].chunk; tval < 0x40000)
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{
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continue;
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}
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for (u32 target : tfound->second)
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{
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const u16 value = m_entry_info[target / 4] ? ::narrow<u16>(target / 4) : root;
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if (u16& tval = m_entry_map[target / 4])
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// TODO: fix condition
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if (tval != value && !m_entry_info[target / 4])
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{
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// TODO: fix condition
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if (tval != value && !m_entry_info[target / 4])
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{
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new_entries.push_back(target);
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}
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}
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else
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{
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tval = value;
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workload.emplace_back(target);
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new_entries.push_back(target);
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}
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}
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break;
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else
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{
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tval = value;
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workload.emplace_back(target);
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}
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}
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}
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@ -2045,6 +2104,91 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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for (u32 entry : new_entries)
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{
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m_entry_info[entry / 4] = true;
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// Acknowledge artificial (reversible) chunk entry point
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m_chunks[entry].joinable = true;
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}
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for (auto& bb : m_bbs)
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{
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// Reset chunk info
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bb.second.chunk = 0x40000;
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}
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}
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// Fill chunk info
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for (auto& bb : m_bbs)
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{
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auto& chunk = m_chunks.at(bb.second.chunk);
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chunk.bbs.push_back(bb.first);
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}
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workload.clear();
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workload.push_back(entry_point);
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// Fill register origin info
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for (u32 wi = 0; wi < workload.size(); wi++)
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{
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const u32 addr = workload[wi];
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auto& block = m_bbs.at(addr);
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if (block.reg_origin[0] == 0x80000000)
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{
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// Initialize entry point with default value: unknown origin (requires load)
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block.reg_origin.fill(0x40000);
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}
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if (block.reg_origin_abs[0] == 0x80000000)
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{
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block.reg_origin_abs.fill(0x40000);
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}
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for (u32 target : block.targets)
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{
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auto& tb = m_bbs.at(target);
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// Target block is either queued for the first time, or on request
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bool enqueue = tb.reg_origin[0] == 0x80000000 || tb.reg_origin_abs[0] == 0x80000000;
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for (u32 i = 0; i < s_reg_max; i++)
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{
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if (tb.chunk == block.chunk && tb.reg_origin[i] != -1)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin[i] == -1 ? addr : block.reg_origin[i];
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if (tb.reg_origin[i] != expected)
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{
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// Multiple origins merged (requires PHI node)
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tb.reg_origin[i] = -1;
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// Need to process this target block again in order to propagate -1
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enqueue = true;
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}
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}
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if (tb.chunk != block.chunk && target != addr + block.size * 4 && m_entry_info[target / 4])
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{
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// Skip call target completely
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continue;
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}
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if (tb.reg_origin_abs[i] != -1)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin_abs[i] == -1 ? addr : block.reg_origin_abs[i];
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if (tb.reg_origin_abs[i] != expected)
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{
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tb.reg_origin_abs[i] = -1;
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enqueue = true;
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}
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}
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}
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if (enqueue)
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{
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workload.emplace_back(target);
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}
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}
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}
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@ -2158,12 +2302,6 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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// Final block (for PHI nodes, set after completion)
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llvm::BasicBlock* block_end{};
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// Regmod compilation (TODO)
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std::bitset<s_reg_max> mod;
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// List of actual predecessors
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std::basic_string<u32> preds;
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// Current register values
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std::array<llvm::Value*, s_reg_max> reg{};
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@ -2239,7 +2377,7 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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{
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if (auto c = llvm::dyn_cast_or_null<llvm::Constant>(m_block->reg[i]))
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{
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if (!(find_reg_origin(addr, i, false) >> 31))
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if (m_bbs.at(addr).reg_origin_abs[i] != -1)
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{
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regs[i] = c;
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}
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@ -2883,112 +3021,6 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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return eval(splat<T>(imm));
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}
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// Return either basic block addr with single dominating value, or negative number of PHI entries
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u32 find_reg_origin(u32 addr, u32 index, bool chunk_only = true)
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{
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u32 result = -1;
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// Handle entry point specially
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if (chunk_only && m_entry_info[addr / 4])
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{
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result = addr;
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}
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// Used for skipping blocks from different chunks
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const u16 root = ::narrow<u16>(m_entry / 4);
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// List of predecessors to check
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m_scan_queue.clear();
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const auto pfound = m_preds.find(addr);
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if (pfound != m_preds.end())
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{
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for (u32 pred : pfound->second)
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{
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if (chunk_only && m_entry_map[pred / 4] != root)
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{
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continue;
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}
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m_scan_queue.push_back(pred);
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}
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}
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// TODO: allow to avoid untouched registers in some cases
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bool regmod_any = result == -1;
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for (u32 i = 0; i < m_scan_queue.size(); i++)
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{
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// Find whether the block modifies the selected register
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bool regmod = false;
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for (addr = m_scan_queue[i];; addr -= 4)
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{
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if (index == m_regmod.at(addr / 4))
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{
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regmod = true;
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regmod_any = true;
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}
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if (LIKELY(!m_block_info[addr / 4]))
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{
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continue;
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}
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const auto pfound = m_preds.find(addr);
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if (pfound == m_preds.end())
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{
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continue;
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}
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if (!regmod)
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{
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// Enqueue predecessors if register is not modified there
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for (u32 pred : pfound->second)
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{
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if (chunk_only && m_entry_map[pred / 4] != root)
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{
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continue;
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}
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// TODO
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if (std::find(m_scan_queue.cbegin(), m_scan_queue.cend(), pred) == m_scan_queue.cend())
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{
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m_scan_queue.push_back(pred);
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}
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}
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}
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break;
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}
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if (regmod || (chunk_only && m_entry_info[addr / 4]))
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{
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if (result == -1)
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{
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result = addr;
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}
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else if (result >> 31)
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{
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result--;
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}
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else
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{
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result = -2;
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}
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}
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}
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if (!regmod_any)
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{
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result = addr;
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}
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return result;
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}
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void update_pc()
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{
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m_ir->CreateStore(m_ir->getInt32(m_pos), spu_ptr<u32>(&spu_thread::pc))->setVolatile(true);
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@ -3325,32 +3357,28 @@ public:
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const u32 baddr = m_block_queue[bi];
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m_block = &m_blocks[baddr];
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m_ir->SetInsertPoint(m_block->block);
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auto& bb = m_bbs.at(baddr);
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bool need_check = false;
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const auto pfound = m_preds.find(baddr);
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if (pfound != m_preds.end() && !pfound->second.empty())
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if (bb.preds.size())
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{
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// Initialize registers and build PHI nodes if necessary
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for (u32 i = 0; i < s_reg_max; i++)
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{
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// TODO: optimize
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const u32 src = find_reg_origin(baddr, i);
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const u32 src = bb.reg_origin[i];
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if (src >> 31)
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//fs::file(m_spurt->get_cache_path() + "info.log", fs::write + fs::create + fs::append)
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// .write(fmt::format("0x%05x: $%u = 0x%05x\n", baddr, i, src >> 31 ? -1 : src));
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if (src == -1)
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{
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// TODO: type
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const auto _phi = m_ir->CreatePHI(get_reg_type(i), 0 - src);
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const auto _phi = m_ir->CreatePHI(get_reg_type(i), ::size32(bb.preds));
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m_block->phi[i] = _phi;
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m_block->reg[i] = _phi;
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for (u32 pred : pfound->second)
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for (u32 pred : bb.preds)
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{
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// TODO: optimize
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while (!m_block_info[pred / 4])
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{
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pred -= 4;
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}
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const auto bfound = m_blocks.find(pred);
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if (bfound != m_blocks.end() && bfound->second.block_end)
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@ -3404,38 +3432,41 @@ public:
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_phi->addIncoming(value, &m_function->getEntryBlock());
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}
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}
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else if (src != baddr)
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else if (src < 0x40000)
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{
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// Passthrough static value or constant
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// Passthrough register value
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const auto bfound = m_blocks.find(src);
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// TODO: error
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if (bfound != m_blocks.end())
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{
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m_block->reg[i] = bfound->second.reg[i];
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}
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else
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{
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LOG_ERROR(SPU, "[0x%05x] Value not found ($%u from 0x%05x)", baddr, i, src);
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}
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}
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else if (baddr == m_entry)
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else
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{
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// Passthrough constant from a different chunk
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// Passthrough constant from a different chunk (will be removed in future)
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m_block->reg[i] = m_finfo->reg[i];
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}
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}
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// Emit state check if necessary (TODO: more conditions)
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for (u32 pred : pfound->second)
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for (u32 pred : bb.preds)
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{
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if (pred >= baddr)
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{
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// If this block is a target of a backward branch (possibly loop), emit a check
|
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check_state(baddr);
|
||||
need_check = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// State check at the beginning of the chunk
|
||||
if (bi == 0 && g_cfg.core.spu_block_size != spu_block_size_type::safe)
|
||||
if (need_check || (bi == 0 && g_cfg.core.spu_block_size != spu_block_size_type::safe))
|
||||
{
|
||||
check_state(baddr);
|
||||
}
|
||||
|
||||
@ -182,6 +182,23 @@ public:
|
||||
// SPU Recompiler instance base class
|
||||
class spu_recompiler_base
|
||||
{
|
||||
public:
|
||||
enum : u8
|
||||
{
|
||||
s_reg_lr = 0,
|
||||
s_reg_sp = 1,
|
||||
s_reg_80 = 80,
|
||||
s_reg_127 = 127,
|
||||
|
||||
s_reg_mfc_eal,
|
||||
s_reg_mfc_lsa,
|
||||
s_reg_mfc_tag,
|
||||
s_reg_mfc_size,
|
||||
|
||||
// Max number of registers (for m_regmod)
|
||||
s_reg_max
|
||||
};
|
||||
|
||||
protected:
|
||||
std::shared_ptr<spu_runtime> m_spurt;
|
||||
|
||||
@ -207,8 +224,46 @@ protected:
|
||||
// List of function entry points and return points (set after BRSL, BRASL, BISL, BISLED)
|
||||
std::bitset<0x10000> m_entry_info;
|
||||
|
||||
// Compressed address of unique entry point for each instruction
|
||||
std::array<u16, 0x10000> m_entry_map{};
|
||||
// Basic block information
|
||||
struct block_info
|
||||
{
|
||||
// Address of the chunk entry point (chunk this block belongs to)
|
||||
u32 chunk = 0x40000;
|
||||
|
||||
// Number of instructions
|
||||
u16 size = 0;
|
||||
|
||||
// Bit mask of the registers modified in the block
|
||||
std::bitset<s_reg_max> reg_mod{};
|
||||
|
||||
// Bit mask of the registers used (before modified)
|
||||
std::bitset<s_reg_max> reg_use{};
|
||||
|
||||
// Single source of the reg value (dominating block address within the same chunk) or a negative number
|
||||
std::array<u32, s_reg_max> reg_origin, reg_origin_abs;
|
||||
|
||||
// All possible successor blocks
|
||||
std::basic_string<u32> targets;
|
||||
|
||||
// All predeccessor blocks
|
||||
std::basic_string<u32> preds;
|
||||
};
|
||||
|
||||
// Sorted basic block info
|
||||
std::map<u32, block_info> m_bbs;
|
||||
|
||||
// Advanced block (chunk) information
|
||||
struct chunk_info
|
||||
{
|
||||
// Flag set for synthetic chunks (false for call targets and return locations)
|
||||
bool joinable = false;
|
||||
|
||||
// List of basic blocks
|
||||
std::basic_string<u32> bbs;
|
||||
};
|
||||
|
||||
// Sorted chunk info
|
||||
std::map<u32, chunk_info> m_chunks;
|
||||
|
||||
std::shared_ptr<spu_cache> m_cache;
|
||||
|
||||
@ -261,20 +316,4 @@ public:
|
||||
|
||||
// Create recompiler instance (LLVM)
|
||||
static std::unique_ptr<spu_recompiler_base> make_llvm_recompiler(u8 magn = 0);
|
||||
|
||||
enum : u8
|
||||
{
|
||||
s_reg_lr = 0,
|
||||
s_reg_sp = 1,
|
||||
s_reg_80 = 80,
|
||||
s_reg_127 = 127,
|
||||
|
||||
s_reg_mfc_eal,
|
||||
s_reg_mfc_lsa,
|
||||
s_reg_mfc_tag,
|
||||
s_reg_mfc_size,
|
||||
|
||||
// Max number of registers (for m_regmod)
|
||||
s_reg_max
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user