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Refactor aarch64 JIT code
This commit is contained in:
kd-11
kd-11
parent
fd6ebe2895
commit
2faa61ac31
@ -333,99 +333,20 @@ namespace aarch64
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// However, there is not much guarantee that those are safe with only rare exceptions, and it doesn't hurt to patch the frame around them that much anyway.
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}
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terminator_found |= instruction_info.is_tail_call;
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if (!instruction_info.preserve_stack)
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if (instruction_info.preserve_stack)
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{
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// Now we patch the call if required. For normal calls that 'return' (i.e calls to C/C++ ABI), we do not patch them as they will manage the stack themselves (callee-managed)
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llvm::Instruction* original_inst = llvm::dyn_cast<llvm::Instruction>(bit);
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irb->SetInsertPoint(ensure(llvm::dyn_cast<llvm::Instruction>(bit)));
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// Non-tail call. If we have a stack allocated, we preserve it across the call
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++bit;
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continue;
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}
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// We're about to make a tail call. This means after this call, we're supposed to return immediately. In that case, don't link, lower to branch only.
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// Note that branches have some undesirable side-effects. For one, we lose the argument inputs, which the callee is expecting.
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// This means we burn some cycles on every exit, but in return we do not require one instruction on the prologue + the ret chain is eliminated.
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// No ret-chain also means two BBs can call each other indefinitely without running out of stack without relying on llvm to optimize that away.
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std::string exit_fn;
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auto ci = ensure(llvm::dyn_cast<llvm::CallInst>(original_inst));
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auto operand_count = ci->getNumOperands() - 1; // The last operand is the callee, not a real operand
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std::vector<std::string> constraints;
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std::vector<llvm::Value*> args;
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// We now load the callee args in reverse order to avoid self-clobbering of dependencies.
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// FIXME: This is often times redundant and wastes cycles, we'll clean this up in a MachineFunction pass later.
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int args_base_reg = instruction_info.callee_is_GHC ? aarch64::x19 : aarch64::x0; // GHC args are always x19..x25
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for (auto i = static_cast<int>(operand_count) - 1; i >= 0; --i)
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{
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args.push_back(ci->getOperand(i));
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exit_fn += fmt::format("mov x%d, $%u;\n", (args_base_reg + i), ::size32(args) - 1);
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constraints.push_back("r");
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}
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// Restore LR to the exit gate if we think it may have been trampled.
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if (function_info.clobbers_x30)
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{
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// Load the context "base" thread register to restore the link register from
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auto context_base_reg = get_base_register_for_call(instruction_info.callee_name);
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if (!instruction_info.callee_is_GHC)
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{
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// For non-GHC calls, we have to remap the arguments to x0...
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context_base_reg = static_cast<gpr>(context_base_reg - 19);
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}
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// We want to do this after loading the arguments in case there was any spilling involved.
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DPRINT("Patching call from %s to %s on register %d...",
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this_name.c_str(),
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instruction_info.callee_name.c_str(),
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static_cast<int>(context_base_reg));
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const auto x30_tail_restore = fmt::format(
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"ldr x30, [x%u, #%u];\n", // Load x30 from thread context
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static_cast<u32>(context_base_reg),
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m_config.hypervisor_context_offset);
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exit_fn += x30_tail_restore;
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}
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// Stack cleanup. We need to do this last to allow the spiller to find it's own spilled variables.
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if (function_info.stack_frame_size > 0)
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{
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exit_fn += frame_epilogue;
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}
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if (m_config.debug_info)
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{
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// Store x27 as our current address taking the place of LR (for debugging since bt is now useless)
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// x28 and x29 are used as breadcrumb registers in this mode to form a pseudo-backtrace.
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exit_fn +=
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"mov x29, x28;\n"
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"mov x28, x27;\n"
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"adr x27, .;\n";
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}
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auto target = ensure(ci->getCalledOperand());
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args.push_back(target);
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if (instruction_info.is_indirect)
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{
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// NOTE: For indirect calls, we read the callee register before we load the operands
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// If we don't do that the operands will overwrite our callee address if it lies in the x19-x25 range
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// There is no safe temp register to stuff the call address to either, you just have to stuff it below sp and load it after operands are all assigned.
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constraints.push_back("r");
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exit_fn = fmt::format("str $%u, [sp, #-8];\n", operand_count) + exit_fn;
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exit_fn +=
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"ldr x15, [sp, #-8];\n"
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"br x15;\n";
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}
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else
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{
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constraints.push_back("i");
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exit_fn += fmt::format("b $%u;\n", operand_count);
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}
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// Emit the branch
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llvm_asm(irb, exit_fn, args, fmt::merge(constraints, ","), f.getContext());
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ensure(instruction_info.is_tail_call);
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terminator_found = true;
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// Now we patch the call if required. For normal calls that 'return' (i.e calls to C/C++ ABI), we do not patch them as they will manage the stack themselves (callee-managed)
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auto ci = llvm::dyn_cast<llvm::CallInst>(bit);
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if (patch_tail_call(irb, f, ci, instruction_info, function_info, frame_epilogue))
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{
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// Delete original call instruction
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bit = ci->eraseFromParent();
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}
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@ -458,6 +379,120 @@ namespace aarch64
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}
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}
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bool GHC_frame_preservation_pass::patch_tail_call(
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llvm::IRBuilder<>* irb,
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llvm::Function& f,
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llvm::CallInst* ci,
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const instruction_info_t& instruction_info,
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const function_info_t& function_info,
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const std::string& frame_epilogue)
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{
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ensure(ci);
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const auto this_name = f.getName().str();
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irb->SetInsertPoint(ci);
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// We're about to make a tail call. This means after this call, we're supposed to return immediately. In that case, don't link, lower to branch only.
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// Note that branches have some undesirable side-effects. For one, we lose the argument inputs, which the callee is expecting.
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// This means we burn some cycles on every exit, but in return we do not require one instruction on the prologue + the ret chain is eliminated.
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// No ret-chain also means two BBs can call each other indefinitely without running out of stack without relying on llvm to optimize that away.
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std::string exit_fn;
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auto operand_count = ci->getNumOperands() - 1; // The last operand is the callee, not a real operand
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std::vector<std::string> arg_constraints;
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std::vector<llvm::Value*> unused_args; // To ref/touch
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std::vector<llvm::Value*> args;
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// We now load the callee args in reverse order to avoid self-clobbering of dependencies.
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// FIXME: This is often times redundant and wastes cycles, we'll clean this up in a MachineFunction pass later.
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int args_base_reg = instruction_info.callee_is_GHC ? aarch64::x19 : aarch64::x0; // GHC args are always x19..x25
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for (auto i = static_cast<int>(operand_count) - 1; i >= 0; --i)
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{
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llvm::Value* arg = ci->getOperand(i);
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args.push_back(arg);
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exit_fn += fmt::format("mov %s, $%u;\n", gpr_names[args_base_reg + i], ::size32(args) - 1);
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arg_constraints.push_back("r");
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}
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// Restore LR to the exit gate if we think it may have been trampled.
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if (function_info.clobbers_x30)
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{
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// Load the context "base" thread register to restore the link register from
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auto context_base_reg = get_base_register_for_call(instruction_info.callee_name);
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if (!instruction_info.callee_is_GHC)
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{
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// For non-GHC calls, we have to remap the arguments to x0...
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context_base_reg = static_cast<gpr>(context_base_reg - 19);
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}
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// We want to do this after loading the arguments in case there was any spilling involved.
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DPRINT("Patching call from %s to %s on register %d...",
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this_name.c_str(),
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instruction_info.callee_name.c_str(),
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static_cast<int>(context_base_reg));
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const auto x30_tail_restore = fmt::format(
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"ldr x30, [%s, #%u];\n", // Load x30 from thread context
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gpr_names[context_base_reg],
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m_config.hypervisor_context_offset);
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exit_fn += x30_tail_restore;
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}
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// Stack cleanup. We need to do this last to allow the spiller to find it's own spilled variables.
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if (function_info.stack_frame_size > 0)
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{
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exit_fn += frame_epilogue;
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}
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if (m_config.debug_info)
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{
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// Store x27 as our current address taking the place of LR (for debugging since bt is now useless)
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// x28 and x29 are used as breadcrumb registers in this mode to form a pseudo-backtrace.
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exit_fn +=
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"mov x29, x28;\n"
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"mov x28, x27;\n"
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"adr x27, .;\n";
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}
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const auto callee_arg = ::size32(args);
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auto target = ensure(ci->getCalledOperand());
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args.push_back(target);
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if (instruction_info.is_indirect)
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{
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// NOTE: For indirect calls, we read the callee register before we load the operands
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// If we don't do that the operands will overwrite our callee address if it lies in the x19-x25 range
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// There is no safe temp register to stuff the call address to either, you just have to stuff it below sp and load it after operands are all assigned.
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arg_constraints.push_back("r");
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exit_fn = fmt::format(
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"str $%u, [sp, #-8];\n",
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callee_arg) + exit_fn;
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exit_fn +=
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"ldr x15, [sp, #-8];\n"
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"br x15;\n";
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}
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else
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{
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arg_constraints.push_back("i");
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exit_fn += fmt::format("b $%u;\n", callee_arg);
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}
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// Touch the unused args by adding them to the instruction. This actually stops LLVM from clobbering the register during lowering.
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for (auto& arg : unused_args)
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{
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args.push_back(arg); // Consume arg to tell LLVM about the reference
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arg_constraints.push_back("r"); // Always a register in this case
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}
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// Emit the branch
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llvm_asm(irb, exit_fn, args, fmt::merge(arg_constraints, ","), f.getContext());
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// Successful patch
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return true;
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}
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bool GHC_frame_preservation_pass::is_ret_instruction(const llvm::Instruction* i)
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{
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if (llvm::isa<llvm::ReturnInst>(i))
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@ -515,8 +550,8 @@ namespace aarch64
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const auto restore_x30 = [&](llvm::Instruction* where)
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{
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const auto x30_tail_restore = fmt::format(
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"ldr x30, [x%u, #%u];\n", // Load x30 from thread context
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static_cast<u32>(thread_context_reg),
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"ldr x30, [%s, #%u];\n", // Load x30 from thread context
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gpr_names[thread_context_reg],
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m_config.hypervisor_context_offset);
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ensure(where);
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@ -545,10 +580,10 @@ namespace aarch64
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const auto callee = ci->getCalledFunction();
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const std::string callee_name = callee ? callee->getName().str() : "__indirect";
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auto base_reg = get_base_register_for_call(callee_name, m_config.base_register_lookup.empty() ? gpr::x19 : gpr::xzr);
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auto base_reg = get_base_register_for_call(callee_name, m_config.base_register_lookup.empty() ? gpr::x19 : gpr::x30);
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// Check if the call is unexpected. We cannot guarantee that the reload is well-formed in such scenarios
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if (base_reg == gpr::xzr)
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if (base_reg == gpr::x30)
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{
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if (callee)
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{
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@ -16,8 +16,26 @@ namespace aarch64
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x0 = 0,
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x1, x2, x3, x4, x5, x6, x7, x8, x9,
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x10, x11, x12, x13, x14, x15, x16, x17, x18, x19,
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x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30,
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xzr, pc, sp
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x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30
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};
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enum spr : s32
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{
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xzr = 0,
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pc,
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sp
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};
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static const char* gpr_names[] =
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{
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9",
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"x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19",
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"x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30"
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};
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static const char* spr_names[] =
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{
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"xzr", "pc", "sp"
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};
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// On non-x86 architectures GHC runs stackless. SP is treated as a pointer to scratchpad memory.
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@ -50,6 +68,7 @@ namespace aarch64
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{
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bool debug_info = false; // Record debug information
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bool use_stack_frames = true; // Allocate a stack frame for each function. The gateway can alternatively manage a global stack to use as scratch.
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bool optimize = true; // Optimize instructions when possible. Set to false when debugging.
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u32 hypervisor_context_offset = 0; // Offset within the "thread" object where we can find the hypervisor context (registers configured at gateway).
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std::function<bool(const std::string&)> exclusion_callback; // [Optional] Callback run on each function before transform. Return "true" to exclude from frame processing.
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std::vector<std::pair<std::string, gpr>> base_register_lookup; // [Optional] Function lookup table to determine the location of the "thread" context.
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@ -73,6 +92,14 @@ namespace aarch64
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gpr get_base_register_for_call(const std::string& callee_name, gpr default_reg = gpr::x19);
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void process_leaf_function(llvm::IRBuilder<>* irb, llvm::Function& f);
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bool patch_tail_call(
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llvm::IRBuilder<>* irb,
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llvm::Function& f,
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llvm::CallInst* where,
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const instruction_info_t& instruction_info,
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const function_info_t& function_info,
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const std::string& frame_epilogue);
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public:
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GHC_frame_preservation_pass(const config_t& configuration);
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