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SPU Analyser: fix reg origin regression
Propagate phi instead of claiming new values
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4bd022f778
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@ -1956,9 +1956,18 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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// Process block targets
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for (u32 target : block.targets)
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{
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const auto tfound = m_bbs.find(target);
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if (tfound == m_bbs.end())
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{
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continue;
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}
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auto& tb = tfound->second;
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const u32 value = m_entry_info[target / 4] ? target : block.chunk;
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if (u32& tval = m_bbs[target].chunk; tval < 0x40000)
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if (u32& tval = tb.chunk; tval < 0x40000)
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{
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// TODO: fix condition
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if (tval != value && !m_entry_info[target / 4])
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@ -2006,7 +2015,14 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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for (u32 target : block.targets)
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{
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auto& tb = m_bbs.at(target);
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const auto tfound = m_bbs.find(target);
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if (tfound == m_bbs.end())
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{
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continue;
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}
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auto& tb = tfound->second;
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if (!tb.analysed)
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{
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@ -2052,13 +2068,20 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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for (u32 target : block.targets)
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{
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auto& tb = m_bbs.at(target);
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const auto tfound = m_bbs.find(target);
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if (tfound == m_bbs.end())
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{
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continue;
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}
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auto& tb = tfound->second;
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for (u32 i = 0; i < s_reg_max; i++)
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{
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if (tb.chunk == block.chunk && tb.reg_origin[i] != -1)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin[i] == -1 ? addr : block.reg_origin[i];
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const u32 expected = block.reg_mod[i] ? addr : block.reg_origin[i];
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if (tb.reg_origin[i] == 0x80000000)
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{
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@ -2081,7 +2104,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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if (tb.reg_origin_abs[i] != -2)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin_abs[i] >> 31 ? addr : block.reg_origin_abs[i];
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const u32 expected = block.reg_mod[i] ? addr : block.reg_origin_abs[i];
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if (tb.reg_origin_abs[i] == 0x80000000)
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{
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@ -2089,7 +2112,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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}
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else if (tb.reg_origin_abs[i] != expected)
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{
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if (tb.reg_origin_abs[i] == 0x40000 || (!block.reg_mod[i] && (block.reg_origin_abs[i] == -2 || block.reg_origin_abs[i] == 0x40000)))
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if (tb.reg_origin_abs[i] == 0x40000 || expected == -2 || expected == 0x40000)
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{
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// Set -2: sticky value indicating possible external reg origin (0x40000)
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tb.reg_origin_abs[i] = -2;
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