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ppu: Improve LWSYNC

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Block load<->load reordering as real lwsync.
This commit is contained in:
Eladash 2019-08-09 19:35:42 +03:00 committed by Ivan
parent 4f00af6000
commit 4b82006984
4 changed files with 12 additions and 12 deletions
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2
rpcs3/Emu/Cell/Modules/cellSpurs.cpp
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@ -2577,7 +2577,7 @@ s32 _cellSpursWorkloadFlagReceiver(vm::ptr<CellSpurs> spurs, u32 wid, u32 is_set
return CELL_SPURS_POLICY_MODULE_ERROR_STAT; return CELL_SPURS_POLICY_MODULE_ERROR_STAT;
} }
std::atomic_thread_fence(std::memory_order_seq_cst); std::atomic_thread_fence(std::memory_order_acq_rel);
if (s32 res = spurs->wklFlag.flag.atomic_op([spurs, wid, is_set](be_t<u32>& flag) -> s32 if (s32 res = spurs->wklFlag.flag.atomic_op([spurs, wid, is_set](be_t<u32>& flag) -> s32
{ {

14
rpcs3/Emu/Cell/Modules/cellSync.cpp
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@ -87,7 +87,7 @@ error_code cellSyncMutexLock(ppu_thread& ppu, vm::ptr<CellSyncMutex> mutex)
} }
} }
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
return CELL_OK; return CELL_OK;
} }
@ -196,7 +196,7 @@ error_code cellSyncBarrierTryNotify(vm::ptr<CellSyncBarrier> barrier)
return CELL_SYNC_ERROR_ALIGN; return CELL_SYNC_ERROR_ALIGN;
} }
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
if (!barrier->ctrl.atomic_op<&CellSyncBarrier::try_notify>()) if (!barrier->ctrl.atomic_op<&CellSyncBarrier::try_notify>())
{ {
@ -220,7 +220,7 @@ error_code cellSyncBarrierWait(ppu_thread& ppu, vm::ptr<CellSyncBarrier> barrier
return CELL_SYNC_ERROR_ALIGN; return CELL_SYNC_ERROR_ALIGN;
} }
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
while (!barrier->ctrl.atomic_op<&CellSyncBarrier::try_wait>()) while (!barrier->ctrl.atomic_op<&CellSyncBarrier::try_wait>())
{ {
@ -247,7 +247,7 @@ error_code cellSyncBarrierTryWait(vm::ptr<CellSyncBarrier> barrier)
return CELL_SYNC_ERROR_ALIGN; return CELL_SYNC_ERROR_ALIGN;
} }
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
if (!barrier->ctrl.atomic_op<&CellSyncBarrier::try_wait>()) if (!barrier->ctrl.atomic_op<&CellSyncBarrier::try_wait>())
{ {
@ -281,7 +281,7 @@ error_code cellSyncRwmInitialize(vm::ptr<CellSyncRwm> rwm, vm::ptr<void> buffer,
rwm->size = buffer_size; rwm->size = buffer_size;
rwm->buffer = buffer; rwm->buffer = buffer;
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
return CELL_OK; return CELL_OK;
} }
@ -453,7 +453,7 @@ error_code cellSyncQueueInitialize(vm::ptr<CellSyncQueue> queue, vm::ptr<u8> buf
queue->depth = depth; queue->depth = depth;
queue->buffer = buffer; queue->buffer = buffer;
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
return CELL_OK; return CELL_OK;
} }
@ -866,7 +866,7 @@ error_code cellSyncLFQueueInitialize(vm::ptr<CellSyncLFQueue> queue, vm::cptr<vo
} }
} }
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
} }
else else
{ {

4
rpcs3/Emu/Cell/Modules/sys_lwmutex_.cpp
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@ -130,7 +130,7 @@ error_code sys_lwmutex_lock(ppu_thread& ppu, vm::ptr<sys_lwmutex_t> lwmutex, u64
// recursive locking succeeded // recursive locking succeeded
lwmutex->recursive_count++; lwmutex->recursive_count++;
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
return CELL_OK; return CELL_OK;
} }
@ -290,7 +290,7 @@ error_code sys_lwmutex_trylock(ppu_thread& ppu, vm::ptr<sys_lwmutex_t> lwmutex)
// recursive locking succeeded // recursive locking succeeded
lwmutex->recursive_count++; lwmutex->recursive_count++;
std::atomic_thread_fence(std::memory_order_release); std::atomic_thread_fence(std::memory_order_acq_rel);
return CELL_OK; return CELL_OK;
} }

4
rpcs3/Emu/Cell/PPUTranslator.cpp
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@ -3106,8 +3106,8 @@ void PPUTranslator::LFSUX(ppu_opcode_t op)
void PPUTranslator::SYNC(ppu_opcode_t op) void PPUTranslator::SYNC(ppu_opcode_t op)
{ {
// sync: Full seq cst barrier // sync: Full seq cst barrier
// lwsync: Release barrier // lwsync: Acq/Release barrier
m_ir->CreateFence(op.l10 ? AtomicOrdering::Release : AtomicOrdering::SequentiallyConsistent); m_ir->CreateFence(op.l10 ? AtomicOrdering::AcquireRelease : AtomicOrdering::SequentiallyConsistent);
} }
void PPUTranslator::LFDX(ppu_opcode_t op) void PPUTranslator::LFDX(ppu_opcode_t op)