diff --git a/rpcs3/Emu/Cell/SPUInterpreter.h b/rpcs3/Emu/Cell/SPUInterpreter.h
index b5d80a691e..8a8ec790a2 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.h
+++ b/rpcs3/Emu/Cell/SPUInterpreter.h
@@ -61,17 +61,6 @@ private:
 	void MFSPR(u32 rt, u32 sa)
 	{
 		UNIMPLEMENTED();
-		//If register is a dummy register (register labeled 0x0)
-		if(sa == 0x0)
-		{
-			CPU.GPR[rt]._u128.hi = 0x0;
-			CPU.GPR[rt]._u128.lo = 0x0;
-		}
-		else
-		{
-			CPU.GPR[rt]._u128.hi =  CPU.SPR[sa]._u128.hi;
-			CPU.GPR[rt]._u128.lo =  CPU.SPR[sa]._u128.lo;
-		}
 	}
 	void RDCH(u32 rt, u32 ra)
 	{
@@ -267,11 +256,7 @@ private:
 	}
 	void MTSPR(u32 rt, u32 sa)
 	{
-		if(sa != 0)
-		{
-			CPU.SPR[sa]._u128.hi = CPU.GPR[rt]._u128.hi;
-			CPU.SPR[sa]._u128.lo = CPU.GPR[rt]._u128.lo;
-		}
+		UNIMPLEMENTED();
 	}
 	void WRCH(u32 ra, u32 rt)
 	{
diff --git a/rpcs3/Emu/Cell/SPURecompiler.h b/rpcs3/Emu/Cell/SPURecompiler.h
index 6bdcddf1cb..e08623ab43 100644
--- a/rpcs3/Emu/Cell/SPURecompiler.h
+++ b/rpcs3/Emu/Cell/SPURecompiler.h
@@ -471,17 +471,6 @@ private:
 	void MFSPR(u32 rt, u32 sa)
 	{
 		UNIMPLEMENTED();
-		//If register is a dummy register (register labeled 0x0)
-		if(sa == 0x0)
-		{
-			CPU.GPR[rt]._u128.hi = 0x0;
-			CPU.GPR[rt]._u128.lo = 0x0;
-		}
-		else
-		{
-			CPU.GPR[rt]._u128.hi =  CPU.SPR[sa]._u128.hi;
-			CPU.GPR[rt]._u128.lo =  CPU.SPR[sa]._u128.lo;
-		}
 	}
 	void RDCH(u32 rt, u32 ra)
 	{
@@ -1098,11 +1087,6 @@ private:
 	void MTSPR(u32 rt, u32 sa)
 	{
 		UNIMPLEMENTED();
-		if(sa != 0)
-		{
-			CPU.SPR[sa]._u128.hi = CPU.GPR[rt]._u128.hi;
-			CPU.SPR[sa]._u128.lo = CPU.GPR[rt]._u128.lo;
-		}
 	}
 	void WRCH(u32 ra, u32 rt)
 	{
diff --git a/rpcs3/Emu/Cell/SPUThread.h b/rpcs3/Emu/Cell/SPUThread.h
index e00a086ed5..c794817e6b 100644
--- a/rpcs3/Emu/Cell/SPUThread.h
+++ b/rpcs3/Emu/Cell/SPUThread.h
@@ -310,8 +310,7 @@ union SPU_SNRConfig_hdr
 class SPUThread : public PPCThread
 {
 public:
-	SPU_GPR_hdr GPR[128]; //General-Purpose Register
-	SPU_SPR_hdr SPR[128]; //Special-Purpose Registers
+	SPU_GPR_hdr GPR[128]; //General-Purpose Registers
 	//FPSCR FPSCR;
 	SPU_SNRConfig_hdr cfg; //Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)