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rsx: Discard color mask writes with reserved bits
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parent
8772219492
commit
5fde96d563
@ -167,7 +167,11 @@ void RSXDisAsm::Write(std::string_view str, s32 count, bool is_non_inc, u32 id)
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{
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{
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last_opcode.clear();
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last_opcode.clear();
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if (count >= 0)
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if (count == 1 && !is_non_inc)
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{
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fmt::append(last_opcode, "[%08x] ( )", dump_pc);
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}
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else if (count >= 0)
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{
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{
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fmt::append(last_opcode, "[%08x] (%s%u)", dump_pc, is_non_inc ? "+" : "", count);
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fmt::append(last_opcode, "[%08x] (%s%u)", dump_pc, is_non_inc ? "+" : "", count);
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}
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}
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@ -1592,7 +1592,7 @@ struct registers_decoder<NV4097_SET_SURFACE_ZETA_OFFSET>
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static void dump(std::string& out, const decoded_type& decoded)
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static void dump(std::string& out, const decoded_type& decoded)
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{
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{
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fmt::append(out, "Surface: Z offset: %u", decoded.surface_z_offset());
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fmt::append(out, "Surface: Z offset: 0x%x", decoded.surface_z_offset());
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}
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}
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};
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};
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@ -3040,10 +3040,21 @@ struct registers_decoder<NV4097_SET_COLOR_MASK>
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{
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{
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return value != 0;
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return value != 0;
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}
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}
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u32 is_invalid() const
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{
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return (value & 0xfefefefe) ? value : 0;
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}
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};
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};
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static void dump(std::string& out, const decoded_type& decoded)
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static void dump(std::string& out, const decoded_type& decoded)
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{
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{
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if (u32 invalid_value = decoded.is_invalid())
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{
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fmt::append(out, "Surface: color mask: invalid = 0x%08x", invalid_value);
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return;
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}
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fmt::append(out, "Surface: color mask A = %s R = %s G = %s B = %s"
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fmt::append(out, "Surface: color mask A = %s R = %s G = %s B = %s"
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, print_boolean(decoded.color_a()), print_boolean(decoded.color_r()), print_boolean(decoded.color_g()), print_boolean(decoded.color_b()));
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, print_boolean(decoded.color_a()), print_boolean(decoded.color_r()), print_boolean(decoded.color_g()), print_boolean(decoded.color_b()));
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}
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}
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@ -849,6 +849,23 @@ namespace rsx
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}
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}
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}
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}
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void set_color_mask(thread* rsx, u32 reg, u32 arg)
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{
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if (arg == method_registers.register_previous_value)
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{
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return;
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}
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if (method_registers.decode<NV4097_SET_COLOR_MASK>(arg).is_invalid()) [[ unlikely ]]
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{
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method_registers.decode(reg, method_registers.register_previous_value);
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}
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else
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{
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set_surface_options_dirty_bit(rsx, reg, arg);
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}
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}
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void set_stencil_op(thread* rsx, u32 reg, u32 arg)
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void set_stencil_op(thread* rsx, u32 reg, u32 arg)
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{
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{
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if (arg == method_registers.register_previous_value)
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if (arg == method_registers.register_previous_value)
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@ -3550,7 +3567,7 @@ namespace rsx
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bind(NV4097_SET_DEPTH_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_FUNC, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_FUNC, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_MASK, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_MASK, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_COLOR_MASK, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_COLOR_MASK, nv4097::set_color_mask);
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bind(NV4097_SET_COLOR_MASK_MRT, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_COLOR_MASK_MRT, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_TWO_SIDED_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_TWO_SIDED_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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@ -67,7 +67,7 @@ LogHighlighter::LogHighlighter(QTextDocument* parent) : Highlighter(parent)
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AsmHighlighter::AsmHighlighter(QTextDocument *parent) : Highlighter(parent)
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AsmHighlighter::AsmHighlighter(QTextDocument *parent) : Highlighter(parent)
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{
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{
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addRule("^\b[A-Z0-9]+\b", Qt::darkBlue); // Instructions
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addRule("^\\b[A-Z0-9]+\\b", Qt::darkBlue); // Instructions
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addRule("-?R\\d[^,;\\s]*", Qt::darkRed); // -R0.*
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addRule("-?R\\d[^,;\\s]*", Qt::darkRed); // -R0.*
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addRule("-?H\\d[^,;\\s]*", Qt::red); // -H1.*
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addRule("-?H\\d[^,;\\s]*", Qt::red); // -H1.*
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addRule("-?v\\[\\d\\]*[^,;\\s]*", Qt::darkCyan); // -v[xyz].*
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addRule("-?v\\[\\d\\]*[^,;\\s]*", Qt::darkCyan); // -v[xyz].*
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