From 817fec9684b92005f133f3fa9d6e221b4160d740 Mon Sep 17 00:00:00 2001
From: Nekotekina <nekotekina@gmail.com>
Date: Wed, 26 Aug 2015 05:54:06 +0300
Subject: [PATCH] SPU Cleanup

SPURecompiler improved
Old SPU decoder removed
SPU Interpreters merged
---
 asmjit                                      |    2 +-
 rpcs3/Emu/Cell/RawSPUThread.cpp             |   22 +-
 rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp      | 2576 ++++++++++++++
 rpcs3/Emu/Cell/SPUASMJITRecompiler.h        |  309 ++
 rpcs3/Emu/Cell/SPUAnalyser.cpp              |  267 ++
 rpcs3/Emu/Cell/SPUAnalyser.h                |  269 ++
 rpcs3/Emu/Cell/SPUContext.h                 |    3 +-
 rpcs3/Emu/Cell/SPUDecoder.h                 |   25 -
 rpcs3/Emu/Cell/SPUDisAsm.h                  |  818 ++---
 rpcs3/Emu/Cell/SPUInstrTable.h              |  259 --
 rpcs3/Emu/Cell/SPUInterpreter.cpp           | 1842 +++++++---
 rpcs3/Emu/Cell/SPUInterpreter.h             | 2311 ++-----------
 rpcs3/Emu/Cell/SPUInterpreter2.h            |  514 ---
 rpcs3/Emu/Cell/SPUOpcodes.h                 |  719 ++--
 rpcs3/Emu/Cell/SPURecompiler.cpp            |   75 +
 rpcs3/Emu/Cell/SPURecompiler.h              |  327 +-
 rpcs3/Emu/Cell/SPURecompilerCore.cpp        | 3427 -------------------
 rpcs3/Emu/Cell/SPUThread.cpp                |  163 +-
 rpcs3/Emu/Cell/SPUThread.h                  |  169 +-
 rpcs3/Emu/Memory/vm.cpp                     |   16 +-
 rpcs3/Emu/SysCalls/Modules/cellSpurs.cpp    |   40 +-
 rpcs3/Emu/SysCalls/Modules/cellSpursSpu.cpp |   90 +-
 rpcs3/Emu/SysCalls/lv2/sys_spu.cpp          |   26 +-
 rpcs3/Emu/System.h                          |    3 +-
 rpcs3/Gui/InterpreterDisAsm.cpp             |   36 +-
 rpcs3/Gui/InterpreterDisAsm.h               |    2 +-
 rpcs3/Gui/SettingsDialog.cpp                |    4 +-
 rpcs3/Loader/ELF64.cpp                      |   28 +-
 rpcs3/emucore.vcxproj                       |    9 +-
 rpcs3/emucore.vcxproj.filters               |   27 +-
 30 files changed, 6117 insertions(+), 8261 deletions(-)
 create mode 100644 rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
 create mode 100644 rpcs3/Emu/Cell/SPUASMJITRecompiler.h
 create mode 100644 rpcs3/Emu/Cell/SPUAnalyser.cpp
 create mode 100644 rpcs3/Emu/Cell/SPUAnalyser.h
 delete mode 100644 rpcs3/Emu/Cell/SPUDecoder.h
 delete mode 100644 rpcs3/Emu/Cell/SPUInstrTable.h
 delete mode 100644 rpcs3/Emu/Cell/SPUInterpreter2.h
 create mode 100644 rpcs3/Emu/Cell/SPURecompiler.cpp
 delete mode 100644 rpcs3/Emu/Cell/SPURecompilerCore.cpp

diff --git a/asmjit b/asmjit
index bd0d261e8b..b0dad1af25 160000
--- a/asmjit
+++ b/asmjit
@@ -1 +1 @@
-Subproject commit bd0d261e8b72d1915e64da8a6b5bebae5637fa20
+Subproject commit b0dad1af25fb141bf2b20cf29392194886448832
diff --git a/rpcs3/Emu/Cell/RawSPUThread.cpp b/rpcs3/Emu/Cell/RawSPUThread.cpp
index 90e2b3654d..1ad595d2d9 100644
--- a/rpcs3/Emu/Cell/RawSPUThread.cpp
+++ b/rpcs3/Emu/Cell/RawSPUThread.cpp
@@ -6,10 +6,11 @@
 
 #include "Emu/Cell/RawSPUThread.h"
 
+// Originally, SPU MFC registers are accessed externally in a concurrent manner (don't mix with channels, SPU MFC channels are isolated)
 thread_local spu_mfc_arg_t raw_spu_mfc[8] = {};
 
 RawSPUThread::RawSPUThread(const std::string& name, u32 index)
-	: SPUThread(CPU_THREAD_RAW_SPU, name, COPY_EXPR(fmt::format("RawSPU%d[0x%x] Thread (%s)[0x%08x]", index, m_id, m_name.c_str(), PC)), index, RAW_SPU_BASE_ADDR + RAW_SPU_OFFSET * index)
+	: SPUThread(CPU_THREAD_RAW_SPU, name, COPY_EXPR(fmt::format("RawSPU[%d] Thread (0x%x)[0x%05x]", index, m_id, pc)), index, RAW_SPU_BASE_ADDR + RAW_SPU_OFFSET * index)
 {
 	if (!vm::falloc(offset, 0x40000))
 	{
@@ -45,13 +46,11 @@ bool RawSPUThread::read_reg(const u32 addr, u32& value)
 
 	case SPU_Out_MBox_offs:
 	{
-		bool notify;
+		value = ch_out_mbox.pop();
 
-		std::tie(value, notify) = ch_out_mbox.pop();
-
-		if (notify)
+		if (ch_out_mbox.notification_required)
 		{
-			// notify if necessary
+			// lock for reliable notification
 			std::lock_guard<std::mutex> lock(mutex);
 
 			cv.notify_one();
@@ -170,7 +169,6 @@ bool RawSPUThread::write_reg(const u32 addr, const u32 value)
 
 	case Prxy_QueryMask_offs:
 	{
-		//proxy_tag_mask = value;
 		return true;
 	}
 
@@ -178,7 +176,7 @@ bool RawSPUThread::write_reg(const u32 addr, const u32 value)
 	{
 		if (ch_in_mbox.push(value))
 		{
-			// notify if necessary
+			// lock for reliable notification
 			std::lock_guard<std::mutex> lock(mutex);
 
 			cv.notify_one();
@@ -238,14 +236,14 @@ bool RawSPUThread::write_reg(const u32 addr, const u32 value)
 void RawSPUThread::task()
 {
 	// get next PC and SPU Interrupt status
-	PC = npc.exchange(0);
+	pc = npc.exchange(0);
 
-	set_interrupt_status((PC & 1) != 0);
+	set_interrupt_status((pc & 1) != 0);
 
-	PC &= 0x3FFFC;
+	pc &= 0x3fffc;
 
 	SPUThread::task();
 
 	// save next PC and current SPU Interrupt status
-	npc.store(PC | ((ch_event_stat.load() & SPU_EVENT_INTR_ENABLED) != 0));
+	npc.store(pc | u32{ (ch_event_stat.load() & SPU_EVENT_INTR_ENABLED) != 0 });
 }
diff --git a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
new file mode 100644
index 0000000000..6cbbe716d7
--- /dev/null
+++ b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
@@ -0,0 +1,2576 @@
+#include "stdafx.h"
+#include "Utilities/Log.h"
+#include "Utilities/File.h"
+#include "Emu/System.h"
+
+#include "SPUDisAsm.h"
+#include "SPUThread.h"
+#include "SPUInterpreter.h"
+#include "SPUASMJITRecompiler.h"
+
+#define ASMJIT_STATIC
+#define ASMJIT_DEBUG
+
+#include "asmjit.h"
+
+#define OFFSET_OF(type, x) static_cast<s32>(reinterpret_cast<uintptr_t>(&(((type*)0)->x)))
+
+#define SPU_OFF_128(x) asmjit::host::oword_ptr(*cpu, OFFSET_OF(SPUThread, x))
+#define SPU_OFF_64(x) asmjit::host::qword_ptr(*cpu, OFFSET_OF(SPUThread, x))
+#define SPU_OFF_32(x) asmjit::host::dword_ptr(*cpu, OFFSET_OF(SPUThread, x))
+#define SPU_OFF_16(x) asmjit::host::word_ptr(*cpu, OFFSET_OF(SPUThread, x))
+#define SPU_OFF_8(x) asmjit::host::byte_ptr(*cpu, OFFSET_OF(SPUThread, x))
+
+spu_recompiler::spu_recompiler()
+	: m_jit(std::make_shared<asmjit::JitRuntime>())
+{
+	asmjit::X86CpuInfo inf;
+	asmjit::X86CpuUtil::detect(&inf);
+
+	LOG_SUCCESS(SPU, "SPU Recompiler (ASMJIT) created...");
+
+	const std::string str = fmt::format("SPU JIT initialization...\n\nTitle: %s\nTitle ID: %s\n\n", Emu.GetTitle().c_str(), Emu.GetTitleID().c_str());
+
+	fs::file("SPUJIT.log", fom::write | fom::create | fom::trunc).write(str.c_str(), str.size());
+}
+
+void spu_recompiler::compile(spu_function_t& f)
+{
+	std::lock_guard<std::mutex> lock(m_mutex);
+
+	if (f.compiled)
+	{
+		// return if function already compiled
+		return;
+	}
+
+	if (f.addr >= 0x40000 || f.addr % 4 || f.size == 0 || f.size >= 0x40000 - f.addr || f.size % 4)
+	{
+		// function shouldn't touch the greatest possible address (0x3fffc) as well
+		throw EXCEPTION("Invalid SPU function (addr=0x%05x, size=0x%x)", f.addr, f.size);
+	}
+
+	using namespace asmjit;
+
+	SPUDisAsm dis_asm(CPUDisAsm_InterpreterMode);
+	dis_asm.offset = reinterpret_cast<u8*>(f.data.data()) - f.addr;
+
+	StringLogger logger;
+	logger.setOption(kLoggerOptionBinaryForm, true);
+
+	std::string log = fmt::format("========== SPU FUNCTION 0x%05x - 0x%05x ==========\n\n", f.addr, f.addr + f.size);
+
+	this->m_func = &f;
+
+	X86Compiler compiler(m_jit.get());
+	this->c = &compiler;
+	compiler.setLogger(&logger);
+
+	compiler.addFunc(kFuncConvHost, FuncBuilder2<u32, void*, void*>());
+
+	X86GpVar cpu_var(compiler, kVarTypeIntPtr, "cpu");
+	compiler.setArg(0, cpu_var);
+	compiler.alloc(cpu_var); // ???
+	this->cpu = &cpu_var;
+
+	X86GpVar ls_var(compiler, kVarTypeIntPtr, "ls");
+	compiler.setArg(1, ls_var);
+	compiler.alloc(ls_var); // ???
+	this->ls = &ls_var;
+
+	X86GpVar pos_var(compiler, kVarTypeUInt32, "pos");
+	this->pos = &pos_var;
+	X86GpVar addr_var(compiler, kVarTypeUInt32, "addr");
+	this->addr = &addr_var;
+	X86GpVar qw0_var(compiler, kVarTypeUInt64, "qw0");
+	this->qw0 = &qw0_var;
+	X86GpVar qw1_var(compiler, kVarTypeUInt64, "qw1");
+	this->qw1 = &qw1_var;
+	X86GpVar qw2_var(compiler, kVarTypeUInt64, "qw2");
+	this->qw2 = &qw2_var;
+
+	std::array<X86XmmVar, 10> vec_vars;
+
+	for (u32 i = 0; i < vec_vars.size(); i++)
+	{
+		vec_vars[i] = X86XmmVar{ compiler, kX86VarTypeXmm, fmt::format("vec%d", i).c_str() };
+		vec.at(i) = vec_vars.data() + i;
+	}
+
+	std::vector<Label> pos_labels{ 0x10000 };
+
+	this->labels = pos_labels.data();
+
+	// Initialize labels
+	for (const u32 addr : f.blocks)
+	{
+		if (addr < f.addr || addr >= f.addr + f.size || addr % 4)
+		{
+			throw EXCEPTION("Invalid function block entry (0x%05x)", addr);
+		}
+
+		pos_labels[addr / 4] = Label{ compiler };
+	}
+
+	pos_labels[(f.addr + f.size) / 4] = Label{ compiler };
+
+	Label jt_label{ compiler };
+	this->jt = &jt_label;
+
+	m_pos = f.addr;
+
+	for (const u32 op : f.data)
+	{
+		// Disasm
+		dis_asm.dump_pc = m_pos;
+		dis_asm.do_disasm(op);
+
+		// Bind label if initialized
+		if (pos_labels[m_pos / 4].isInitialized())
+		{
+			compiler.bind(pos_labels[m_pos / 4]);
+			compiler.addComment("Block:");
+		}
+
+		compiler.addComment(dis_asm.last_opcode.c_str());
+		log += dis_asm.last_opcode.c_str();
+		log += '\n';
+
+		(this->*spu_recompiler::opcodes[op])({ op });
+
+		// Set next position
+		m_pos += 4;
+	}
+
+	log += '\n';
+
+	// Generate default function end (go to the next address)
+	compiler.bind(pos_labels.at(m_pos / 4));
+	compiler.addComment("Fallthrough:");
+	compiler.mov(pos_var, m_pos);
+	compiler.ret(pos_var);
+
+	// Generate jump table resolver (uses pos_var)
+	compiler.bind(jt_label);
+
+	if (f.jtable.size())
+	{
+		compiler.addComment("Jump table resolver:");
+		compiler.mov(addr_var, pos_var);
+		compiler.and_(addr_var, 0x3fffc);
+	}
+
+	for (const u32 addr : f.jtable)
+	{
+		if (pos_labels[addr / 4].isInitialized())
+		{
+			// It could be binary search or something
+			compiler.cmp(addr_var, addr);
+			compiler.je(pos_labels[addr / 4]);
+		}
+		else
+		{
+			LOG_ERROR(SPU, "Unable to add jump table entry (0x%05x)", addr);
+		}
+	}
+
+	compiler.ret(pos_var);
+
+	// Finalization
+	compiler.endFunc();
+
+	// Append log file
+	fs::file log_file("SPUJIT.log", fom::write | fom::append | fom::create);
+
+	// Write log header
+	log_file.write(log.c_str(), log.size());
+
+	// Compile and store function address
+	f.compiled = asmjit_cast<spu_jit_func_t>(compiler.make());
+
+	logger.logString(kLoggerStyleDefault, "\n\n\n");
+
+	// Write ASMJIT logs
+	const auto log_data = logger.getString(); log_file.write(log_data, std::strlen(log_data));
+}
+
+spu_recompiler::XmmLink spu_recompiler::XmmAlloc() // get empty xmm register
+{
+	for (auto& v : vec)
+	{
+		if (v)
+		{
+			return XmmLink{ v };
+		}
+	}
+
+	throw EXCEPTION("Out of Xmm Vars");
+}
+
+spu_recompiler::XmmLink spu_recompiler::XmmGet(s8 reg, XmmType type) // get xmm register with specific SPU reg
+{
+	XmmLink result = XmmAlloc();
+
+	switch (type)
+	{
+	case XmmType::Int: c->movdqa(result, SPU_OFF_128(gpr[reg])); break;
+	case XmmType::Float: c->movaps(result, SPU_OFF_128(gpr[reg])); break;
+	case XmmType::Double: c->movapd(result, SPU_OFF_128(gpr[reg])); break;
+	default: throw EXCEPTION("Invalid XmmType");
+	}
+
+	return result;
+}
+
+inline asmjit::X86Mem spu_recompiler::XmmConst(v128 data)
+{
+	return c->newXmmConst(asmjit::kConstScopeLocal, asmjit::Vec128::fromUq(data._u64[0], data._u64[1]));
+}
+
+inline asmjit::X86Mem spu_recompiler::XmmConst(__m128 data)
+{
+	return XmmConst(v128::fromF(data));
+}
+
+inline asmjit::X86Mem spu_recompiler::XmmConst(__m128i data)
+{
+	return XmmConst(v128::fromV(data));
+}
+
+void spu_recompiler::InterpreterCall(spu_opcode_t op)
+{
+	auto gate = [](SPUThread* _spu, u32 opcode, spu_inter_func_t _func) -> u32
+	{
+		try
+		{
+			// TODO: check correctness
+
+			const u32 old_pc = _spu->pc;
+
+			_func(*_spu, { opcode });
+
+			if (old_pc != _spu->pc)
+			{
+				_spu->pc += 4;
+				return 2;
+			}
+
+			_spu->pc += 4;
+			return 0;
+		}
+		catch (...)
+		{
+			_spu->pending_exception = std::current_exception();
+			return 1;
+		}
+	};
+
+	c->mov(SPU_OFF_32(pc), m_pos);
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, u32(SPUThread*, u32, spu_inter_func_t)>(gate)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<u32, void*, u32, void*>());
+	call->setArg(0, *cpu);
+	call->setArg(1, asmjit::imm_u(op.opcode));
+	call->setArg(2, asmjit::imm_ptr(asmjit_cast<void*>(spu_interpreter::fast::g_spu_opcode_table[op.opcode])));
+	call->setRet(0, *addr);
+
+	// return immediately if an error occured
+	asmjit::Label next(*c);
+	c->test(*addr, *addr);
+	c->jz(next);
+	c->mov(*pos, SPU_OFF_32(pc));
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::FunctionCall()
+{
+	auto gate = [](SPUThread* _spu, u32 link) -> u32
+	{
+		try
+		{
+			if (_spu->pc == link)
+			{
+				LOG_ERROR(SPU, "Branch-to-next (pc=0x%05x)", _spu->pc);
+			}
+			else if (_spu->pc == link - 4)
+			{
+				LOG_ERROR(SPU, "Branch-to-self (pc=0x%05x)", _spu->pc);
+			}
+
+			// TODO: analyse stack consistency
+			// TODO: check correctness
+
+			while (!_spu->m_state.load() || !_spu->check_status())
+			{
+				// try to use non-virtual call since the type is known
+				static_cast<SPURecompilerDecoder&>(*_spu->m_dec).DecodeMemory(_spu->offset + _spu->pc);
+
+				if (_spu->pc == link)
+				{
+					// returned successfully
+					return 0;
+				}
+			}
+
+			return 2;
+		}
+		catch (...)
+		{
+			_spu->pending_exception = std::current_exception();
+			return 1;
+		}
+	};
+
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, u32(SPUThread*, u32)>(gate)), asmjit::kFuncConvHost, asmjit::FuncBuilder2<u32, SPUThread*, u32>());
+	call->setArg(0, *cpu);
+	call->setArg(1, asmjit::imm_u(m_pos + 4));
+	call->setRet(0, *addr);
+
+	// return immediately if an error occured
+	asmjit::Label next(*c);
+	c->test(*addr, *addr);
+	c->jz(next);
+	c->mov(*pos, SPU_OFF_32(pc));
+	c->ret(*pos);
+	c->bind(next);
+
+	//asmjit::Label next2(*c);
+	//c->cmp(SPU_OFF_32(pc), m_pos + 4); // compare current PC with next position
+	//c->je(next2);
+	//c->mov(*pos, SPU_OFF_32(pc));
+	//c->jmp(*jt); // go to the jump table resolver
+	//c->bind(next2);
+}
+
+void spu_recompiler::STOP(spu_opcode_t op)
+{
+	InterpreterCall(op); // TODO
+}
+
+void spu_recompiler::LNOP(spu_opcode_t op)
+{
+}
+
+void spu_recompiler::SYNC(spu_opcode_t op)
+{
+	// This instruction must be used following a store instruction that modifies the instruction stream.
+	c->mfence();
+}
+
+void spu_recompiler::DSYNC(spu_opcode_t op)
+{
+	// This instruction forces all earlier load, store, and channel instructions to complete before proceeding.
+	c->mfence();
+}
+
+void spu_recompiler::MFSPR(spu_opcode_t op)
+{
+	InterpreterCall(op);
+}
+
+void spu_recompiler::RDCH(spu_opcode_t op)
+{
+	InterpreterCall(op); // TODO
+}
+
+void spu_recompiler::RCHCNT(spu_opcode_t op)
+{
+	InterpreterCall(op); // TODO
+}
+
+void spu_recompiler::SF(spu_opcode_t op)
+{
+	// sub from
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->psubd(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::OR(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->por(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::BG(spu_opcode_t op)
+{
+	// compare if-greater-than
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from32p(0x80000000)));
+	c->pxor(va, vi);
+	c->pxor(vi, SPU_OFF_128(gpr[op.rb]));
+	c->pcmpgtd(va, vi);
+	c->paddd(va, XmmConst(v128::from32p(1)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SFH(spu_opcode_t op)
+{
+	// sub from (halfword)
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->psubw(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::NOR(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->por(va, SPU_OFF_128(gpr[op.rb]));
+	c->pxor(va, XmmConst(v128::from32p(0xffffffff)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ABSDB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& vm = XmmAlloc();
+	c->movdqa(vm, va);
+	c->pmaxub(va, vb);
+	c->pminub(vb, vm);
+	c->psubb(va, vb);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROT(spu_opcode_t op)
+{
+	auto body = [](u32* t, const u32* a, const s32* b) noexcept
+	{
+		for (u32 i = 0; i < 4; i++)
+		{
+			t[i] = (a[i] << b[i]) | (a[i] >> (32 - b[i]));
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u32*, const u32*, const s32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 4; i++) // unrolled loop
+	//{
+	//	c->mov(qw0->r32(), SPU_OFF_32(gpr[op.ra]._u32[i]));
+	//	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[i]));
+	//	c->rol(qw0->r32(), *addr);
+	//	c->mov(SPU_OFF_32(gpr[op.rt]._u32[i]), qw0->r32());
+	//}
+}
+
+void spu_recompiler::ROTM(spu_opcode_t op)
+{
+	auto body = [](u32* t, const u32* a, const u32* b) noexcept
+	{
+		for (u32 i = 0; i < 4; i++)
+		{
+			t[i] = static_cast<u32>(static_cast<u64>(a[i]) >> (0 - b[i]));
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u32*, const u32*, const u32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 4; i++) // unrolled loop
+	//{
+	//	c->mov(qw0->r32(), SPU_OFF_32(gpr[op.ra]._u32[i]));
+	//	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[i]));
+	//	c->neg(*addr);
+	//	c->shr(*qw0, *addr);
+	//	c->mov(SPU_OFF_32(gpr[op.rt]._u32[i]), qw0->r32());
+	//}
+}
+
+void spu_recompiler::ROTMA(spu_opcode_t op)
+{
+	auto body = [](s32* t, const s32* a, const u32* b) noexcept
+	{
+		for (u32 i = 0; i < 4; i++)
+		{
+			t[i] = static_cast<s32>(static_cast<s64>(a[i]) >> (0 - b[i]));
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(s32*, const s32*, const u32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 4; i++) // unrolled loop
+	//{
+	//	c->movsxd(*qw0, SPU_OFF_32(gpr[op.ra]._u32[i]));
+	//	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[i]));
+	//	c->neg(*addr);
+	//	c->sar(*qw0, *addr);
+	//	c->mov(SPU_OFF_32(gpr[op.rt]._u32[i]), qw0->r32());
+	//}
+}
+
+void spu_recompiler::SHL(spu_opcode_t op)
+{
+	auto body = [](u32* t, const u32* a, const u32* b) noexcept
+	{
+		for (u32 i = 0; i < 4; i++)
+		{
+			t[i] = static_cast<u32>(static_cast<u64>(a[i]) << b[i]);
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u32*, const u32*, const u32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 4; i++) // unrolled loop
+	//{
+	//	c->mov(qw0->r32(), SPU_OFF_32(gpr[op.ra]._u32[i]));
+	//	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[i]));
+	//	c->shl(*qw0, *addr);
+	//	c->mov(SPU_OFF_32(gpr[op.rt]._u32[i]), qw0->r32());
+	//}
+}
+
+void spu_recompiler::ROTH(spu_opcode_t op) //nf
+{
+	auto body = [](u16* t, const u16* a, const s16* b) noexcept
+	{
+		for (u32 i = 0; i < 8; i++)
+		{
+			t[i] = (a[i] << b[i]) | (a[i] >> (16 - b[i]));
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u16*, const u16*, const s16*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 8; i++) // unrolled loop
+	//{
+	//	c->movzx(qw0->r32(), SPU_OFF_16(gpr[op.ra]._u16[i]));
+	//	c->movzx(*addr, SPU_OFF_16(gpr[op.rb]._u16[i]));
+	//	c->rol(qw0->r16(), *addr);
+	//	c->mov(SPU_OFF_16(gpr[op.rt]._u16[i]), qw0->r16());
+	//}
+}
+
+void spu_recompiler::ROTHM(spu_opcode_t op)
+{
+	auto body = [](u16* t, const u16* a, const u16* b) noexcept
+	{
+		for (u32 i = 0; i < 8; i++)
+		{
+			t[i] = static_cast<u16>(static_cast<u32>(a[i]) >> (0 - b[i]));
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u16*, const u16*, const u16*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 8; i++) // unrolled loop
+	//{
+	//	c->movzx(qw0->r32(), SPU_OFF_16(gpr[op.ra]._u16[i]));
+	//	c->movzx(*addr, SPU_OFF_16(gpr[op.rb]._u16[i]));
+	//	c->neg(*addr);
+	//	c->shr(qw0->r32(), *addr);
+	//	c->mov(SPU_OFF_16(gpr[op.rt]._u16[i]), qw0->r16());
+	//}
+}
+
+void spu_recompiler::ROTMAH(spu_opcode_t op)
+{
+	auto body = [](s16* t, const s16* a, const u16* b) noexcept
+	{
+		for (u32 i = 0; i < 8; i++)
+		{
+			t[i] = static_cast<s16>(static_cast<s32>(a[i]) >> (0 - b[i]));
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(s16*, const s16*, const u16*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 8; i++) // unrolled loop
+	//{
+	//	c->movsx(qw0->r32(), SPU_OFF_16(gpr[op.ra]._u16[i]));
+	//	c->movzx(*addr, SPU_OFF_16(gpr[op.rb]._u16[i]));
+	//	c->neg(*addr);
+	//	c->sar(qw0->r32(), *addr);
+	//	c->mov(SPU_OFF_16(gpr[op.rt]._u16[i]), qw0->r16());
+	//}
+}
+
+void spu_recompiler::SHLH(spu_opcode_t op)
+{
+	auto body = [](u16* t, const u16* a, const u16* b) noexcept
+	{
+		for (u32 i = 0; i < 8; i++)
+		{
+			t[i] = static_cast<u16>(static_cast<u32>(a[i]) << b[i]);
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u16*, const u16*, const u16*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+
+	//for (u32 i = 0; i < 8; i++) // unrolled loop
+	//{
+	//	c->movzx(qw0->r32(), SPU_OFF_16(gpr[op.ra]._u16[i]));
+	//	c->movzx(*addr, SPU_OFF_16(gpr[op.rb]._u16[i]));
+	//	c->shl(qw0->r32(), *addr);
+	//	c->mov(SPU_OFF_16(gpr[op.rt]._u16[i]), qw0->r16());
+	//}
+}
+
+void spu_recompiler::ROTI(spu_opcode_t op)
+{
+	// rotate left
+	const int s = op.si7 & 0x1f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& v1 = XmmAlloc();
+	c->movdqa(v1, va);
+	c->pslld(va, s);
+	c->psrld(v1, 32 - s);
+	c->por(va, v1);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTMI(spu_opcode_t op)
+{
+	// shift right logical
+	const int s = (0 - op.si7) & 0x3f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psrld(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTMAI(spu_opcode_t op)
+{
+	// shift right arithmetical
+	const int s = (0 - op.si7) & 0x3f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psrad(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SHLI(spu_opcode_t op)
+{
+	// shift left
+	const int s = op.si7 & 0x3f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pslld(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTHI(spu_opcode_t op)
+{
+	// rotate left (halfword)
+	const int s = op.si7 & 0xf;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& v1 = XmmAlloc();
+	c->movdqa(v1, va);
+	c->psllw(va, s);
+	c->psrlw(v1, 16 - s);
+	c->por(va, v1);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTHMI(spu_opcode_t op)
+{
+	// shift right logical
+	const int s = (0 - op.si7) & 0x1f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psrlw(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTMAHI(spu_opcode_t op)
+{
+	// shift right arithmetical (halfword)
+	const int s = (0 - op.si7) & 0x1f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psraw(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SHLHI(spu_opcode_t op)
+{
+	// shift left (halfword)
+	const int s = op.si7 & 0x1f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psllw(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::A(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->paddd(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::AND(spu_opcode_t op)
+{
+	// and
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pand(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::CG(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from32p(0x80000000)));
+	c->paddd(vb, va);
+	c->pxor(va, vi);
+	c->pxor(vb, vi);
+	c->pcmpgtd(va, vb);
+	c->psrld(va, 31);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::AH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->paddw(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::NAND(spu_opcode_t op)
+{
+	// nand
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pand(va, SPU_OFF_128(gpr[op.rb]));
+	c->pxor(va, XmmConst(v128::from32p(0xffffffff)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::AVGB(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pavgb(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::MTSPR(spu_opcode_t op)
+{
+	InterpreterCall(op);
+}
+
+void spu_recompiler::WRCH(spu_opcode_t op)
+{
+	InterpreterCall(op); // TODO
+}
+
+void spu_recompiler::BIZ(spu_opcode_t op)
+{
+	if (op.d || op.e)
+	{
+		throw EXCEPTION("TODO: enable/disable interrupts");
+	}
+
+	asmjit::Label next(*c);
+
+	c->cmp(SPU_OFF_32(gpr[op.rt]._u32[3]), 0);
+	c->jne(next);
+
+	c->mov(*pos, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*pos, 0x3fffc);
+	//c->or_(*pos, u32{ op.ra != 0 } << 25 | u32{ op.e } << 26 | u32{ op.d } << 27);
+	c->jmp(*jt);
+	c->bind(next);
+}
+
+void spu_recompiler::BINZ(spu_opcode_t op)
+{
+	if (op.d || op.e)
+	{
+		throw EXCEPTION("TODO: enable/disable interrupts");
+	}
+
+	asmjit::Label next(*c);
+
+	c->cmp(SPU_OFF_32(gpr[op.rt]._u32[3]), 0);
+	c->je(next);
+
+	c->mov(*pos, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*pos, 0x3fffc);
+	//c->or_(*pos, u32{ op.ra != 0 } << 25 | u32{ op.e } << 26 | u32{ op.d } << 27);
+	c->jmp(*jt);
+	c->bind(next);
+}
+
+void spu_recompiler::BIHZ(spu_opcode_t op)
+{
+	if (op.d || op.e)
+	{
+		throw EXCEPTION("TODO: enable/disable interrupts");
+	}
+	
+	asmjit::Label next(*c);
+
+	c->cmp(SPU_OFF_16(gpr[op.rt]._u16[6]), 0);
+	c->jne(next);
+
+	c->mov(*pos, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*pos, 0x3fffc);
+	//c->or_(*pos, u32{ op.ra != 0 } << 25 | u32{ op.e } << 26 | u32{ op.d } << 27);
+	c->jmp(*jt);
+	c->bind(next);
+}
+
+void spu_recompiler::BIHNZ(spu_opcode_t op)
+{
+	if (op.d || op.e)
+	{
+		throw EXCEPTION("TODO: enable/disable interrupts");
+	}
+
+	asmjit::Label next(*c);
+
+	c->cmp(SPU_OFF_16(gpr[op.rt]._u16[6]), 0);
+	c->je(next);
+
+	c->mov(*pos, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*pos, 0x3fffc);
+	//c->or_(*pos, u32{ op.ra != 0 } << 25 | u32{ op.e } << 26 | u32{ op.d } << 27);
+	c->jmp(*jt);
+	c->bind(next);
+}
+
+void spu_recompiler::STOPD(spu_opcode_t op)
+{
+	InterpreterCall(op);
+}
+
+void spu_recompiler::STQX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->add(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 0x3fff0);
+
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(asmjit::host::oword_ptr(*ls, *addr), vt);
+}
+
+void spu_recompiler::BI(spu_opcode_t op)
+{
+	if (op.d || op.e)
+	{
+		throw EXCEPTION("TODO: enable/disable interrupts");
+	}
+
+	c->mov(*pos, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*pos, 0x3fffc);
+	//c->or_(*pos, u32{ op.ra != 0 } << 25 | u32{ op.e } << 26 | u32{ op.d } << 27);
+	c->jmp(*jt);
+}
+
+void spu_recompiler::BISL(spu_opcode_t op)
+{
+	if (op.d || op.e)
+	{
+		throw EXCEPTION("TODO: enable/disable interrupts");
+	}
+
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*addr, 0x3fffc);
+	c->mov(SPU_OFF_32(pc), *addr);
+	//c->or_(*pos, 0x2000000 | u32{ op.e } << 26 | u32{ op.d } << 27);
+
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32(0, 0, 0, m_pos + 4)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	FunctionCall();
+}
+
+void spu_recompiler::IRET(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::BISLED(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::HBR(spu_opcode_t op)
+{
+}
+
+void spu_recompiler::GB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pshufb(va, XmmConst(_mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 12, 8, 4, 0)));
+	c->psllq(va, 7);
+	c->pmovmskb(*addr, va);
+	c->pxor(va, va);
+	c->pinsrw(va, *addr, 6);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::GBH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pshufb(va, XmmConst(_mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 14, 12, 10, 8, 6, 4, 2, 0)));
+	c->psllq(va, 7);
+	c->pmovmskb(*addr, va);
+	c->pxor(va, va);
+	c->pinsrw(va, *addr, 6);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::GBB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psllq(va, 7);
+	c->pmovmskb(*addr, va);
+	c->pxor(va, va);
+	c->pinsrw(va, *addr, 6);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FSM(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.fsm));
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*addr, 0xf);
+	c->shl(*addr, 4);
+	c->movdqa(vr, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::FSMH(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.fsmh));
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*addr, 0xff);
+	c->shl(*addr, 4);
+	c->movdqa(vr, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::FSMB(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.fsmb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->and_(*addr, 0xffff);
+	c->shl(*addr, 4);
+	c->movdqa(vr, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::FREST(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->rcpps(va, va);
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FRSQEST(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->andps(va, XmmConst(v128::from32p(0x7fffffff))); // abs
+	c->rsqrtps(va, va);
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::LQX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->add(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 0x3fff0);
+
+	const XmmLink& vt = XmmAlloc();
+	c->movdqa(vt, asmjit::host::oword_ptr(*ls, *addr));
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::ROTQBYBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.rldq_pshufb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 0xf << 3);
+	c->shl(*addr, 1);
+	c->pshufb(va, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTQMBYBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.srdq_pshufb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->shr(*addr, 3);
+	c->neg(*addr);
+	c->and_(*addr, 0x1f);
+	c->shl(*addr, 4);
+	c->pshufb(va, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SHLQBYBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.sldq_pshufb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 0x1f << 3);
+	c->shl(*addr, 1);
+	c->pshufb(va, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CBX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->add(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->not_(*addr);
+	c->and_(*addr, 0xf);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(asmjit::host::byte_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), 0x03);
+}
+
+void spu_recompiler::CHX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->add(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->not_(*addr);
+	c->and_(*addr, 0xe);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(asmjit::host::word_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), 0x0203);
+}
+
+void spu_recompiler::CWX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->add(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->not_(*addr);
+	c->and_(*addr, 0xc);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(asmjit::host::dword_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), 0x00010203);
+}
+
+void spu_recompiler::CDX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->add(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->not_(*addr);
+	c->and_(*addr, 0x8);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(*qw0, asmjit::imm_u(0x0001020304050607));
+	c->mov(asmjit::host::qword_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), *qw0);
+}
+
+void spu_recompiler::ROTQBI(spu_opcode_t op)
+{
+	c->mov(*qw0, SPU_OFF_64(gpr[op.ra]._u64[0]));
+	c->mov(*qw1, SPU_OFF_64(gpr[op.ra]._u64[1]));
+	c->mov(*qw2, *qw0);
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 7);
+	c->shld(*qw0, *qw1, *addr);
+	c->shld(*qw1, *qw2, *addr);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[1]), *qw1);
+}
+
+void spu_recompiler::ROTQMBI(spu_opcode_t op)
+{
+	c->mov(*qw0, SPU_OFF_64(gpr[op.ra]._u64[0]));
+	c->mov(*qw1, SPU_OFF_64(gpr[op.ra]._u64[1]));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->neg(*addr);
+	c->and_(*addr, 7);
+	c->shrd(*qw0, *qw1, *addr);
+	c->shr(*qw1, *addr);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[1]), *qw1);
+}
+
+void spu_recompiler::SHLQBI(spu_opcode_t op)
+{
+	c->mov(*qw0, SPU_OFF_64(gpr[op.ra]._u64[0]));
+	c->mov(*qw1, SPU_OFF_64(gpr[op.ra]._u64[1]));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 7);
+	c->shld(*qw1, *qw0, *addr);
+	c->shl(*qw0, *addr);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[1]), *qw1);
+}
+
+void spu_recompiler::ROTQBY(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.rldq_pshufb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 0xf);
+	c->shl(*addr, 4);
+	c->pshufb(va, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTQMBY(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.srdq_pshufb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->neg(*addr);
+	c->and_(*addr, 0x1f);
+	c->shl(*addr, 4);
+	c->pshufb(va, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SHLQBY(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->mov(*qw0, asmjit::imm_ptr((void*)g_spu_imm.sldq_pshufb));
+	c->mov(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+	c->and_(*addr, 0x1f);
+	c->shl(*addr, 4);
+	c->pshufb(va, asmjit::host::oword_ptr(*qw0, *addr));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ORX(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[0]));
+	c->or_(*addr, SPU_OFF_32(gpr[op.ra]._u32[1]));
+	c->or_(*addr, SPU_OFF_32(gpr[op.ra]._u32[2]));
+	c->or_(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->mov(SPU_OFF_32(gpr[op.rt]._u32[3]), *addr);
+	c->xor_(*addr, *addr);
+	c->mov(SPU_OFF_32(gpr[op.rt]._u32[0]), *addr);
+	c->mov(SPU_OFF_32(gpr[op.rt]._u32[1]), *addr);
+	c->mov(SPU_OFF_32(gpr[op.rt]._u32[2]), *addr);
+}
+
+void spu_recompiler::CBD(spu_opcode_t op)
+{
+	//if (op.ra == 1)
+	//{
+	//	// assuming that SP % 16 is always zero
+	//	const XmmLink& vr = XmmAlloc();
+	//	v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
+	//	value.u8r[op.si7 & 0xf] = 0x03;
+	//	c->movdqa(vr, XmmConst(value));
+	//	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+	//	return;
+	//}
+
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	if (op.si7) c->add(*addr, op.si7);
+	c->not_(*addr);
+	c->and_(*addr, 0xf);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(asmjit::host::byte_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), 0x03);
+}
+
+void spu_recompiler::CHD(spu_opcode_t op)
+{
+	//if (op.ra == 1)
+	//{
+	//	// assuming that SP % 16 is always zero
+	//	const XmmLink& vr = XmmAlloc();
+	//	v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
+	//	value.u16r[(op.si7 >> 1) & 0x7] = 0x0203;
+	//	c->movdqa(vr, XmmConst(value));
+	//	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+	//	return;
+	//}
+
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	if (op.si7) c->add(*addr, op.si7);
+	c->not_(*addr);
+	c->and_(*addr, 0xe);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(asmjit::host::word_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), 0x0203);
+}
+
+void spu_recompiler::CWD(spu_opcode_t op)
+{
+	//if (op.ra == 1)
+	//{
+	//	// assuming that SP % 16 is always zero
+	//	const XmmLink& vr = XmmAlloc();
+	//	v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
+	//	value.u32r[(op.si7 >> 2) & 0x3] = 0x00010203;
+	//	c->movdqa(vr, XmmConst(value));
+	//	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+	//	return;
+	//}
+
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	if (op.si7) c->add(*addr, op.si7);
+	c->not_(*addr);
+	c->and_(*addr, 0xc);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(asmjit::host::dword_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), 0x00010203);
+}
+
+void spu_recompiler::CDD(spu_opcode_t op)
+{
+	//if (op.ra == 1)
+	//{
+	//	// assuming that SP % 16 is always zero
+	//	const XmmLink& vr = XmmAlloc();
+	//	v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
+	//	value.u64r[(op.si7 >> 3) & 0x1] = 0x0001020304050607ull;
+	//	c->movdqa(vr, XmmConst(value));
+	//	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+	//	return;
+	//}
+
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	if (op.si7) c->add(*addr, op.si7);
+	c->not_(*addr);
+	c->and_(*addr, 0x8);
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	c->mov(*qw0, asmjit::imm_u(0x0001020304050607));
+	c->mov(asmjit::host::qword_ptr(*cpu, *addr, 0, OFFSET_OF(SPUThread, gpr[op.rt])), *qw0);
+}
+
+void spu_recompiler::ROTQBII(spu_opcode_t op)
+{
+	c->mov(*qw0, SPU_OFF_64(gpr[op.ra]._u64[0]));
+	c->mov(*qw1, SPU_OFF_64(gpr[op.ra]._u64[1]));
+	c->mov(*qw2, *qw0);
+	c->shld(*qw0, *qw1, op.si7 & 0x7);
+	c->shld(*qw1, *qw2, op.si7 & 0x7);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[1]), *qw1);
+}
+
+void spu_recompiler::ROTQMBII(spu_opcode_t op)
+{
+	c->mov(*qw0, SPU_OFF_64(gpr[op.ra]._u64[0]));
+	c->mov(*qw1, SPU_OFF_64(gpr[op.ra]._u64[1]));
+	c->shrd(*qw0, *qw1, (0 - op.si7) & 0x7);
+	c->shr(*qw1, (0 - op.si7) & 0x7);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[1]), *qw1);
+}
+
+void spu_recompiler::SHLQBII(spu_opcode_t op)
+{
+	c->mov(*qw0, SPU_OFF_64(gpr[op.ra]._u64[0]));
+	c->mov(*qw1, SPU_OFF_64(gpr[op.ra]._u64[1]));
+	c->shld(*qw1, *qw0, op.si7 & 0x7);
+	c->shl(*qw0, op.si7 & 0x7);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._u64[1]), *qw1);
+}
+
+void spu_recompiler::ROTQBYI(spu_opcode_t op)
+{
+	const int s = op.si7 & 0xf;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->palignr(va, va, 16 - s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ROTQMBYI(spu_opcode_t op)
+{
+	const int s = (0 - op.si7) & 0x1f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psrldq(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SHLQBYI(spu_opcode_t op)
+{
+	const int s = op.si7 & 0x1f;
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pslldq(va, s);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::NOP(spu_opcode_t op)
+{
+}
+
+void spu_recompiler::CGT(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpgtd(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::XOR(spu_opcode_t op)
+{
+	// xor
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pxor(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CGTH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpgtw(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::EQV(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pxor(vb, XmmConst(v128::from32p(0xffffffff)));
+	c->pxor(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::CGTB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpgtb(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SUMB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from8p(1)));
+	c->pmaddubsw(va, vi);
+	c->pmaddubsw(vb, vi);
+	c->phaddw(va, vb);
+	c->pshufb(va, XmmConst(_mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+//HGT uses signed values.  HLGT uses unsigned values
+void spu_recompiler::HGT(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._s32[3]));
+	c->cmp(*addr, SPU_OFF_32(gpr[op.rb]._s32[3]));
+
+	asmjit::Label next(*c);
+	c->jng(next);
+	c->mov(*pos, m_pos | 0x1000000);
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::CLZ(spu_opcode_t op)
+{
+	auto body = [](u32* t, const u32* a) noexcept
+	{
+		for (u32 i = 0; i < 4; i++)
+		{
+			t[i] = cntlz32(a[i]);
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u32*, const u32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder2<void, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+
+	//c->mov(*qw0, 32 + 31);
+	//for (u32 i = 0; i < 4; i++) // unrolled loop
+	//{
+	//	c->bsr(*addr, SPU_OFF_32(gpr[op.ra]._u32[i]));
+	//	c->cmovz(*addr, qw0->r32());
+	//	c->xor_(*addr, 31);
+	//	c->mov(SPU_OFF_32(gpr[op.rt]._u32[i]), *addr);
+	//}
+}
+
+void spu_recompiler::XSWD(spu_opcode_t op)
+{
+	c->movsxd(*qw0, SPU_OFF_32(gpr[op.ra]._s32[0]));
+	c->movsxd(*qw1, SPU_OFF_32(gpr[op.ra]._s32[2]));
+	c->mov(SPU_OFF_64(gpr[op.rt]._s64[0]), *qw0);
+	c->mov(SPU_OFF_64(gpr[op.rt]._s64[1]), *qw1);
+}
+
+void spu_recompiler::XSHW(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pslld(va, 16);
+	c->psrad(va, 16);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CNTB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& v1 = XmmAlloc();
+	const XmmLink& vm = XmmAlloc();
+	c->movdqa(v1, va);
+	c->psrlq(v1, 4);
+	c->movdqa(vm, XmmConst(v128::from8p(0xf)));
+	c->pand(va, vm);
+	c->pand(v1, vm);
+	c->movdqa(vm, XmmConst(_mm_set_epi8(4, 3, 3, 2, 3, 2, 2, 1, 3, 2, 2, 1, 2, 1, 1, 0)));
+	c->pshufb(vm, va);
+	c->movdqa(va, XmmConst(_mm_set_epi8(4, 3, 3, 2, 3, 2, 2, 1, 3, 2, 2, 1, 2, 1, 1, 0)));
+	c->pshufb(va, v1);
+	c->paddb(va, vm);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::XSBH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psllw(va, 8);
+	c->psraw(va, 8);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CLGT(spu_opcode_t op)
+{
+	// compare if-greater-than
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from32p(0x80000000)));
+	c->pxor(va, vi);
+	c->pxor(vi, SPU_OFF_128(gpr[op.rb]));
+	c->pcmpgtd(va, vi);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ANDC(spu_opcode_t op)
+{
+	// and not
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pandn(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::FCGT(spu_opcode_t op)
+{
+	// reverted less-than
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Float);
+	c->cmpps(vb, SPU_OFF_128(gpr[op.ra]), 1);
+	c->movaps(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::DFCGT(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::FA(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->addps(va, SPU_OFF_128(gpr[op.rb]));
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->subps(va, SPU_OFF_128(gpr[op.rb]));
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FM(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->mulps(va, SPU_OFF_128(gpr[op.rb]));
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CLGTH(spu_opcode_t op)
+{
+	// compare if-greater-than
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from16p(0x8000)));
+	c->pxor(va, vi);
+	c->pxor(vi, SPU_OFF_128(gpr[op.rb]));
+	c->pcmpgtw(va, vi);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ORC(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pxor(vb, XmmConst(v128::from32p(0xffffffff)));
+	c->por(vb, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::FCMGT(spu_opcode_t op)
+{
+	// reverted less-than
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Float);
+	const XmmLink& vi = XmmAlloc();
+	c->movaps(vi, XmmConst(v128::from32p(0x7fffffff)));
+	c->andps(vb, vi); // abs
+	c->andps(vi, SPU_OFF_128(gpr[op.ra]));
+	c->cmpps(vb, vi, 1);
+	c->movaps(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::DFCMGT(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::DFA(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	c->addpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->movapd(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::DFS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	c->subpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->movapd(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::DFM(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	c->mulpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->movapd(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CLGTB(spu_opcode_t op)
+{
+	// compare if-greater-than
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from8p(0x80)));
+	c->pxor(va, vi);
+	c->pxor(vi, SPU_OFF_128(gpr[op.rb]));
+	c->pcmpgtb(va, vi);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::HLGT(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->cmp(*addr, SPU_OFF_32(gpr[op.rb]._u32[3]));
+
+	asmjit::Label next(*c);
+	c->jna(next);
+	c->mov(*pos, m_pos | 0x1000000);
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::DFMA(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmGet(op.rt, XmmType::Double);
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	c->mulpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->addpd(vr, va);
+	c->movapd(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::DFMS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Double);
+	c->mulpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->subpd(va, vt);
+	c->movapd(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::DFNMS(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmGet(op.rt, XmmType::Double);
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	c->mulpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->subpd(vr, va);
+	c->movapd(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::DFNMA(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Double);
+	c->mulpd(va, SPU_OFF_128(gpr[op.rb]));
+	c->addpd(vt, va);
+	c->xorpd(va, va);
+	c->subpd(va, vt);
+	c->movapd(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CEQ(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpeqd(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::MPYHHU(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& va2 = XmmAlloc();
+	c->movdqa(va2, va);
+	c->pmulhuw(va, vb);
+	c->pmullw(va2, vb);
+	c->pand(va, XmmConst(v128::from32p(0xffff0000)));
+	c->psrld(va2, 16);
+	c->por(va, va2);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ADDX(spu_opcode_t op)
+{
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	c->pand(vt, XmmConst(v128::from32p(1)));
+	c->paddd(vt, SPU_OFF_128(gpr[op.ra]));
+	c->paddd(vt, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::SFX(spu_opcode_t op)
+{
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pandn(vt, XmmConst(v128::from32p(1)));
+	c->psubd(vb, SPU_OFF_128(gpr[op.ra]));
+	c->psubd(vb, vt);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::CGX(spu_opcode_t op) //nf
+{
+	auto body = [](u32* t, const u32* a, const u32* b) noexcept
+	{
+		for (s32 i = 0; i < 4; i++)
+		{
+			t[i] = (static_cast<u64>(t[i] & 1) + a[i] + b[i]) >> 32;
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u32*, const u32*, const u32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+}
+
+void spu_recompiler::BGX(spu_opcode_t op) //nf
+{
+	auto body = [](u32* t, const u32* a, const u32* b) noexcept
+	{
+		for (s32 i = 0; i < 4; i++)
+		{
+			const s64 result = (u64)b[i] - (u64)a[i] - (u64)(1 - (t[i] & 1));
+			t[i] = result >= 0;
+		}
+	};
+
+	c->lea(*qw0, SPU_OFF_128(gpr[op.rt]));
+	c->lea(*qw1, SPU_OFF_128(gpr[op.ra]));
+	c->lea(*qw2, SPU_OFF_128(gpr[op.rb]));
+	asmjit::X86CallNode* call = c->call(asmjit::imm_ptr(asmjit_cast<void*, void(u32*, const u32*, const u32*)>(body)), asmjit::kFuncConvHost, asmjit::FuncBuilder3<void, void*, void*, void*>());
+	call->setArg(0, *qw0);
+	call->setArg(1, *qw1);
+	call->setArg(2, *qw2);
+}
+
+void spu_recompiler::MPYHHA(spu_opcode_t op)
+{
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->psrld(va, 16);
+	c->psrld(vb, 16);
+	c->pmaddwd(va, vb);
+	c->paddd(vt, va);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::MPYHHAU(spu_opcode_t op)
+{
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& va2 = XmmAlloc();
+	c->movdqa(va2, va);
+	c->pmulhuw(va, vb);
+	c->pmullw(va2, vb);
+	c->pand(va, XmmConst(v128::from32p(0xffff0000)));
+	c->psrld(va2, 16);
+	c->paddd(vt, va);
+	c->paddd(vt, va2);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::FSCRRD(spu_opcode_t op)
+{
+	// zero (hack)
+	const XmmLink& v0 = XmmAlloc();
+	c->pxor(v0, v0);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), v0);
+}
+
+void spu_recompiler::FESD(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->shufps(va, va, 0x8d); // _f[0] = _f[1]; _f[1] = _f[3];
+	c->cvtps2pd(va, va);
+	c->movapd(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FRDS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Double);
+	c->cvtpd2ps(va, va);
+	c->shufps(va, va, 0x72); // _f[1] = _f[0]; _f[3] = _f[1]; _f[0] = _f[2] = 0;
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FSCRWR(spu_opcode_t op)
+{
+	// nop (not implemented)
+}
+
+void spu_recompiler::DFTSV(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::FCEQ(spu_opcode_t op)
+{
+	// compare equal
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Float);
+	c->cmpps(vb, SPU_OFF_128(gpr[op.ra]), 0);
+	c->movaps(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::DFCEQ(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::MPY(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from32p(0xffff)));
+	c->pand(va, vi);
+	c->pand(vb, vi);
+	c->pmaddwd(va, vb);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::MPYH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->psrld(va, 16);
+	c->pmullw(va, vb);
+	c->pslld(va, 16);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::MPYHH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->psrld(va, 16);
+	c->psrld(vb, 16);
+	c->pmaddwd(va, vb);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::MPYS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	c->pmulhw(va, vb);
+	c->pslld(va, 16);
+	c->psrad(va, 16);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CEQH(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpeqw(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FCMEQ(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Float);
+	const XmmLink& vi = XmmAlloc();
+	c->movaps(vi, XmmConst(v128::from32p(0x7fffffff)));
+	c->andps(vb, vi); // abs
+	c->andps(vi, SPU_OFF_128(gpr[op.ra]));
+	c->cmpps(vb, vi, 0); // ==
+	c->movaps(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::DFCMEQ(spu_opcode_t op)
+{
+	throw EXCEPTION("Unexpected instruction");
+}
+
+void spu_recompiler::MPYU(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& va2 = XmmAlloc();
+	c->movdqa(va2, va);
+	c->pmulhuw(va, vb);
+	c->pmullw(va2, vb);
+	c->pslld(va, 16);
+	c->pand(va2, XmmConst(v128::from32p(0xffff)));
+	c->por(va, va2);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CEQB(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpeqb(va, SPU_OFF_128(gpr[op.rb]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::FI(spu_opcode_t op)
+{
+	// Floating Interpolate
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Float);
+	c->movaps(SPU_OFF_128(gpr[op.rt]), vb);
+}
+
+void spu_recompiler::HEQ(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._s32[3]));
+	c->cmp(*addr, SPU_OFF_32(gpr[op.rb]._s32[3]));
+
+	asmjit::Label next(*c);
+	c->jne(next);
+	c->mov(*pos, m_pos | 0x1000000);
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::CFLTS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	const XmmLink& vi = XmmAlloc();
+	if (op.si8 != 173) c->mulps(va, XmmConst(_mm_set1_ps(exp2f(static_cast<float>(173 - (op.si8 & 0xff)))))); // scale
+	c->movaps(vi, XmmConst(_mm_set1_ps(exp2f(31))));
+	c->cmpps(vi, va, 2);
+	c->cvttps2dq(va, va); // convert to ints with truncation
+	c->pxor(va, vi); // fix result saturation (0x80000000 -> 0x7fffffff)
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CFLTU(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	const XmmLink& vs = XmmAlloc();
+	const XmmLink& vs2 = XmmAlloc();
+	const XmmLink& vs3 = XmmAlloc();
+	if (op.si8 != 173) c->mulps(va, XmmConst(_mm_set1_ps(exp2f(static_cast<float>(173 - (op.si8 & 0xff)))))); // scale
+	c->maxps(va, XmmConst(_mm_set1_ps(0.0f))); // saturate
+	c->movaps(vs, va); // copy scaled value
+	c->movaps(vs2, va);
+	c->movaps(vs3, XmmConst(_mm_set1_ps(exp2f(31))));
+	c->subps(vs2, vs3);
+	c->cmpps(vs3, vs, 2);
+	c->andps(vs2, vs3);
+	c->cvttps2dq(va, va);
+	c->cmpps(vs, XmmConst(_mm_set1_ps(exp2f(32))), 5);
+	c->cvttps2dq(vs2, vs2);
+	c->por(va, vs);
+	c->por(va, vs2);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CSFLT(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->cvtdq2ps(va, va); // convert to floats
+	if (op.si8 != 155) c->mulps(va, XmmConst(_mm_set1_ps(exp2f(static_cast<float>((op.si8 & 0xff) - 155))))); // scale
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CUFLT(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& v1 = XmmAlloc();
+	c->movdqa(v1, va);
+	c->pand(va, XmmConst(v128::from32p(0x7fffffff)));
+	c->cvtdq2ps(va, va); // convert to floats
+	c->psrad(v1, 31); // generate mask from sign bit
+	c->andps(v1, XmmConst(_mm_set1_ps(exp2f(31)))); // generate correction component
+	c->addps(va, v1); // add correction component
+	if (op.si8 != 155) c->mulps(va, XmmConst(_mm_set1_ps(exp2f(static_cast<float>((op.si8 & 0xff) - 155))))); // scale
+	c->movaps(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::BRZ(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(m_pos, op.si16);
+
+	c->cmp(SPU_OFF_32(gpr[op.rt]._u32[3]), 0);
+
+	if (labels[target / 4].isInitialized())
+	{
+		c->je(labels[target / 4]);
+	}
+	else
+	{
+		if (target >= m_func->addr && target < m_func->addr + m_func->size)
+		{
+			LOG_ERROR(SPU, "Local block not registered (brz 0x%x)", target);
+		}
+
+		asmjit::Label next(*c);
+		c->jne(next);
+		c->mov(*pos, target);
+		c->ret(*pos);
+		c->bind(next);
+	}
+}
+
+void spu_recompiler::STQA(spu_opcode_t op)
+{
+	const u32 lsa = (op.si16 << 2) & 0x3fff0;
+
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(asmjit::host::oword_ptr(*ls, lsa), vt);
+}
+
+void spu_recompiler::BRNZ(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(m_pos, op.si16);
+
+	c->cmp(SPU_OFF_32(gpr[op.rt]._u32[3]), 0);
+
+	if (labels[target / 4].isInitialized())
+	{
+		c->jne(labels[target / 4]);
+	}
+	else
+	{
+		if (target >= m_func->addr && target < m_func->addr + m_func->size)
+		{
+			LOG_ERROR(SPU, "Local block not registered (brnz 0x%x)", target);
+		}
+
+		asmjit::Label next(*c);
+		c->je(next);
+		c->mov(*pos, target);
+		c->ret(*pos);
+		c->bind(next);
+	}
+}
+
+void spu_recompiler::BRHZ(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(m_pos, op.si16);
+
+	c->cmp(SPU_OFF_16(gpr[op.rt]._u16[6]), 0);
+
+	if (labels[target / 4].isInitialized())
+	{
+		c->je(labels[target / 4]);
+	}
+	else
+	{
+		if (target >= m_func->addr && target < m_func->addr + m_func->size)
+		{
+			LOG_ERROR(SPU, "Local block not registered (brhz 0x%x)", target);
+		}
+
+		asmjit::Label next(*c);
+		c->jne(next);
+		c->mov(*pos, target);
+		c->ret(*pos);
+		c->bind(next);
+	}
+}
+
+void spu_recompiler::BRHNZ(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(m_pos, op.si16);
+
+	c->cmp(SPU_OFF_16(gpr[op.rt]._u16[6]), 0);
+
+	if (labels[target / 4].isInitialized())
+	{
+		c->jne(labels[target / 4]);
+	}
+	else
+	{
+		if (target >= m_func->addr && target < m_func->addr + m_func->size)
+		{
+			LOG_ERROR(SPU, "Local block not registered (brhnz 0x%x)", target);
+		}
+
+		asmjit::Label next(*c);
+		c->je(next);
+		c->mov(*pos, target);
+		c->ret(*pos);
+		c->bind(next);
+	}
+}
+
+void spu_recompiler::STQR(spu_opcode_t op)
+{
+	const u32 lsa = spu_branch_target(m_pos, op.si16) & 0x3fff0;
+
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(asmjit::host::oword_ptr(*ls, lsa), vt);
+}
+
+void spu_recompiler::BRA(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(0, op.si16);
+
+	if (labels[target / 4].isInitialized())
+	{
+		c->jmp(labels[target / 4]);
+	}
+	else
+	{
+		if (target >= m_func->addr && target < m_func->addr + m_func->size)
+		{
+			LOG_ERROR(SPU, "Local block not registered (bra 0x%x)", target);
+		}
+
+		c->mov(*pos, target);
+		c->ret(*pos);
+	}
+}
+
+void spu_recompiler::LQA(spu_opcode_t op)
+{
+	const u32 lsa = (op.si16 << 2) & 0x3fff0;
+
+	const XmmLink& vt = XmmAlloc();
+	c->movdqa(vt, asmjit::host::oword_ptr(*ls, lsa));
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::BRASL(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(0, op.si16);
+
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32(0, 0, 0, m_pos + 4)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	if (target == m_pos + 4)
+	{
+		// branch-to-next, probably makes sense only for BRSL
+		return;
+	}
+
+	c->mov(SPU_OFF_32(pc), target);
+
+	FunctionCall();
+}
+
+void spu_recompiler::BR(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(m_pos, op.si16);
+
+	if (labels[target / 4].isInitialized())
+	{
+		c->jmp(labels[target / 4]);
+	}
+	else
+	{
+		if (target >= m_func->addr && target < m_func->addr + m_func->size)
+		{
+			LOG_ERROR(SPU, "Local block not registered (brz 0x%x)", target);
+		}
+
+		c->mov(*pos, target);
+		c->ret(*pos);
+	}
+}
+
+void spu_recompiler::FSMBI(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(g_spu_imm.fsmb[op.si16 & 0xffff]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::BRSL(spu_opcode_t op)
+{
+	const u32 target = spu_branch_target(m_pos, op.si16);
+
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32(0, 0, 0, m_pos + 4)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+
+	if (target == m_pos + 4)
+	{
+		// branch-to-next
+		return;
+	}
+
+	c->mov(SPU_OFF_32(pc), target);
+
+	FunctionCall();
+}
+
+void spu_recompiler::LQR(spu_opcode_t op)
+{
+	const u32 lsa = spu_branch_target(m_pos, op.si16) & 0x3fff0;
+
+	const XmmLink& vt = XmmAlloc();
+	c->movdqa(vt, asmjit::host::oword_ptr(*ls, lsa));
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::IL(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32p(op.si16)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::ILHU(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32p(op.si16 << 16)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::ILH(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32p(op.si16)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::IOHL(spu_opcode_t op)
+{
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	c->por(vt, XmmConst(v128::from32p(op.si16 & 0xffff)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::ORI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	if (op.si10) c->por(va, XmmConst(v128::from32p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ORHI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->por(va, XmmConst(v128::from16p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ORBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->por(va, XmmConst(v128::from8p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::SFI(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32p(op.si10)));
+	c->psubd(vr, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::SFHI(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from16p(op.si10)));
+	c->psubw(vr, SPU_OFF_128(gpr[op.ra]));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::ANDI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pand(va, XmmConst(v128::from32p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ANDHI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pand(va, XmmConst(v128::from16p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::ANDBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pand(va, XmmConst(v128::from8p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::AI(spu_opcode_t op)
+{
+	// add
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->paddd(va, XmmConst(v128::from32p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::AHI(spu_opcode_t op)
+{
+	// add
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->paddw(va, XmmConst(v128::from16p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::STQD(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	if (op.si10) c->add(*addr, op.si10 << 4);
+	c->and_(*addr, 0x3fff0);
+
+	const XmmLink& vt = XmmGet(op.rt, XmmType::Int);
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(asmjit::host::oword_ptr(*ls, *addr), vt);
+}
+
+void spu_recompiler::LQD(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	if (op.si10) c->add(*addr, op.si10 << 4);
+	c->and_(*addr, 0x3fff0);
+
+	const XmmLink& vt = XmmAlloc();
+	c->movdqa(vt, asmjit::host::oword_ptr(*ls, *addr));
+	c->pshufb(vt, XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vt);
+}
+
+void spu_recompiler::XORI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pxor(va, XmmConst(v128::from32p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::XORHI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pxor(va, XmmConst(v128::from16p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::XORBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pxor(va, XmmConst(v128::from8p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CGTI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpgtd(va, XmmConst(v128::from32p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CGTHI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpgtw(va, XmmConst(v128::from16p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CGTBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpgtb(va, XmmConst(v128::from8p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::HGTI(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._s32[3]));
+	c->cmp(*addr, op.si10);
+
+	asmjit::Label next(*c);
+	c->jng(next);
+	c->mov(*pos, m_pos | 0x1000000);
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::CLGTI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pxor(va, XmmConst(v128::from32p(0x80000000)));
+	c->pcmpgtd(va, XmmConst(v128::from32p((u32)op.si10 - 0x80000000)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CLGTHI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pxor(va, XmmConst(v128::from16p(0x8000)));
+	c->pcmpgtw(va, XmmConst(v128::from16p((u16)op.si10 - 0x8000)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CLGTBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->psubb(va, XmmConst(v128::from8p(0x80)));
+	c->pcmpgtb(va, XmmConst(v128::from8p((s8)op.si10 - 0x80)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::HLGTI(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->cmp(*addr, op.si10);
+
+	asmjit::Label next(*c);
+	c->jna(next);
+	c->mov(*pos, m_pos | 0x1000000);
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::MPYI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pmaddwd(va, XmmConst(v128::from32p(op.si10 & 0xffff)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::MPYUI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	const XmmLink& va2 = XmmAlloc();
+	c->movdqa(va2, va);
+	c->movdqa(vi, XmmConst(v128::from32p(op.si10 & 0xffff)));
+	c->pmulhuw(va, vi);
+	c->pmullw(va2, vi);
+	c->pslld(va, 16);
+	c->por(va, va2);
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CEQI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpeqd(va, XmmConst(v128::from32p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CEQHI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpeqw(va, XmmConst(v128::from16p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::CEQBI(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	c->pcmpeqb(va, XmmConst(v128::from8p(op.si10)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), va);
+}
+
+void spu_recompiler::HEQI(spu_opcode_t op)
+{
+	c->mov(*addr, SPU_OFF_32(gpr[op.ra]._u32[3]));
+	c->cmp(*addr, op.si10);
+
+	asmjit::Label next(*c);
+	c->jne(next);
+	c->mov(*pos, m_pos | 0x1000000);
+	c->ret(*pos);
+	c->bind(next);
+}
+
+void spu_recompiler::HBRA(spu_opcode_t op)
+{
+}
+
+void spu_recompiler::HBRR(spu_opcode_t op)
+{
+}
+
+void spu_recompiler::ILA(spu_opcode_t op)
+{
+	const XmmLink& vr = XmmAlloc();
+	c->movdqa(vr, XmmConst(v128::from32p(op.i18 & 0x3ffff)));
+	c->movdqa(SPU_OFF_128(gpr[op.rt]), vr);
+}
+
+void spu_recompiler::SELB(spu_opcode_t op)
+{
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& vc = XmmGet(op.rt, XmmType::Int);
+	c->pand(vb, vc);
+	c->pandn(vc, SPU_OFF_128(gpr[op.ra]));
+	c->por(vb, vc);
+	c->movdqa(SPU_OFF_128(gpr[op.rc]), vb);
+}
+
+void spu_recompiler::SHUFB(spu_opcode_t op)
+{
+	const XmmLink& v0 = XmmGet(op.rt, XmmType::Int); // v0 = mask
+	const XmmLink& v1 = XmmAlloc();
+	const XmmLink& v2 = XmmAlloc();
+	const XmmLink& v3 = XmmAlloc();
+	const XmmLink& v4 = XmmAlloc();
+	const XmmLink& vFF = XmmAlloc();
+	c->movdqa(v2, v0); // v2 = mask
+	// generate specific values:
+	c->movdqa(v1, XmmConst(v128::from8p(0xe0))); // v1 = 11100000
+	c->movdqa(v3, XmmConst(v128::from8p(0x80))); // v3 = 10000000
+	c->pand(v2, v1); // filter mask      v2 = mask & 11100000
+	c->movdqa(vFF, v2); // and copy      vFF = mask & 11100000
+	c->movdqa(v4, XmmConst(v128::from8p(0xc0))); // v4 = 11000000
+	c->pcmpeqb(vFF, v4); // gen 0xff     vFF = (mask & 11100000 == 11000000) ? 0xff : 0
+	c->movdqa(v4, v2); // copy again     v4 = mask & 11100000
+	c->pand(v4, v3); // filter mask      v4 = mask & 10000000
+	c->pcmpeqb(v2, v1); //               v2 = (mask & 11100000 == 11100000) ? 0xff : 0
+	c->pcmpeqb(v4, v3); //               v4 = (mask & 10000000 == 10000000) ? 0xff : 0
+	c->pand(v2, v3); // generate 0x80    v2 = (mask & 11100000 == 11100000) ? 0x80 : 0
+	c->por(vFF, v2); // merge 0xff, 0x80 vFF = (mask & 11100000 == 11000000) ? 0xff : (mask & 11100000 == 11100000) ? 0x80 : 0
+	c->pandn(v1, v0); // filter mask     v1 = mask & 00011111
+	// select bytes from [op.rb]:
+	c->movdqa(v2, XmmConst(v128::from8p(0x0f))); //   v2 = 00001111
+	c->pxor(v1, XmmConst(v128::from8p(0x10))); //   v1 = (mask & 00011111) ^ 00010000
+	c->psubb(v2, v1); //                 v2 = 00001111 - ((mask & 00011111) ^ 00010000)
+	c->movdqa(v1, SPU_OFF_128(gpr[op.rb])); //        v1 = op.rb
+	c->pshufb(v1, v2); //                v1 = select(op.rb, 00001111 - ((mask & 00011111) ^ 00010000))
+	// select bytes from [op.ra]:
+	c->pxor(v2, XmmConst(v128::from8p(0xf0))); //   v2 = (00001111 - ((mask & 00011111) ^ 00010000)) ^ 11110000
+	c->movdqa(v3, SPU_OFF_128(gpr[op.ra])); //        v3 = op.ra
+	c->pshufb(v3, v2); //                v3 = select(op.ra, (00001111 - ((mask & 00011111) ^ 00010000)) ^ 11110000)
+	c->por(v1, v3); //                   v1 = select(op.rb, 00001111 - ((mask & 00011111) ^ 00010000)) | (v3)
+	c->pandn(v4, v1); // filter result   v4 = v1 & ((mask & 10000000 == 10000000) ? 0 : 0xff)
+	c->por(vFF, v4); // final merge      vFF = (mask & 10000000 == 10000000) ? ((mask & 11100000 == 11000000) ? 0xff : (mask & 11100000 == 11100000) ? 0x80 : 0) : (v1)
+	c->movdqa(SPU_OFF_128(gpr[op.rc]), vFF);
+}
+
+void spu_recompiler::MPYA(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Int);
+	const XmmLink& vb = XmmGet(op.rb, XmmType::Int);
+	const XmmLink& vi = XmmAlloc();
+	c->movdqa(vi, XmmConst(v128::from32p(0xffff)));
+	c->pand(va, vi);
+	c->pand(vb, vi);
+	c->pmaddwd(va, vb);
+	c->paddd(va, SPU_OFF_128(gpr[op.rt]));
+	c->movdqa(SPU_OFF_128(gpr[op.rc]), va);
+}
+
+void spu_recompiler::FNMS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	const XmmLink& vc = XmmGet(op.rt, XmmType::Float);
+	c->mulps(va, SPU_OFF_128(gpr[op.rb]));
+	c->subps(vc, va);
+	c->movaps(SPU_OFF_128(gpr[op.rc]), vc);
+}
+
+void spu_recompiler::FMA(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->mulps(va, SPU_OFF_128(gpr[op.rb]));
+	c->addps(va, SPU_OFF_128(gpr[op.rt]));
+	c->movaps(SPU_OFF_128(gpr[op.rc]), va);
+}
+
+void spu_recompiler::FMS(spu_opcode_t op)
+{
+	const XmmLink& va = XmmGet(op.ra, XmmType::Float);
+	c->mulps(va, SPU_OFF_128(gpr[op.rb]));
+	c->subps(va, SPU_OFF_128(gpr[op.rt]));
+	c->movaps(SPU_OFF_128(gpr[op.rc]), va);
+}
+
+void spu_recompiler::UNK(spu_opcode_t op)
+{
+	throw EXCEPTION("Unknown/Illegal opcode (0x%08x)", op.opcode);
+}
+
+const spu_opcode_table_t<void(spu_recompiler::*)(spu_opcode_t)> spu_recompiler::opcodes{ DEFINE_SPU_OPCODES(&spu_recompiler::), &spu_recompiler::UNK };
diff --git a/rpcs3/Emu/Cell/SPUASMJITRecompiler.h b/rpcs3/Emu/Cell/SPUASMJITRecompiler.h
new file mode 100644
index 0000000000..a1ba609b8c
--- /dev/null
+++ b/rpcs3/Emu/Cell/SPUASMJITRecompiler.h
@@ -0,0 +1,309 @@
+#pragma once
+
+#include "SPURecompiler.h"
+
+namespace asmjit
+{
+	struct JitRuntime;
+	struct X86Compiler;
+	struct X86GpVar;
+	struct X86XmmVar;
+	struct X86Mem;
+	struct Label;
+}
+
+// SPU ASMJIT Recompiler
+class spu_recompiler : public SPURecompilerBase
+{
+	const std::shared_ptr<asmjit::JitRuntime> m_jit;
+
+public:
+	spu_recompiler();
+
+	virtual void compile(spu_function_t& f) override;
+
+private:
+	// emitter:
+	asmjit::X86Compiler* c;
+
+	// input:
+	asmjit::X86GpVar* cpu;
+	asmjit::X86GpVar* ls;
+
+	// output:
+	asmjit::X86GpVar* pos;
+
+	// temporary:
+	asmjit::X86GpVar* addr;
+	asmjit::X86GpVar* qw0;
+	asmjit::X86GpVar* qw1;
+	asmjit::X86GpVar* qw2;
+	std::array<asmjit::X86XmmVar*, 10> vec;
+
+	// labels:
+	asmjit::Label* labels; // array[0x10000]
+	asmjit::Label* jt; // jump table resolver
+
+	class XmmLink
+	{
+		friend class spu_recompiler;
+
+		asmjit::X86XmmVar*& m_alloc;
+		asmjit::X86XmmVar* xmm_var;
+
+		XmmLink(asmjit::X86XmmVar*& xmm_var)
+			: m_alloc(xmm_var)
+			, xmm_var(xmm_var)
+		{
+			m_alloc = nullptr;
+		}
+
+	public:
+		XmmLink() = delete;
+
+		XmmLink(const XmmLink&) = delete;
+
+		XmmLink(XmmLink&& right)
+			: m_alloc(right.m_alloc)
+			, xmm_var(right.xmm_var)
+		{
+			right.xmm_var = nullptr;
+		}
+
+		XmmLink& operator =(const XmmLink&) = delete;
+
+		XmmLink& operator =(XmmLink&& right) = delete;
+
+		~XmmLink()
+		{
+			if (xmm_var) m_alloc = xmm_var;
+		}
+
+		inline operator const asmjit::X86XmmVar&() const
+		{
+			return *xmm_var;
+		}
+	};
+
+	enum class XmmType
+	{
+		Int,
+		Float,
+		Double,
+	};
+
+	XmmLink XmmAlloc();
+	XmmLink XmmGet(s8 reg, XmmType type);
+
+	asmjit::X86Mem XmmConst(v128 data);
+	asmjit::X86Mem XmmConst(__m128 data);
+	asmjit::X86Mem XmmConst(__m128i data);
+
+private:
+	void InterpreterCall(spu_opcode_t op);
+	void FunctionCall();
+
+	void STOP(spu_opcode_t op);
+	void LNOP(spu_opcode_t op);
+	void SYNC(spu_opcode_t op);
+	void DSYNC(spu_opcode_t op);
+	void MFSPR(spu_opcode_t op);
+	void RDCH(spu_opcode_t op);
+	void RCHCNT(spu_opcode_t op);
+	void SF(spu_opcode_t op);
+	void OR(spu_opcode_t op);
+	void BG(spu_opcode_t op);
+	void SFH(spu_opcode_t op);
+	void NOR(spu_opcode_t op);
+	void ABSDB(spu_opcode_t op);
+	void ROT(spu_opcode_t op);
+	void ROTM(spu_opcode_t op);
+	void ROTMA(spu_opcode_t op);
+	void SHL(spu_opcode_t op);
+	void ROTH(spu_opcode_t op);
+	void ROTHM(spu_opcode_t op);
+	void ROTMAH(spu_opcode_t op);
+	void SHLH(spu_opcode_t op);
+	void ROTI(spu_opcode_t op);
+	void ROTMI(spu_opcode_t op);
+	void ROTMAI(spu_opcode_t op);
+	void SHLI(spu_opcode_t op);
+	void ROTHI(spu_opcode_t op);
+	void ROTHMI(spu_opcode_t op);
+	void ROTMAHI(spu_opcode_t op);
+	void SHLHI(spu_opcode_t op);
+	void A(spu_opcode_t op);
+	void AND(spu_opcode_t op);
+	void CG(spu_opcode_t op);
+	void AH(spu_opcode_t op);
+	void NAND(spu_opcode_t op);
+	void AVGB(spu_opcode_t op);
+	void MTSPR(spu_opcode_t op);
+	void WRCH(spu_opcode_t op);
+	void BIZ(spu_opcode_t op);
+	void BINZ(spu_opcode_t op);
+	void BIHZ(spu_opcode_t op);
+	void BIHNZ(spu_opcode_t op);
+	void STOPD(spu_opcode_t op);
+	void STQX(spu_opcode_t op);
+	void BI(spu_opcode_t op);
+	void BISL(spu_opcode_t op);
+	void IRET(spu_opcode_t op);
+	void BISLED(spu_opcode_t op);
+	void HBR(spu_opcode_t op);
+	void GB(spu_opcode_t op);
+	void GBH(spu_opcode_t op);
+	void GBB(spu_opcode_t op);
+	void FSM(spu_opcode_t op);
+	void FSMH(spu_opcode_t op);
+	void FSMB(spu_opcode_t op);
+	void FREST(spu_opcode_t op);
+	void FRSQEST(spu_opcode_t op);
+	void LQX(spu_opcode_t op);
+	void ROTQBYBI(spu_opcode_t op);
+	void ROTQMBYBI(spu_opcode_t op);
+	void SHLQBYBI(spu_opcode_t op);
+	void CBX(spu_opcode_t op);
+	void CHX(spu_opcode_t op);
+	void CWX(spu_opcode_t op);
+	void CDX(spu_opcode_t op);
+	void ROTQBI(spu_opcode_t op);
+	void ROTQMBI(spu_opcode_t op);
+	void SHLQBI(spu_opcode_t op);
+	void ROTQBY(spu_opcode_t op);
+	void ROTQMBY(spu_opcode_t op);
+	void SHLQBY(spu_opcode_t op);
+	void ORX(spu_opcode_t op);
+	void CBD(spu_opcode_t op);
+	void CHD(spu_opcode_t op);
+	void CWD(spu_opcode_t op);
+	void CDD(spu_opcode_t op);
+	void ROTQBII(spu_opcode_t op);
+	void ROTQMBII(spu_opcode_t op);
+	void SHLQBII(spu_opcode_t op);
+	void ROTQBYI(spu_opcode_t op);
+	void ROTQMBYI(spu_opcode_t op);
+	void SHLQBYI(spu_opcode_t op);
+	void NOP(spu_opcode_t op);
+	void CGT(spu_opcode_t op);
+	void XOR(spu_opcode_t op);
+	void CGTH(spu_opcode_t op);
+	void EQV(spu_opcode_t op);
+	void CGTB(spu_opcode_t op);
+	void SUMB(spu_opcode_t op);
+	void HGT(spu_opcode_t op);
+	void CLZ(spu_opcode_t op);
+	void XSWD(spu_opcode_t op);
+	void XSHW(spu_opcode_t op);
+	void CNTB(spu_opcode_t op);
+	void XSBH(spu_opcode_t op);
+	void CLGT(spu_opcode_t op);
+	void ANDC(spu_opcode_t op);
+	void FCGT(spu_opcode_t op);
+	void DFCGT(spu_opcode_t op);
+	void FA(spu_opcode_t op);
+	void FS(spu_opcode_t op);
+	void FM(spu_opcode_t op);
+	void CLGTH(spu_opcode_t op);
+	void ORC(spu_opcode_t op);
+	void FCMGT(spu_opcode_t op);
+	void DFCMGT(spu_opcode_t op);
+	void DFA(spu_opcode_t op);
+	void DFS(spu_opcode_t op);
+	void DFM(spu_opcode_t op);
+	void CLGTB(spu_opcode_t op);
+	void HLGT(spu_opcode_t op);
+	void DFMA(spu_opcode_t op);
+	void DFMS(spu_opcode_t op);
+	void DFNMS(spu_opcode_t op);
+	void DFNMA(spu_opcode_t op);
+	void CEQ(spu_opcode_t op);
+	void MPYHHU(spu_opcode_t op);
+	void ADDX(spu_opcode_t op);
+	void SFX(spu_opcode_t op);
+	void CGX(spu_opcode_t op);
+	void BGX(spu_opcode_t op);
+	void MPYHHA(spu_opcode_t op);
+	void MPYHHAU(spu_opcode_t op);
+	void FSCRRD(spu_opcode_t op);
+	void FESD(spu_opcode_t op);
+	void FRDS(spu_opcode_t op);
+	void FSCRWR(spu_opcode_t op);
+	void DFTSV(spu_opcode_t op);
+	void FCEQ(spu_opcode_t op);
+	void DFCEQ(spu_opcode_t op);
+	void MPY(spu_opcode_t op);
+	void MPYH(spu_opcode_t op);
+	void MPYHH(spu_opcode_t op);
+	void MPYS(spu_opcode_t op);
+	void CEQH(spu_opcode_t op);
+	void FCMEQ(spu_opcode_t op);
+	void DFCMEQ(spu_opcode_t op);
+	void MPYU(spu_opcode_t op);
+	void CEQB(spu_opcode_t op);
+	void FI(spu_opcode_t op);
+	void HEQ(spu_opcode_t op);
+	void CFLTS(spu_opcode_t op);
+	void CFLTU(spu_opcode_t op);
+	void CSFLT(spu_opcode_t op);
+	void CUFLT(spu_opcode_t op);
+	void BRZ(spu_opcode_t op);
+	void STQA(spu_opcode_t op);
+	void BRNZ(spu_opcode_t op);
+	void BRHZ(spu_opcode_t op);
+	void BRHNZ(spu_opcode_t op);
+	void STQR(spu_opcode_t op);
+	void BRA(spu_opcode_t op);
+	void LQA(spu_opcode_t op);
+	void BRASL(spu_opcode_t op);
+	void BR(spu_opcode_t op);
+	void FSMBI(spu_opcode_t op);
+	void BRSL(spu_opcode_t op);
+	void LQR(spu_opcode_t op);
+	void IL(spu_opcode_t op);
+	void ILHU(spu_opcode_t op);
+	void ILH(spu_opcode_t op);
+	void IOHL(spu_opcode_t op);
+	void ORI(spu_opcode_t op);
+	void ORHI(spu_opcode_t op);
+	void ORBI(spu_opcode_t op);
+	void SFI(spu_opcode_t op);
+	void SFHI(spu_opcode_t op);
+	void ANDI(spu_opcode_t op);
+	void ANDHI(spu_opcode_t op);
+	void ANDBI(spu_opcode_t op);
+	void AI(spu_opcode_t op);
+	void AHI(spu_opcode_t op);
+	void STQD(spu_opcode_t op);
+	void LQD(spu_opcode_t op);
+	void XORI(spu_opcode_t op);
+	void XORHI(spu_opcode_t op);
+	void XORBI(spu_opcode_t op);
+	void CGTI(spu_opcode_t op);
+	void CGTHI(spu_opcode_t op);
+	void CGTBI(spu_opcode_t op);
+	void HGTI(spu_opcode_t op);
+	void CLGTI(spu_opcode_t op);
+	void CLGTHI(spu_opcode_t op);
+	void CLGTBI(spu_opcode_t op);
+	void HLGTI(spu_opcode_t op);
+	void MPYI(spu_opcode_t op);
+	void MPYUI(spu_opcode_t op);
+	void CEQI(spu_opcode_t op);
+	void CEQHI(spu_opcode_t op);
+	void CEQBI(spu_opcode_t op);
+	void HEQI(spu_opcode_t op);
+	void HBRA(spu_opcode_t op);
+	void HBRR(spu_opcode_t op);
+	void ILA(spu_opcode_t op);
+	void SELB(spu_opcode_t op);
+	void SHUFB(spu_opcode_t op);
+	void MPYA(spu_opcode_t op);
+	void FNMS(spu_opcode_t op);
+	void FMA(spu_opcode_t op);
+	void FMS(spu_opcode_t op);
+
+	void UNK(spu_opcode_t op);
+
+	static const spu_opcode_table_t<void(spu_recompiler::*)(spu_opcode_t)> opcodes;
+};
diff --git a/rpcs3/Emu/Cell/SPUAnalyser.cpp b/rpcs3/Emu/Cell/SPUAnalyser.cpp
new file mode 100644
index 0000000000..329a80a41c
--- /dev/null
+++ b/rpcs3/Emu/Cell/SPUAnalyser.cpp
@@ -0,0 +1,267 @@
+#include "stdafx.h"
+#include "Utilities/Log.h"
+
+#include "Crypto/sha1.h"
+#include "SPURecompiler.h"
+#include "SPUAnalyser.h"
+
+const spu_opcode_table_t<spu_itype_t> g_spu_itype{ DEFINE_SPU_OPCODES(spu_itype::), spu_itype::UNK };
+
+SPUDatabase::SPUDatabase()
+{
+	// TODO: load existing database associated with currently running executable
+
+	LOG_SUCCESS(SPU, "SPU Database initialized...");
+}
+
+SPUDatabase::~SPUDatabase()
+{
+	// TODO: serialize database
+}
+
+std::shared_ptr<spu_function_t> SPUDatabase::analyse(const be_t<u32>* ls, u32 entry, u32 max_limit)
+{
+	std::lock_guard<std::mutex> lock(m_mutex);
+
+	// Check arguments (bounds and alignment)
+	if (max_limit > 0x40000 || entry >= max_limit || entry % 4 || max_limit % 4)
+	{
+		throw EXCEPTION("Invalid arguments (entry=0x%05x, limit=0x%05x)", entry, max_limit);
+	}
+
+	// Key for multimap
+	const u64 key = entry | u64{ ls[entry / 4] } << 32;
+
+	// Try to find existing function in the database
+	for (auto found = m_db.find(key); found != m_db.end(); found++)
+	{
+		// Compare binary data explicitly (TODO: optimize)
+		if (std::equal(found->second->data.begin(), found->second->data.end(), ls + entry / 4))
+		{
+			return found->second;
+		}
+	}
+
+	// Initialize block entries with the function entry point
+	std::set<u32> blocks{ entry };
+
+	// Entries of adjacent functions; jump table entries
+	std::set<u32> adjacent, jt;
+
+	// Set initial limit which will be narrowed later
+	u32 limit = max_limit;
+
+	// Find preliminary set of possible block entries (first pass), `start` is the current block address
+	for (u32 start = entry, pos = entry; pos < limit; pos += 4)
+	{
+		const spu_opcode_t op{ ls[pos / 4] };
+
+		const spu_itype_t type = g_spu_itype[op.opcode];
+
+		using namespace spu_itype;
+
+		if (start == pos) // Additional analysis at the beginning of the block (questionable)
+		{
+			// Possible jump table
+			std::vector<u32> jt_abs, jt_rel;
+
+			for (; pos < limit; pos += 4)
+			{
+				const u32 target = ls[pos / 4];
+
+				if (target % 4)
+				{
+					// Misaligned address: abort analysis
+					break;
+				}
+
+				if (target >= entry && target < limit)
+				{
+					// Possible jump table entry (absolute)
+					jt_abs.emplace_back(target);
+				}
+
+				if (target + start >= entry && target + start < limit)
+				{
+					// Possible jump table entry (relative)
+					jt_rel.emplace_back(target + start);
+				}
+
+				if (std::max(jt_abs.size(), jt_rel.size()) * 4 + start <= pos)
+				{
+					break;
+				}
+			}
+
+			if (pos - start >= 8)
+			{
+				// Register jump table block (at least 2 entries) as an ordinary block
+				blocks.emplace(start);
+
+				// Register jump table entries (absolute)
+				if (jt_abs.size() * 4 == pos - start)
+				{
+					blocks.insert(jt_abs.begin(), jt_abs.end());
+
+					jt.insert(jt_abs.begin(), jt_abs.end());
+				}
+
+				// Register jump table entries (relative)
+				if (jt_rel.size() * 4 == pos - start)
+				{
+					blocks.insert(jt_rel.begin(), jt_rel.end());
+
+					jt.insert(jt_rel.begin(), jt_rel.end());
+				}
+
+				// Fix pos value
+				start = pos; pos = pos - 4;
+				
+				continue;
+			}
+
+			// Restore pos value
+			pos = start;
+		}
+
+		if (!type || (start == pos && start > *blocks.rbegin())) // Invalid instruction or "unrelated" block started
+		{
+			// Discard current block and abort the operation
+			limit = start;
+
+			break;
+		}
+		else if (op.opcode == 0) // Hack: special case (STOP 0)
+		{
+			limit = pos + 4;
+
+			break;
+		}
+		else if (type == BI) // Branch Indirect
+		{
+			blocks.emplace(start); start = pos + 4;
+		}
+		else if (type == BR || type == BRA) // Branch Relative/Absolute
+		{
+			const u32 target = spu_branch_target(type == BR ? pos : 0, op.i16);
+
+			// Add adjacent function because it always could be
+			adjacent.emplace(target);
+
+			if (target > entry)
+			{
+				blocks.emplace(target);
+			}
+
+			blocks.emplace(start); start = pos + 4;
+		}
+		else if (type == BRSL || type == BRASL) // Branch Relative/Absolute and Set Link
+		{
+			const u32 target = spu_branch_target(type == BRSL ? pos : 0, op.i16);
+
+			if (target == pos + 4)
+			{
+				// Branch to the next instruction and set link ("get next instruction address" idiom)
+
+				if (op.rt == 0) LOG_ERROR(SPU, "Suspicious instruction at [0x%05x]", pos);
+			}
+			else
+			{
+				// Add adjacent function
+				adjacent.emplace(target);
+
+				if (target > entry)
+				{
+					limit = std::min<u32>(limit, target);
+				}
+			}
+		}
+		else if (type == BISL) // Branch Indirect and Set Link
+		{
+			// Nothing
+		}
+		else if (type == BRNZ || type == BRZ || type == BRHNZ || type == BRHZ) // Branch Relative if (Not) Zero Word/Halfword
+		{
+			const u32 target = spu_branch_target(pos, op.i16);
+
+			// Add adjacent function because it always could be
+			adjacent.emplace(target);
+
+			if (target > entry)
+			{
+				blocks.emplace(target);
+			}
+		}
+	}
+
+	// Find more function calls (second pass, questionable)
+	for (u32 pos = 0; pos < 0x40000; pos += 4)
+	{
+		const spu_opcode_t op{ ls[pos / 4] };
+
+		const spu_itype_t type = g_spu_itype[op.opcode];
+
+		using namespace spu_itype;
+
+		if (!type) // Invalid instruction
+		{
+			break;
+		}
+		else if (type == BRSL || type == BRASL) // Branch Relative/Absolute and Set Link
+		{
+			const u32 target = spu_branch_target(type == BRSL ? pos : 0, op.i16);
+
+			if (target != pos + 4 && target > entry && limit > target)
+			{
+				// Narrow the limit
+				limit = target;
+			}
+		}
+	}
+
+	if (limit <= entry)
+	{
+		LOG_ERROR(SPU, "Function not found [0x%05x]", entry);
+		return nullptr;
+	}
+
+	// Prepare new function (set addr and size)
+	auto func = std::make_shared<spu_function_t>(entry, limit - entry);
+
+	// Fill function block info
+	for (auto i = blocks.crbegin(); i != blocks.crend(); i++)
+	{
+		if (limit > *i)
+		{
+			func->blocks.emplace_hint(func->blocks.begin(), *i);
+		}
+	}
+
+	// Fill adjacent function info
+	for (auto i = adjacent.crbegin(); i != adjacent.crend(); i++)
+	{
+		if (limit <= *i || entry >= *i)
+		{
+			func->adjacent.emplace_hint(func->adjacent.begin(), *i);
+		}
+	}
+
+	// Fill jump table entries
+	for (auto i = jt.crbegin(); i != jt.crend(); i++)
+	{
+		if (limit > *i)
+		{
+			func->jtable.emplace_hint(func->jtable.begin(), *i);
+		}
+	}
+
+	// Copy function contents
+	func->data = { ls + entry / 4, ls + limit / 4 };
+
+	// Add function to the database
+	m_db.emplace(key, func);
+
+	LOG_SUCCESS(SPU, "Function detected [0x%05x-0x%05x] (size=0x%x)", func->addr, func->addr + func->size, func->size);
+
+	return func;
+}
diff --git a/rpcs3/Emu/Cell/SPUAnalyser.h b/rpcs3/Emu/Cell/SPUAnalyser.h
new file mode 100644
index 0000000000..3d3995ae05
--- /dev/null
+++ b/rpcs3/Emu/Cell/SPUAnalyser.h
@@ -0,0 +1,269 @@
+#pragma once
+
+#include "Emu/Cell/SPUOpcodes.h"
+
+class SPUThread;
+
+// Type of the runtime functions generated by SPU recompiler
+using spu_jit_func_t = u32(*)(SPUThread* _spu, be_t<u32>* _ls);
+
+// SPU instruction classification namespace
+namespace spu_itype
+{
+	enum spu_itype_t : u32
+	{
+		UNK = 0,
+
+		STOP,
+		LNOP,
+		SYNC,
+		DSYNC,
+		MFSPR,
+		RDCH,
+		RCHCNT,
+		SF,
+		OR,
+		BG,
+		SFH,
+		NOR,
+		ABSDB,
+		ROT,
+		ROTM,
+		ROTMA,
+		SHL,
+		ROTH,
+		ROTHM,
+		ROTMAH,
+		SHLH,
+		ROTI,
+		ROTMI,
+		ROTMAI,
+		SHLI,
+		ROTHI,
+		ROTHMI,
+		ROTMAHI,
+		SHLHI,
+		A,
+		AND,
+		CG,
+		AH,
+		NAND,
+		AVGB,
+		MTSPR,
+		WRCH,
+		BIZ,
+		BINZ,
+		BIHZ,
+		BIHNZ,
+		STOPD,
+		STQX,
+		BI,
+		BISL,
+		IRET,
+		BISLED,
+		HBR,
+		GB,
+		GBH,
+		GBB,
+		FSM,
+		FSMH,
+		FSMB,
+		FREST,
+		FRSQEST,
+		LQX,
+		ROTQBYBI,
+		ROTQMBYBI,
+		SHLQBYBI,
+		CBX,
+		CHX,
+		CWX,
+		CDX,
+		ROTQBI,
+		ROTQMBI,
+		SHLQBI,
+		ROTQBY,
+		ROTQMBY,
+		SHLQBY,
+		ORX,
+		CBD,
+		CHD,
+		CWD,
+		CDD,
+		ROTQBII,
+		ROTQMBII,
+		SHLQBII,
+		ROTQBYI,
+		ROTQMBYI,
+		SHLQBYI,
+		NOP,
+		CGT,
+		XOR,
+		CGTH,
+		EQV,
+		CGTB,
+		SUMB,
+		HGT,
+		CLZ,
+		XSWD,
+		XSHW,
+		CNTB,
+		XSBH,
+		CLGT,
+		ANDC,
+		FCGT,
+		DFCGT,
+		FA,
+		FS,
+		FM,
+		CLGTH,
+		ORC,
+		FCMGT,
+		DFCMGT,
+		DFA,
+		DFS,
+		DFM,
+		CLGTB,
+		HLGT,
+		DFMA,
+		DFMS,
+		DFNMS,
+		DFNMA,
+		CEQ,
+		MPYHHU,
+		ADDX,
+		SFX,
+		CGX,
+		BGX,
+		MPYHHA,
+		MPYHHAU,
+		FSCRRD,
+		FESD,
+		FRDS,
+		FSCRWR,
+		DFTSV,
+		FCEQ,
+		DFCEQ,
+		MPY,
+		MPYH,
+		MPYHH,
+		MPYS,
+		CEQH,
+		FCMEQ,
+		DFCMEQ,
+		MPYU,
+		CEQB,
+		FI,
+		HEQ,
+		CFLTS,
+		CFLTU,
+		CSFLT,
+		CUFLT,
+		BRZ,
+		STQA,
+		BRNZ,
+		BRHZ,
+		BRHNZ,
+		STQR,
+		BRA,
+		LQA,
+		BRASL,
+		BR,
+		FSMBI,
+		BRSL,
+		LQR,
+		IL,
+		ILHU,
+		ILH,
+		IOHL,
+		ORI,
+		ORHI,
+		ORBI,
+		SFI,
+		SFHI,
+		ANDI,
+		ANDHI,
+		ANDBI,
+		AI,
+		AHI,
+		STQD,
+		LQD,
+		XORI,
+		XORHI,
+		XORBI,
+		CGTI,
+		CGTHI,
+		CGTBI,
+		HGTI,
+		CLGTI,
+		CLGTHI,
+		CLGTBI,
+		HLGTI,
+		MPYI,
+		MPYUI,
+		CEQI,
+		CEQHI,
+		CEQBI,
+		HEQI,
+		HBRA,
+		HBRR,
+		ILA,
+		SELB,
+		SHUFB,
+		MPYA,
+		FNMS,
+		FMA,
+		FMS,
+	};
+}
+
+using spu_itype::spu_itype_t;
+
+// SPU Instruction Classification table
+extern const spu_opcode_table_t<spu_itype_t> g_spu_itype;
+
+// SPU basic function information structure
+struct spu_function_t
+{
+	// entry point (LS address)
+	const u32 addr;
+
+	// function size (in bytes)
+	const u32 size;
+
+	// function contents (binary copy)
+	std::vector<be_t<u32>> data;
+
+	// basic blocks (start addresses)
+	std::set<u32> blocks;
+
+	// functions possibly called by this function (may not be available)
+	std::set<u32> adjacent;
+
+	// jump table values (start addresses)
+	std::set<u32> jtable;
+
+	// pointer to the compiled function
+	spu_jit_func_t compiled = nullptr;
+
+	spu_function_t(u32 addr, u32 size)
+		: addr(addr)
+		, size(size)
+	{
+	}
+};
+
+// SPU Function Database (must be global or PS3 process-local)
+class SPUDatabase final
+{
+	std::mutex m_mutex;
+
+	// All registered functions (uses addr and first instruction as a key)
+	std::unordered_multimap<u64, std::shared_ptr<spu_function_t>> m_db;
+
+public:
+	SPUDatabase();
+	~SPUDatabase();
+
+	// Try to retrieve SPU function information
+	std::shared_ptr<spu_function_t> analyse(const be_t<u32>* ls, u32 entry, u32 limit = 0x40000);
+};
diff --git a/rpcs3/Emu/Cell/SPUContext.h b/rpcs3/Emu/Cell/SPUContext.h
index 2fa42dd9da..9c408ffdd2 100644
--- a/rpcs3/Emu/Cell/SPUContext.h
+++ b/rpcs3/Emu/Cell/SPUContext.h
@@ -1,6 +1,5 @@
 #pragma once
 
-struct SPUContext
+struct spu_context_t
 {
-	v128 gpr[128];
 };
diff --git a/rpcs3/Emu/Cell/SPUDecoder.h b/rpcs3/Emu/Cell/SPUDecoder.h
deleted file mode 100644
index ec2dc3daa2..0000000000
--- a/rpcs3/Emu/Cell/SPUDecoder.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#pragma once
-
-#include "Emu/Cell/SPUOpcodes.h"
-#include "Emu/Cell/PPCDecoder.h"
-#include "Emu/Cell/SPUInstrTable.h"
-
-class SPUDecoder : public PPCDecoder
-{
-	SPUOpcodes* m_op;
-	
-public:
-	SPUDecoder(SPUOpcodes& op) : m_op(&op)
-	{
-	}
-
-	~SPUDecoder()
-	{
-		delete m_op;
-	}
-
-	virtual void Decode(const u32 code)
-	{
-		(*SPU_instr::rrr_list)(m_op, code);
-	}
-};
diff --git a/rpcs3/Emu/Cell/SPUDisAsm.h b/rpcs3/Emu/Cell/SPUDisAsm.h
index c40f4a56f3..d65eb1f369 100644
--- a/rpcs3/Emu/Cell/SPUDisAsm.h
+++ b/rpcs3/Emu/Cell/SPUDisAsm.h
@@ -1,7 +1,7 @@
 #pragma once
 
-#include "Emu/Cell/SPUOpcodes.h"
-#include "Emu/Cell/PPCDisAsm.h"
+#include "PPCDisAsm.h"
+#include "SPUOpcodes.h"
 
 static const char* spu_reg_name[128] =
 {
@@ -66,9 +66,7 @@ static const char* spu_ch_name[128] =
 	"$ch121", "$ch122", "$ch123", "$ch124", "$ch125", "$ch126", "$ch127",
 };
 
-class SPUDisAsm 
-	: public SPUOpcodes
-	, public PPCDisAsm
+class SPUDisAsm : public PPCDisAsm
 {
 public:
 	SPUDisAsm(CPUDisAsmMode mode) : PPCDisAsm(mode)
@@ -80,9 +78,9 @@ public:
 	}
 
 private:
-	virtual u32 DisAsmBranchTarget(const s32 imm)
+	virtual u32 DisAsmBranchTarget(const s32 imm) override
 	{
-		return branchTarget(dump_pc, imm);
+		return spu_branch_target(dump_pc, imm);
 	}
 
 private:
@@ -136,815 +134,823 @@ private:
 		Write(fmt::format("%s %s,%s,%s,%s", FixOp(op).c_str(), a1, a2, a3, a4));
 	}
 	//0 - 10
-	void STOP(u32 code)
+	void STOP(spu_opcode_t op)
 	{
-		DisAsm("stop", code);
+		DisAsm("stop", op.opcode & 0x1fffff);
 	}
-	void LNOP()
+	void LNOP(spu_opcode_t op)
 	{
 		DisAsm("lnop");
 	}
-	void SYNC(u32 Cbit)
+	void SYNC(spu_opcode_t op)
 	{
-		DisAsm("sync", Cbit);
+		DisAsm(op.c ? "syncc" : "sync");
 	}
-	void DSYNC()
+	void DSYNC(spu_opcode_t op)
 	{
 		DisAsm("dsync");
 	}
-	void MFSPR(u32 rt, u32 sa)
+	void MFSPR(spu_opcode_t op)
 	{
-		DisAsm("mfspr", spu_reg_name[rt], spu_spreg_name[sa]);
+		DisAsm("mfspr", spu_reg_name[op.rt], spu_spreg_name[op.ra]);
 	}
-	void RDCH(u32 rt, u32 ra)
+	void RDCH(spu_opcode_t op)
 	{
-		DisAsm("rdch", spu_reg_name[rt], spu_ch_name[ra]);
+		DisAsm("rdch", spu_reg_name[op.rt], spu_ch_name[op.ra]);
 	}
-	void RCHCNT(u32 rt, u32 ra)
+	void RCHCNT(spu_opcode_t op)
 	{
-		DisAsm("rchcnt", spu_reg_name[rt], spu_ch_name[ra]);
+		DisAsm("rchcnt", spu_reg_name[op.rt], spu_ch_name[op.ra]);
 	}
-	void SF(u32 rt, u32 ra, u32 rb)
+	void SF(spu_opcode_t op)
 	{
-		DisAsm("sf", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("sf", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void OR(u32 rt, u32 ra, u32 rb)
+	void OR(spu_opcode_t op)
 	{
-		DisAsm("or", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("or", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void BG(u32 rt, u32 ra, u32 rb)
+	void BG(spu_opcode_t op)
 	{
-		DisAsm("bg", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("bg", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SFH(u32 rt, u32 ra, u32 rb)
+	void SFH(spu_opcode_t op)
 	{
-		DisAsm("sfh", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("sfh", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void NOR(u32 rt, u32 ra, u32 rb)
+	void NOR(spu_opcode_t op)
 	{
-		DisAsm("nor", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("nor", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ABSDB(u32 rt, u32 ra, u32 rb)
+	void ABSDB(spu_opcode_t op)
 	{
-		DisAsm("absdb", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("absdb", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROT(u32 rt, u32 ra, u32 rb)
+	void ROT(spu_opcode_t op)
 	{
-		DisAsm("rot", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rot", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTM(u32 rt, u32 ra, u32 rb)
+	void ROTM(spu_opcode_t op)
 	{
-		DisAsm("rotm", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotm", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTMA(u32 rt, u32 ra, u32 rb)
+	void ROTMA(spu_opcode_t op)
 	{
-		DisAsm("rotma", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotma", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SHL(u32 rt, u32 ra, u32 rb)
+	void SHL(spu_opcode_t op)
 	{
-		DisAsm("shl", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("shl", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTH(u32 rt, u32 ra, u32 rb)
+	void ROTH(spu_opcode_t op)
 	{
-		DisAsm("roth", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("roth", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTHM(u32 rt, u32 ra, u32 rb)
+	void ROTHM(spu_opcode_t op)
 	{
-		DisAsm("rothm", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rothm", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTMAH(u32 rt, u32 ra, u32 rb)
+	void ROTMAH(spu_opcode_t op)
 	{
-		DisAsm("rotmah", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotmah", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SHLH(u32 rt, u32 ra, u32 rb)
+	void SHLH(spu_opcode_t op)
 	{
-		DisAsm("shlh", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("shlh", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTI(u32 rt, u32 ra, s32 i7)
+	void ROTI(spu_opcode_t op)
 	{
-		DisAsm("roti", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("roti", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTMI(u32 rt, u32 ra, s32 i7)
+	void ROTMI(spu_opcode_t op)
 	{
-		DisAsm("rotmi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotmi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTMAI(u32 rt, u32 ra, s32 i7)
+	void ROTMAI(spu_opcode_t op)
 	{
-		DisAsm("rotmai", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotmai", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void SHLI(u32 rt, u32 ra, s32 i7)
+	void SHLI(spu_opcode_t op)
 	{
-		DisAsm("shli", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("shli", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTHI(u32 rt, u32 ra, s32 i7)
+	void ROTHI(spu_opcode_t op)
 	{
-		DisAsm("rothi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rothi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTHMI(u32 rt, u32 ra, s32 i7)
+	void ROTHMI(spu_opcode_t op)
 	{
-		DisAsm("rothmi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rothmi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTMAHI(u32 rt, u32 ra, s32 i7)
+	void ROTMAHI(spu_opcode_t op)
 	{
-		DisAsm("rotmahi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotmahi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void SHLHI(u32 rt, u32 ra, s32 i7)
+	void SHLHI(spu_opcode_t op)
 	{
-		DisAsm("shlhi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("shlhi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void A(u32 rt, u32 ra, u32 rb)
+	void A(spu_opcode_t op)
 	{
-		DisAsm("a", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("a", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void AND(u32 rt, u32 ra, u32 rb)
+	void AND(spu_opcode_t op)
 	{
-		DisAsm("and", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("and", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CG(u32 rt, u32 ra, u32 rb)
+	void CG(spu_opcode_t op)
 	{
-		DisAsm("cg", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cg", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void AH(u32 rt, u32 ra, u32 rb)
+	void AH(spu_opcode_t op)
 	{
-		DisAsm("ah", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("ah", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void NAND(u32 rt, u32 ra, u32 rb)
+	void NAND(spu_opcode_t op)
 	{
-		DisAsm("nand", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("nand", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void AVGB(u32 rt, u32 ra, u32 rb)
+	void AVGB(spu_opcode_t op)
 	{
-		DisAsm("avgb", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("avgb", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MTSPR(u32 rt, u32 sa)
+	void MTSPR(spu_opcode_t op)
 	{
-		DisAsm("mtspr", spu_spreg_name[sa], spu_reg_name[rt]);
+		DisAsm("mtspr", spu_spreg_name[op.ra], spu_reg_name[op.rt]);
 	}
-	void WRCH(u32 ra, u32 rt)
+	void WRCH(spu_opcode_t op)
 	{
-		DisAsm("wrch", spu_ch_name[ra], spu_reg_name[rt]);
+		DisAsm("wrch", spu_ch_name[op.ra], spu_reg_name[op.rt]);
 	}
-	void BIZ(u32 intr, u32 rt, u32 ra)
+	void BIZ(spu_opcode_t op)
 	{
-		DisAsm("biz", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("biz", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void BINZ(u32 intr, u32 rt, u32 ra)
+	void BINZ(spu_opcode_t op)
 	{
-		DisAsm("binz", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("binz", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void BIHZ(u32 intr, u32 rt, u32 ra)
+	void BIHZ(spu_opcode_t op)
 	{
-		DisAsm("bihz", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("bihz", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void BIHNZ(u32 intr, u32 rt, u32 ra)
+	void BIHNZ(spu_opcode_t op)
 	{
-		DisAsm("bihnz", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("bihnz", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void STOPD(u32 rc, u32 ra, u32 rb)
+	void STOPD(spu_opcode_t op)
 	{
-		DisAsm("bihnz", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("bihnz", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void STQX(u32 rt, u32 ra, u32 rb)
+	void STQX(spu_opcode_t op)
 	{
-		DisAsm("stqx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("stqx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void BI(u32 intr, u32 ra)
+	void BI(spu_opcode_t op)
 	{
-		DisAsm("bi", spu_reg_name[ra]);
+		DisAsm("bi", spu_reg_name[op.ra]);
 	}
-	void BISL(u32 intr, u32 rt, u32 ra)
+	void BISL(spu_opcode_t op)
 	{
-		DisAsm("bisl", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("bisl", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void IRET(u32 ra)
+	void IRET(spu_opcode_t op)
 	{
-		DisAsm("iret", spu_reg_name[ra]);
+		DisAsm("iret", spu_reg_name[op.ra]);
 	}
-	void BISLED(u32 intr, u32 rt, u32 ra)
+	void BISLED(spu_opcode_t op)
 	{
-		DisAsm("bisled", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("bisled", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void HBR(u32 p, u32 ro, u32 ra)
+	void HBR(spu_opcode_t op)
 	{
-		DisAsm("hbr", DisAsmBranchTarget(ro), spu_reg_name[ra]);
+		DisAsm(op.c ? "hbrp" : "hbr", DisAsmBranchTarget((op.roh << 7) | op.rt), spu_reg_name[op.ra]);
 	}
-	void GB(u32 rt, u32 ra)
+	void GB(spu_opcode_t op)
 	{
-		DisAsm("gb", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("gb", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void GBH(u32 rt, u32 ra)
+	void GBH(spu_opcode_t op)
 	{
-		DisAsm("gbh", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("gbh", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void GBB(u32 rt, u32 ra)
+	void GBB(spu_opcode_t op)
 	{
-		DisAsm("gbb", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("gbb", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FSM(u32 rt, u32 ra)
+	void FSM(spu_opcode_t op)
 	{
-		DisAsm("fsm", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("fsm", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FSMH(u32 rt, u32 ra)
+	void FSMH(spu_opcode_t op)
 	{
-		DisAsm("fsmh", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("fsmh", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FSMB(u32 rt, u32 ra)
+	void FSMB(spu_opcode_t op)
 	{
-		DisAsm("fsmb", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("fsmb", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FREST(u32 rt, u32 ra)
+	void FREST(spu_opcode_t op)
 	{
-		DisAsm("frest", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("frest", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FRSQEST(u32 rt, u32 ra)
+	void FRSQEST(spu_opcode_t op)
 	{
-		DisAsm("frsqest", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("frsqest", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void LQX(u32 rt, u32 ra, u32 rb)
+	void LQX(spu_opcode_t op)
 	{
-		DisAsm("lqx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("lqx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTQBYBI(u32 rt, u32 ra, u32 rb)
+	void ROTQBYBI(spu_opcode_t op)
 	{
-		DisAsm("rotqbybi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotqbybi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTQMBYBI(u32 rt, u32 ra, u32 rb)
+	void ROTQMBYBI(spu_opcode_t op)
 	{
-		DisAsm("rotqmbybi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotqmbybi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SHLQBYBI(u32 rt, u32 ra, u32 rb)
+	void SHLQBYBI(spu_opcode_t op)
 	{
-		DisAsm("shlqbybi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("shlqbybi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CBX(u32 rt, u32 ra, u32 rb)
+	void CBX(spu_opcode_t op)
 	{
-		DisAsm("cbx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cbx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CHX(u32 rt, u32 ra, u32 rb)
+	void CHX(spu_opcode_t op)
 	{
-		DisAsm("chx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("chx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CWX(u32 rt, u32 ra, u32 rb)
+	void CWX(spu_opcode_t op)
 	{
-		DisAsm("cwx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cwx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CDX(u32 rt, u32 ra, u32 rb)
+	void CDX(spu_opcode_t op)
 	{
-		DisAsm("cdx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cdx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTQBI(u32 rt, u32 ra, u32 rb)
+	void ROTQBI(spu_opcode_t op)
 	{
-		DisAsm("rotqbi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotqbi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTQMBI(u32 rt, u32 ra, u32 rb)
+	void ROTQMBI(spu_opcode_t op)
 	{
-		DisAsm("rotqmbi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotqmbi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SHLQBI(u32 rt, u32 ra, u32 rb)
+	void SHLQBI(spu_opcode_t op)
 	{
-		DisAsm("shlqbi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("shlqbi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTQBY(u32 rt, u32 ra, u32 rb)
+	void ROTQBY(spu_opcode_t op)
 	{
-		DisAsm("rotqby", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotqby", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ROTQMBY(u32 rt, u32 ra, u32 rb)
+	void ROTQMBY(spu_opcode_t op)
 	{
-		DisAsm("rotqmby", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("rotqmby", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SHLQBY(u32 rt, u32 ra, u32 rb)
+	void SHLQBY(spu_opcode_t op)
 	{
-		DisAsm("shlqby", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("shlqby", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ORX(u32 rt, u32 ra)
+	void ORX(spu_opcode_t op)
 	{
-		DisAsm("orx", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("orx", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void CBD(u32 rt, u32 ra, s32 i7)
+	void CBD(spu_opcode_t op)
 	{
-		DisAsm("cbd", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("cbd", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void CHD(u32 rt, u32 ra, s32 i7)
+	void CHD(spu_opcode_t op)
 	{
-		DisAsm("chd", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("chd", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void CWD(u32 rt, u32 ra, s32 i7)
+	void CWD(spu_opcode_t op)
 	{
-		DisAsm("cwd", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("cwd", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void CDD(u32 rt, u32 ra, s32 i7)
+	void CDD(spu_opcode_t op)
 	{
-		DisAsm("cdd", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("cdd", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTQBII(u32 rt, u32 ra, s32 i7)
+	void ROTQBII(spu_opcode_t op)
 	{
-		DisAsm("rotqbii", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotqbii", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTQMBII(u32 rt, u32 ra, s32 i7)
+	void ROTQMBII(spu_opcode_t op)
 	{
-		DisAsm("rotqmbii", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotqmbii", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void SHLQBII(u32 rt, u32 ra, s32 i7)
+	void SHLQBII(spu_opcode_t op)
 	{
-		DisAsm("shlqbii", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("shlqbii", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTQBYI(u32 rt, u32 ra, s32 i7)
+	void ROTQBYI(spu_opcode_t op)
 	{
-		DisAsm("rotqbyi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotqbyi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void ROTQMBYI(u32 rt, u32 ra, s32 i7)
+	void ROTQMBYI(spu_opcode_t op)
 	{
-		DisAsm("rotqmbyi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("rotqmbyi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void SHLQBYI(u32 rt, u32 ra, s32 i7)
+	void SHLQBYI(spu_opcode_t op)
 	{
-		DisAsm("shlqbyi", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("shlqbyi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void NOP(u32 rt)
+	void NOP(spu_opcode_t op)
 	{
-		DisAsm("nop", spu_reg_name[rt]);
+		DisAsm("nop", spu_reg_name[op.rt]);
 	}
-	void CGT(u32 rt, u32 ra, u32 rb)
+	void CGT(spu_opcode_t op)
 	{
-		DisAsm("cgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void XOR(u32 rt, u32 ra, u32 rb)
+	void XOR(spu_opcode_t op)
 	{
-		DisAsm("xor", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("xor", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CGTH(u32 rt, u32 ra, u32 rb)
+	void CGTH(spu_opcode_t op)
 	{
-		DisAsm("cgth", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cgth", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void EQV(u32 rt, u32 ra, u32 rb)
+	void EQV(spu_opcode_t op)
 	{
-		DisAsm("eqv", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("eqv", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CGTB(u32 rt, u32 ra, u32 rb)
+	void CGTB(spu_opcode_t op)
 	{
-		DisAsm("cgtb", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cgtb", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SUMB(u32 rt, u32 ra, u32 rb)
+	void SUMB(spu_opcode_t op)
 	{
-		DisAsm("sumb", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("sumb", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void HGT(u32 rt, s32 ra, s32 rb)
+	void HGT(spu_opcode_t op)
 	{
-		DisAsm("hgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("hgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CLZ(u32 rt, u32 ra)
+	void CLZ(spu_opcode_t op)
 	{
-		DisAsm("clz", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("clz", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void XSWD(u32 rt, u32 ra)
+	void XSWD(spu_opcode_t op)
 	{
-		DisAsm("xswd", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("xswd", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void XSHW(u32 rt, u32 ra)
+	void XSHW(spu_opcode_t op)
 	{
-		DisAsm("xshw", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("xshw", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void CNTB(u32 rt, u32 ra)
+	void CNTB(spu_opcode_t op)
 	{
-		DisAsm("cntb", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("cntb", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void XSBH(u32 rt, u32 ra)
+	void XSBH(spu_opcode_t op)
 	{
-		DisAsm("xsbh", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("xsbh", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void CLGT(u32 rt, u32 ra, u32 rb)
+	void CLGT(spu_opcode_t op)
 	{
-		DisAsm("clgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("clgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ANDC(u32 rt, u32 ra, u32 rb)
+	void ANDC(spu_opcode_t op)
 	{
-		DisAsm("andc", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("andc", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FCGT(u32 rt, u32 ra, u32 rb)
+	void FCGT(spu_opcode_t op)
 	{
-		DisAsm("fcgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fcgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFCGT(u32 rt, u32 ra, u32 rb)
+	void DFCGT(spu_opcode_t op)
 	{
-		DisAsm("dfcgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfcgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FA(u32 rt, u32 ra, u32 rb)
+	void FA(spu_opcode_t op)
 	{
-		DisAsm("fa", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fa", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FS(u32 rt, u32 ra, u32 rb)
+	void FS(spu_opcode_t op)
 	{
-		DisAsm("fs", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fs", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FM(u32 rt, u32 ra, u32 rb)
+	void FM(spu_opcode_t op)
 	{
-		DisAsm("fm", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fm", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CLGTH(u32 rt, u32 ra, u32 rb)
+	void CLGTH(spu_opcode_t op)
 	{
-		DisAsm("clgth", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("clgth", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ORC(u32 rt, u32 ra, u32 rb)
+	void ORC(spu_opcode_t op)
 	{
-		DisAsm("orc", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("orc", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FCMGT(u32 rt, u32 ra, u32 rb)
+	void FCMGT(spu_opcode_t op)
 	{
-		DisAsm("fcmgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fcmgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFCMGT(u32 rt, u32 ra, u32 rb)
+	void DFCMGT(spu_opcode_t op)
 	{
-		DisAsm("dfcmgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfcmgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFA(u32 rt, u32 ra, u32 rb)
+	void DFA(spu_opcode_t op)
 	{
-		DisAsm("dfa", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfa", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFS(u32 rt, u32 ra, u32 rb)
+	void DFS(spu_opcode_t op)
 	{
-		DisAsm("dfs", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfs", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFM(u32 rt, u32 ra, u32 rb)
+	void DFM(spu_opcode_t op)
 	{
-		DisAsm("dfm", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfm", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CLGTB(u32 rt, u32 ra, u32 rb)
+	void CLGTB(spu_opcode_t op)
 	{
-		DisAsm("clgtb", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("clgtb", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void HLGT(u32 rt, u32 ra, u32 rb)
+	void HLGT(spu_opcode_t op)
 	{
-		DisAsm("hlgt", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("hlgt", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFMA(u32 rt, u32 ra, u32 rb)
+	void DFMA(spu_opcode_t op)
 	{
-		DisAsm("dfma", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfma", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFMS(u32 rt, u32 ra, u32 rb)
+	void DFMS(spu_opcode_t op)
 	{
-		DisAsm("dfms", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfms", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFNMS(u32 rt, u32 ra, u32 rb)
+	void DFNMS(spu_opcode_t op)
 	{
-		DisAsm("dfnms", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfnms", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFNMA(u32 rt, u32 ra, u32 rb)
+	void DFNMA(spu_opcode_t op)
 	{
-		DisAsm("dfnma", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfnma", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CEQ(u32 rt, u32 ra, u32 rb)
+	void CEQ(spu_opcode_t op)
 	{
-		DisAsm("ceq", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("ceq", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYHHU(u32 rt, u32 ra, u32 rb)
+	void MPYHHU(spu_opcode_t op)
 	{
-		DisAsm("mpyhhu", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpyhhu", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void ADDX(u32 rt, u32 ra, u32 rb)
+	void ADDX(spu_opcode_t op)
 	{
-		DisAsm("addx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("addx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void SFX(u32 rt, u32 ra, u32 rb)
+	void SFX(spu_opcode_t op)
 	{
-		DisAsm("sfx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("sfx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CGX(u32 rt, u32 ra, u32 rb)
+	void CGX(spu_opcode_t op)
 	{
-		DisAsm("cgx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("cgx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void BGX(u32 rt, u32 ra, u32 rb)
+	void BGX(spu_opcode_t op)
 	{
-		DisAsm("bgx", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("bgx", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYHHA(u32 rt, u32 ra, u32 rb)
+	void MPYHHA(spu_opcode_t op)
 	{
-		DisAsm("mpyhha", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpyhha", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYHHAU(u32 rt, u32 ra, u32 rb)
+	void MPYHHAU(spu_opcode_t op)
 	{
-		DisAsm("mpyhhau", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpyhhau", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FSCRRD(u32 rt)
+	void FSCRRD(spu_opcode_t op)
 	{
-		DisAsm("fscrrd", spu_reg_name[rt]);
+		DisAsm("fscrrd", spu_reg_name[op.rt]);
 	}
-	void FESD(u32 rt, u32 ra)
+	void FESD(spu_opcode_t op)
 	{
-		DisAsm("fesd", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("fesd", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FRDS(u32 rt, u32 ra)
+	void FRDS(spu_opcode_t op)
 	{
-		DisAsm("frds", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("frds", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void FSCRWR(u32 rt, u32 ra)
+	void FSCRWR(spu_opcode_t op)
 	{
-		DisAsm("fscrwr", spu_reg_name[rt], spu_reg_name[ra]);
+		DisAsm("fscrwr", spu_reg_name[op.rt], spu_reg_name[op.ra]);
 	}
-	void DFTSV(u32 rt, u32 ra, s32 i7)
+	void DFTSV(spu_opcode_t op)
 	{
-		DisAsm("dftsv", spu_reg_name[rt], spu_reg_name[ra], i7);
+		DisAsm("dftsv", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si7);
 	}
-	void FCEQ(u32 rt, u32 ra, u32 rb)
+	void FCEQ(spu_opcode_t op)
 	{
-		DisAsm("fceq", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fceq", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFCEQ(u32 rt, u32 ra, u32 rb)
+	void DFCEQ(spu_opcode_t op)
 	{
-		DisAsm("dfceq", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfceq", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPY(u32 rt, u32 ra, u32 rb)
+	void MPY(spu_opcode_t op)
 	{
-		DisAsm("mpy", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpy", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYH(u32 rt, u32 ra, u32 rb)
+	void MPYH(spu_opcode_t op)
 	{
-		DisAsm("mpyh", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpyh", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYHH(u32 rt, u32 ra, u32 rb)
+	void MPYHH(spu_opcode_t op)
 	{
-		DisAsm("mpyhh", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpyhh", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYS(u32 rt, u32 ra, u32 rb)
+	void MPYS(spu_opcode_t op)
 	{
-		DisAsm("mpys", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpys", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CEQH(u32 rt, u32 ra, u32 rb)
+	void CEQH(spu_opcode_t op)
 	{
-		DisAsm("ceqh", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("ceqh", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FCMEQ(u32 rt, u32 ra, u32 rb)
+	void FCMEQ(spu_opcode_t op)
 	{
-		DisAsm("fcmeq", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fcmeq", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void DFCMEQ(u32 rt, u32 ra, u32 rb)
+	void DFCMEQ(spu_opcode_t op)
 	{
-		DisAsm("dfcmeq", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("dfcmeq", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void MPYU(u32 rt, u32 ra, u32 rb)
+	void MPYU(spu_opcode_t op)
 	{
-		DisAsm("mpyu", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("mpyu", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void CEQB(u32 rt, u32 ra, u32 rb)
+	void CEQB(spu_opcode_t op)
 	{
-		DisAsm("ceqb", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("ceqb", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void FI(u32 rt, u32 ra, u32 rb)
+	void FI(spu_opcode_t op)
 	{
-		DisAsm("fi", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("fi", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
-	void HEQ(u32 rt, u32 ra, u32 rb)
+	void HEQ(spu_opcode_t op)
 	{
-		DisAsm("heq", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb]);
+		DisAsm("heq", spu_reg_name[op.rt], spu_reg_name[op.ra], spu_reg_name[op.rb]);
 	}
 
 	//0 - 9
-	void CFLTS(u32 rt, u32 ra, s32 i8)
+	void CFLTS(spu_opcode_t op)
 	{
-		DisAsm("cflts", spu_reg_name[rt], spu_reg_name[ra], i8);
+		DisAsm("cflts", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si8);
 	}
-	void CFLTU(u32 rt, u32 ra, s32 i8)
+	void CFLTU(spu_opcode_t op)
 	{
-		DisAsm("cfltu", spu_reg_name[rt], spu_reg_name[ra], i8);
+		DisAsm("cfltu", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si8);
 	}
-	void CSFLT(u32 rt, u32 ra, s32 i8)
+	void CSFLT(spu_opcode_t op)
 	{
-		DisAsm("csflt", spu_reg_name[rt], spu_reg_name[ra], i8);
+		DisAsm("csflt", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si8);
 	}
-	void CUFLT(u32 rt, u32 ra, s32 i8)
+	void CUFLT(spu_opcode_t op)
 	{
-		DisAsm("cuflt", spu_reg_name[rt], spu_reg_name[ra], i8);
+		DisAsm("cuflt", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si8);
 	}
 
 	//0 - 8
-	void BRZ(u32 rt, s32 i16)
+	void BRZ(spu_opcode_t op)
 	{
-		DisAsm("brz", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("brz", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void STQA(u32 rt, s32 i16)
+	void STQA(spu_opcode_t op)
 	{
-		DisAsm("stqa", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("stqa", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void BRNZ(u32 rt, s32 i16)
+	void BRNZ(spu_opcode_t op)
 	{
-		DisAsm("brnz", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("brnz", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void BRHZ(u32 rt, s32 i16)
+	void BRHZ(spu_opcode_t op)
 	{
-		DisAsm("brhz", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("brhz", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void BRHNZ(u32 rt, s32 i16)
+	void BRHNZ(spu_opcode_t op)
 	{
-		DisAsm("brhnz", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("brhnz", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void STQR(u32 rt, s32 i16)
+	void STQR(spu_opcode_t op)
 	{
-		DisAsm("stqr", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("stqr", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void BRA(s32 i16)
+	void BRA(spu_opcode_t op)
 	{
-		DisAsm("bra", DisAsmBranchTarget(i16));
+		DisAsm("bra", DisAsmBranchTarget(op.si16));
 	}
-	void LQA(u32 rt, s32 i16)
+	void LQA(spu_opcode_t op)
 	{
-		DisAsm("lqa", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("lqa", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void BRASL(u32 rt, s32 i16)
+	void BRASL(spu_opcode_t op)
 	{
-		DisAsm("brasl", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("brasl", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void BR(s32 i16)
+	void BR(spu_opcode_t op)
 	{
-		DisAsm("br", DisAsmBranchTarget(i16));
+		DisAsm("br", DisAsmBranchTarget(op.si16));
 	}
-	void FSMBI(u32 rt, s32 i16)
+	void FSMBI(spu_opcode_t op)
 	{
-		DisAsm("fsmbi", spu_reg_name[rt], i16);
+		DisAsm("fsmbi", spu_reg_name[op.rt], op.si16);
 	}
-	void BRSL(u32 rt, s32 i16)
+	void BRSL(spu_opcode_t op)
 	{
-		DisAsm("brsl", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("brsl", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void LQR(u32 rt, s32 i16)
+	void LQR(spu_opcode_t op)
 	{
-		DisAsm("lqr", spu_reg_name[rt], DisAsmBranchTarget(i16));
+		DisAsm("lqr", spu_reg_name[op.rt], DisAsmBranchTarget(op.si16));
 	}
-	void IL(u32 rt, s32 i16)
+	void IL(spu_opcode_t op)
 	{
-		DisAsm("il", spu_reg_name[rt], i16);
+		DisAsm("il", spu_reg_name[op.rt], op.si16);
 	}
-	void ILHU(u32 rt, s32 i16)
+	void ILHU(spu_opcode_t op)
 	{
-		DisAsm("ilhu", spu_reg_name[rt], i16);
+		DisAsm("ilhu", spu_reg_name[op.rt], op.si16);
 	}
-	void ILH(u32 rt, s32 i16)
+	void ILH(spu_opcode_t op)
 	{
-		DisAsm("ilh", spu_reg_name[rt], i16);
+		DisAsm("ilh", spu_reg_name[op.rt], op.si16);
 	}
-	void IOHL(u32 rt, s32 i16)
+	void IOHL(spu_opcode_t op)
 	{
-		DisAsm("iolh", spu_reg_name[rt], i16);
+		DisAsm("iohl", spu_reg_name[op.rt], op.si16);
 	}
 
 	//0 - 7
-	void ORI(u32 rt, u32 ra, s32 i10)
+	void ORI(spu_opcode_t op)
 	{
-		DisAsm("ori", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("ori", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void ORHI(u32 rt, u32 ra, s32 i10)
+	void ORHI(spu_opcode_t op)
 	{
-		DisAsm("orhi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("orhi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void ORBI(u32 rt, u32 ra, s32 i10)
+	void ORBI(spu_opcode_t op)
 	{
-		DisAsm("orbi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("orbi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void SFI(u32 rt, u32 ra, s32 i10)
+	void SFI(spu_opcode_t op)
 	{
-		DisAsm("sfi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("sfi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void SFHI(u32 rt, u32 ra, s32 i10)
+	void SFHI(spu_opcode_t op)
 	{
-		DisAsm("sfhi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("sfhi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void ANDI(u32 rt, u32 ra, s32 i10)
+	void ANDI(spu_opcode_t op)
 	{
-		DisAsm("andi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("andi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void ANDHI(u32 rt, u32 ra, s32 i10)
+	void ANDHI(spu_opcode_t op)
 	{
-		DisAsm("andhi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("andhi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void ANDBI(u32 rt, u32 ra, s32 i10)
+	void ANDBI(spu_opcode_t op)
 	{
-		DisAsm("andbi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("andbi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void AI(u32 rt, u32 ra, s32 i10)
+	void AI(spu_opcode_t op)
 	{
-		DisAsm("ai", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("ai", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void AHI(u32 rt, u32 ra, s32 i10)
+	void AHI(spu_opcode_t op)
 	{
-		DisAsm("ahi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("ahi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void STQD(u32 rt, s32 i10, u32 ra)
+	void STQD(spu_opcode_t op)
 	{
-		DisAsm("stqd", spu_reg_name[rt], i10, spu_reg_name[ra]);
+		DisAsm("stqd", spu_reg_name[op.rt], op.si10 << 4, spu_reg_name[op.ra]);
 	}
-	void LQD(u32 rt, s32 i10, u32 ra)
+	void LQD(spu_opcode_t op)
 	{
-		DisAsm("lqd", spu_reg_name[rt], i10, spu_reg_name[ra]);
+		DisAsm("lqd", spu_reg_name[op.rt], op.si10 << 4, spu_reg_name[op.ra]);
 	}
-	void XORI(u32 rt, u32 ra, s32 i10)
+	void XORI(spu_opcode_t op)
 	{
-		DisAsm("xori", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("xori", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void XORHI(u32 rt, u32 ra, s32 i10)
+	void XORHI(spu_opcode_t op)
 	{
-		DisAsm("xorhi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("xorhi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void XORBI(u32 rt, u32 ra, s32 i10)
+	void XORBI(spu_opcode_t op)
 	{
-		DisAsm("xorbi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("xorbi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CGTI(u32 rt, u32 ra, s32 i10)
+	void CGTI(spu_opcode_t op)
 	{
-		DisAsm("cgti", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("cgti", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CGTHI(u32 rt, u32 ra, s32 i10)
+	void CGTHI(spu_opcode_t op)
 	{
-		DisAsm("cgthi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("cgthi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CGTBI(u32 rt, u32 ra, s32 i10)
+	void CGTBI(spu_opcode_t op)
 	{
-		DisAsm("cgtbi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("cgtbi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void HGTI(u32 rt, u32 ra, s32 i10)
+	void HGTI(spu_opcode_t op)
 	{
-		DisAsm("hgti", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("hgti", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CLGTI(u32 rt, u32 ra, s32 i10)
+	void CLGTI(spu_opcode_t op)
 	{
-		DisAsm("clgti", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("clgti", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CLGTHI(u32 rt, u32 ra, s32 i10)
+	void CLGTHI(spu_opcode_t op)
 	{
-		DisAsm("clgthi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("clgthi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CLGTBI(u32 rt, u32 ra, s32 i10)
+	void CLGTBI(spu_opcode_t op)
 	{
-		DisAsm("clgtbi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("clgtbi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void HLGTI(u32 rt, u32 ra, s32 i10)
+	void HLGTI(spu_opcode_t op)
 	{
-		DisAsm("hlgti", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("hlgti", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void MPYI(u32 rt, u32 ra, s32 i10)
+	void MPYI(spu_opcode_t op)
 	{
-		DisAsm("mpyi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("mpyi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void MPYUI(u32 rt, u32 ra, s32 i10)
+	void MPYUI(spu_opcode_t op)
 	{
-		DisAsm("mpyui", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("mpyui", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CEQI(u32 rt, u32 ra, s32 i10)
+	void CEQI(spu_opcode_t op)
 	{
-		DisAsm("ceqi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("ceqi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CEQHI(u32 rt, u32 ra, s32 i10)
+	void CEQHI(spu_opcode_t op)
 	{
-		DisAsm("ceqhi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("ceqhi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void CEQBI(u32 rt, u32 ra, s32 i10)
+	void CEQBI(spu_opcode_t op)
 	{
-		DisAsm("ceqbi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("ceqbi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
-	void HEQI(u32 rt, u32 ra, s32 i10)
+	void HEQI(spu_opcode_t op)
 	{
-		DisAsm("heqi", spu_reg_name[rt], spu_reg_name[ra], i10);
+		DisAsm("heqi", spu_reg_name[op.rt], spu_reg_name[op.ra], op.si10);
 	}
 
 	//0 - 6
-	void HBRA(s32 ro, s32 i16)
+	void HBRA(spu_opcode_t op)
 	{
-		DisAsm("hbra", DisAsmBranchTarget(ro), DisAsmBranchTarget(i16));
+		DisAsm("hbra", DisAsmBranchTarget((op.r0h << 7) | op.rt), DisAsmBranchTarget(op.si16));
 	}
-	void HBRR(s32 ro, s32 i16)
+	void HBRR(spu_opcode_t op)
 	{
-		DisAsm("hbrr", DisAsmBranchTarget(ro), DisAsmBranchTarget(i16));
+		DisAsm("hbrr", DisAsmBranchTarget((op.r0h << 7) | op.rt), DisAsmBranchTarget(op.si16));
 	}
-	void ILA(u32 rt, u32 i18)
+	void ILA(spu_opcode_t op)
 	{
-		DisAsm("ila", spu_reg_name[rt], i18);
+		DisAsm("ila", spu_reg_name[op.rt], op.i18);
 	}
 
-	//0 - 3
-	void SELB(u32 rc, u32 ra, u32 rb, u32 rt)
+	//0 - 3, rt <> rc
+	void SELB(spu_opcode_t op)
 	{
-		DisAsm("selb", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt]);
+		DisAsm("selb", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rt]);
 	}
-	void SHUFB(u32 rc, u32 ra, u32 rb, u32 rt)
+	void SHUFB(spu_opcode_t op)
 	{
-		DisAsm("shufb", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt]);
+		DisAsm("shufb", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rt]);
 	}
-	void MPYA(u32 rc, u32 ra, u32 rb, u32 rt)
+	void MPYA(spu_opcode_t op)
 	{
-		DisAsm("mpya", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt]);
+		DisAsm("mpya", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rt]);
 	}
-	void FNMS(u32 rc, u32 ra, u32 rb, u32 rt)
+	void FNMS(spu_opcode_t op)
 	{
-		DisAsm("fnms", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt]);
+		DisAsm("fnms", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rt]);
 	}
-	void FMA(u32 rc, u32 ra, u32 rb, u32 rt)
+	void FMA(spu_opcode_t op)
 	{
-		DisAsm("fma", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt]);
+		DisAsm("fma", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rt]);
 	}
-	void FMS(u32 rc, u32 ra, u32 rb, u32 rt)
+	void FMS(spu_opcode_t op)
 	{
-		DisAsm("fms", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt]);
+		DisAsm("fms", spu_reg_name[op.rc], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rt]);
 	}
 
-	void UNK(u32 code, u32 opcode, u32 gcode)
+	void UNK(spu_opcode_t op)
 	{
-		Write(fmt::format("Unknown/Illegal opcode! (0x%08x, 0x%x, 0x%x)", code, opcode, gcode));
+		Write(fmt::format("Unknown/Illegal opcode! (0x%08x)", op.opcode));
+	}
+
+	static const spu_opcode_table_t<void(SPUDisAsm::*)(spu_opcode_t)> opcodes;
+
+public:
+	inline void do_disasm(u32 opcode)
+	{
+		(this->*opcodes[opcode])({ opcode });
 	}
 };
diff --git a/rpcs3/Emu/Cell/SPUInstrTable.h b/rpcs3/Emu/Cell/SPUInstrTable.h
deleted file mode 100644
index 267db8df8d..0000000000
--- a/rpcs3/Emu/Cell/SPUInstrTable.h
+++ /dev/null
@@ -1,259 +0,0 @@
-#pragma once
-#include "PPCDecoder.h"
-#include "SPUOpcodes.h"
-
-namespace SPU_instr
-{
-	static CodeField<4, 10> RC(FIELD_R_GPR);
-	static CodeField<25, 31> RT(FIELD_R_GPR);
-	static CodeField<18, 24> RA(FIELD_R_GPR);
-	static CodeField<11, 17> RB(FIELD_R_GPR);
-
-	static CodeField<11, 17> i7;
-	static CodeField<10, 17> i8;
-	static CodeField<8, 17> i10;
-	static CodeField<9, 24> i16;
-	static CodeField<7, 24> i18;
-
-	static CodeFieldSigned<11, 17> si7;
-	static CodeFieldSigned<10, 17> si8;
-	static CodeFieldSigned<8, 17> si10;
-	static CodeFieldSignedOffset<8, 17, 4> si10s4;
-	static CodeFieldSigned<9, 24> si16;
-	static CodeFieldOffset<9, 24, 2> i16s2;
-	static CodeFieldSigned<7, 24> si18;
-
-	static CodeField<16, 17> ROH;
-	static CodeField<25, 31> ROL;
-	static DoubleCodeField<16, 17, 25, 31, 8> RO;
-
-	static CodeField<0, 3> RRR;
-	static CodeField<0, 6> RI18;
-	static CodeField<0, 7> RI10;
-	static CodeField<0, 8> RI16;
-	static CodeField<0, 9> RI8;
-	static CodeField<0, 10> RI7;
-	static CodeField<0, 10> RR;
-
-	static CodeField<18, 31> L_18_31;
-	static CodeField<11> L_11;
-
-	// static auto rrr_list = new_list<SPUOpcodes>(RRR);
-	static InstrList<1 << CodeField<0, 3>::size, SPUOpcodes> rrr_list_obj(RRR, nullptr);
-	static auto rrr_list = &rrr_list_obj;
-	static auto ri18_list = new_list(rrr_list, RI18);
-	static auto ri10_list = new_list(ri18_list, RI10);
-	static auto ri16_list = new_list(ri10_list, RI16);
-	static auto ri8_list = new_list(ri16_list, RI8);
-	static auto ri7_list = new_list(ri8_list, RI7, instr_bind(&SPUOpcodes::UNK, GetCode, RRR, RI7));
-
-	#define bind_instr(list, name, ...) \
-		static const auto& name = make_instr<SPU_opcodes::name>(list, #name, &SPUOpcodes::name, ##__VA_ARGS__)
-
-	bind_instr(ri7_list, STOP, L_18_31);
-	bind_instr(ri7_list, LNOP);
-	bind_instr(ri7_list, SYNC, L_11);
-	bind_instr(ri7_list, DSYNC);
-	bind_instr(ri7_list, MFSPR, RT, RA);
-	bind_instr(ri7_list, RDCH, RT, RA);
-	bind_instr(ri7_list, RCHCNT, RT, RA);
-	bind_instr(ri7_list, SF, RT, RA, RB);
-	bind_instr(ri7_list, OR, RT, RA, RB);
-	bind_instr(ri7_list, BG, RT, RA, RB);
-	bind_instr(ri7_list, SFH, RT, RA, RB);
-	bind_instr(ri7_list, NOR, RT, RA, RB);
-	bind_instr(ri7_list, ABSDB, RT, RA, RB);
-	bind_instr(ri7_list, ROT, RT, RA, RB);
-	bind_instr(ri7_list, ROTM, RT, RA, RB);
-	bind_instr(ri7_list, ROTMA, RT, RA, RB);
-	bind_instr(ri7_list, SHL, RT, RA, RB);
-	bind_instr(ri7_list, ROTH, RT, RA, RB);
-	bind_instr(ri7_list, ROTHM, RT, RA, RB);
-	bind_instr(ri7_list, ROTMAH, RT, RA, RB);
-	bind_instr(ri7_list, SHLH, RT, RA, RB);
-	bind_instr(ri7_list, ROTI, RT, RA, RB);
-	bind_instr(ri7_list, ROTMI, RT, RA, RB);
-	bind_instr(ri7_list, ROTMAI, RT, RA, RB);
-	bind_instr(ri7_list, SHLI, RT, RA, i7);
-	bind_instr(ri7_list, ROTHI, RT, RA, i7);
-	bind_instr(ri7_list, ROTHMI, RT, RA, i7);
-	bind_instr(ri7_list, ROTMAHI, RT, RA, i7);
-	bind_instr(ri7_list, SHLHI, RT, RA, i7);
-	bind_instr(ri7_list, A, RT, RA, RB);
-	bind_instr(ri7_list, AND, RT, RA, RB);
-	bind_instr(ri7_list, CG, RT, RA, RB);
-	bind_instr(ri7_list, AH, RT, RA, RB);
-	bind_instr(ri7_list, NAND, RT, RA, RB);
-	bind_instr(ri7_list, AVGB, RT, RA, RB);
-	bind_instr(ri7_list, MTSPR, RT, RA);
-	bind_instr(ri7_list, WRCH, RA, RT);
-	bind_instr(ri7_list, BIZ, RB, RT, RA);
-	bind_instr(ri7_list, BINZ, RB, RT, RA);
-	bind_instr(ri7_list, BIHZ, RB, RT, RA);
-	bind_instr(ri7_list, BIHNZ, RB, RT, RA);
-	bind_instr(ri7_list, STOPD, RT, RA, RB);
-	bind_instr(ri7_list, STQX, RT, RA, RB);
-	bind_instr(ri7_list, BI, RB, RA);
-	bind_instr(ri7_list, BISL, RB, RT, RA);
-	bind_instr(ri7_list, IRET, RA);
-	bind_instr(ri7_list, BISLED, RB, RT, RA);
-	bind_instr(ri7_list, HBR, L_11, RO, RA);
-	bind_instr(ri7_list, GB, RT, RA);
-	bind_instr(ri7_list, GBH, RT, RA);
-	bind_instr(ri7_list, GBB, RT, RA);
-	bind_instr(ri7_list, FSM, RT, RA);
-	bind_instr(ri7_list, FSMH, RT, RA);
-	bind_instr(ri7_list, FSMB, RT, RA);
-	bind_instr(ri7_list, FREST, RT, RA);
-	bind_instr(ri7_list, FRSQEST, RT, RA);
-	bind_instr(ri7_list, LQX, RT, RA, RB);
-	bind_instr(ri7_list, ROTQBYBI, RT, RA, RB);
-	bind_instr(ri7_list, ROTQMBYBI, RT, RA, RB);
-	bind_instr(ri7_list, SHLQBYBI, RT, RA, RB);
-	bind_instr(ri7_list, CBX, RT, RA, RB);
-	bind_instr(ri7_list, CHX, RT, RA, RB);
-	bind_instr(ri7_list, CWX, RT, RA, RB);
-	bind_instr(ri7_list, CDX, RT, RA, RB);
-	bind_instr(ri7_list, ROTQBI, RT, RA, RB);
-	bind_instr(ri7_list, ROTQMBI, RT, RA, RB);
-	bind_instr(ri7_list, SHLQBI, RT, RA, RB);
-	bind_instr(ri7_list, ROTQBY, RT, RA, RB);
-	bind_instr(ri7_list, ROTQMBY, RT, RA, RB);
-	bind_instr(ri7_list, SHLQBY, RT, RA, RB);
-	bind_instr(ri7_list, ORX, RT, RA);
-	bind_instr(ri7_list, CBD, RT, RA, si7);
-	bind_instr(ri7_list, CHD, RT, RA, si7);
-	bind_instr(ri7_list, CWD, RT, RA, si7);
-	bind_instr(ri7_list, CDD, RT, RA, si7);
-	bind_instr(ri7_list, ROTQBII, RT, RA, i7);
-	bind_instr(ri7_list, ROTQMBII, RT, RA, i7);
-	bind_instr(ri7_list, SHLQBII, RT, RA, i7);
-	bind_instr(ri7_list, ROTQBYI, RT, RA, i7);
-	bind_instr(ri7_list, ROTQMBYI, RT, RA, i7);
-	bind_instr(ri7_list, SHLQBYI, RT, RA, i7);
-	bind_instr(ri7_list, NOP, RT);
-	bind_instr(ri7_list, CGT, RT, RA, RB);
-	bind_instr(ri7_list, XOR, RT, RA, RB);
-	bind_instr(ri7_list, CGTH, RT, RA, RB);
-	bind_instr(ri7_list, EQV, RT, RA, RB);
-	bind_instr(ri7_list, CGTB, RT, RA, RB);
-	bind_instr(ri7_list, SUMB, RT, RA, RB);
-	bind_instr(ri7_list, HGT, RT, RA, RB);
-	bind_instr(ri7_list, CLZ, RT, RA);
-	bind_instr(ri7_list, XSWD, RT, RA);
-	bind_instr(ri7_list, XSHW, RT, RA);
-	bind_instr(ri7_list, CNTB, RT, RA);
-	bind_instr(ri7_list, XSBH, RT, RA);
-	bind_instr(ri7_list, CLGT, RT, RA, RB);
-	bind_instr(ri7_list, ANDC, RT, RA, RB);
-	bind_instr(ri7_list, FCGT, RT, RA, RB);
-	bind_instr(ri7_list, DFCGT, RT, RA, RB);
-	bind_instr(ri7_list, FA, RT, RA, RB);
-	bind_instr(ri7_list, FS, RT, RA, RB);
-	bind_instr(ri7_list, FM, RT, RA, RB);
-	bind_instr(ri7_list, CLGTH, RT, RA, RB);
-	bind_instr(ri7_list, ORC, RT, RA, RB);
-	bind_instr(ri7_list, FCMGT, RT, RA, RB);
-	bind_instr(ri7_list, DFCMGT, RT, RA, RB);
-	bind_instr(ri7_list, DFA, RT, RA, RB);
-	bind_instr(ri7_list, DFS, RT, RA, RB);
-	bind_instr(ri7_list, DFM, RT, RA, RB);
-	bind_instr(ri7_list, CLGTB, RT, RA, RB);
-	bind_instr(ri7_list, HLGT, RT, RA, RB);
-	bind_instr(ri7_list, DFMA, RT, RA, RB);
-	bind_instr(ri7_list, DFMS, RT, RA, RB);
-	bind_instr(ri7_list, DFNMS, RT, RA, RB);
-	bind_instr(ri7_list, DFNMA, RT, RA, RB);
-	bind_instr(ri7_list, CEQ, RT, RA, RB);
-	bind_instr(ri7_list, MPYHHU, RT, RA, RB);
-	bind_instr(ri7_list, ADDX, RT, RA, RB);
-	bind_instr(ri7_list, SFX, RT, RA, RB);
-	bind_instr(ri7_list, CGX, RT, RA, RB);
-	bind_instr(ri7_list, BGX, RT, RA, RB);
-	bind_instr(ri7_list, MPYHHA, RT, RA, RB);
-	bind_instr(ri7_list, MPYHHAU, RT, RA, RB);
-	bind_instr(ri7_list, FSCRRD, RT);
-	bind_instr(ri7_list, FESD, RT, RA);
-	bind_instr(ri7_list, FRDS, RT, RA);
-	bind_instr(ri7_list, FSCRWR, RT, RA);
-	bind_instr(ri7_list, DFTSV, RT, RA, i7);
-	bind_instr(ri7_list, FCEQ, RT, RA, RB);
-	bind_instr(ri7_list, DFCEQ, RT, RA, RB);
-	bind_instr(ri7_list, MPY, RT, RA, RB);
-	bind_instr(ri7_list, MPYH, RT, RA, RB);
-	bind_instr(ri7_list, MPYHH, RT, RA, RB);
-	bind_instr(ri7_list, MPYS, RT, RA, RB);
-	bind_instr(ri7_list, CEQH, RT, RA, RB);
-	bind_instr(ri7_list, FCMEQ, RT, RA, RB);
-	bind_instr(ri7_list, DFCMEQ, RT, RA, RB);
-	bind_instr(ri7_list, MPYU, RT, RA, RB);
-	bind_instr(ri7_list, CEQB, RT, RA, RB);
-	bind_instr(ri7_list, FI, RT, RA, RB);
-	bind_instr(ri7_list, HEQ, RT, RA, RB);
-
-	bind_instr(ri8_list, CFLTS, RT, RA, i8);
-	bind_instr(ri8_list, CFLTU, RT, RA, i8);
-	bind_instr(ri8_list, CSFLT, RT, RA, i8);
-	bind_instr(ri8_list, CUFLT, RT, RA, i8);
-
-	bind_instr(ri16_list, BRZ, RT, si16);
-	bind_instr(ri16_list, STQA, RT, si16);
-	bind_instr(ri16_list, BRNZ, RT, si16);
-	bind_instr(ri16_list, BRHZ, RT, si16);
-	bind_instr(ri16_list, BRHNZ, RT, si16);
-	bind_instr(ri16_list, STQR, RT, i16);
-	bind_instr(ri16_list, BRA, si16);
-	bind_instr(ri16_list, LQA, RT, si16);
-	bind_instr(ri16_list, BRASL, RT, si16);
-	bind_instr(ri16_list, BR, si16);
-	bind_instr(ri16_list, FSMBI, RT, i16);
-	bind_instr(ri16_list, BRSL, RT, si16);
-	bind_instr(ri16_list, LQR, RT, si16);
-	bind_instr(ri16_list, IL, RT, si16);
-	bind_instr(ri16_list, ILHU, RT, i16);
-	bind_instr(ri16_list, ILH, RT, i16);
-	bind_instr(ri16_list, IOHL, RT, i16);
-
-	bind_instr(ri10_list, ORI, RT, RA, si10);
-	bind_instr(ri10_list, ORHI, RT, RA, si10);
-	bind_instr(ri10_list, ORBI, RT, RA, i10);
-	bind_instr(ri10_list, SFI, RT, RA, si10);
-	bind_instr(ri10_list, SFHI, RT, RA, si10);
-	bind_instr(ri10_list, ANDI, RT, RA, si10);
-	bind_instr(ri10_list, ANDHI, RT, RA, si10);
-	bind_instr(ri10_list, ANDBI, RT, RA, i10);
-	bind_instr(ri10_list, AI, RT, RA, si10);
-	bind_instr(ri10_list, AHI, RT, RA, si10);
-	bind_instr(ri10_list, STQD, RT, si10s4, RA);
-	bind_instr(ri10_list, LQD, RT, si10s4, RA);
-	bind_instr(ri10_list, XORI, RT, RA, si10);
-	bind_instr(ri10_list, XORHI, RT, RA, si10);
-	bind_instr(ri10_list, XORBI, RT, RA, i10);
-	bind_instr(ri10_list, CGTI, RT, RA, si10);
-	bind_instr(ri10_list, CGTHI, RT, RA, si10);
-	bind_instr(ri10_list, CGTBI, RT, RA, i10);
-	bind_instr(ri10_list, HGTI, RT, RA, si10);
-	bind_instr(ri10_list, CLGTI, RT, RA, si10);
-	bind_instr(ri10_list, CLGTHI, RT, RA, si10);
-	bind_instr(ri10_list, CLGTBI, RT, RA, i10);
-	bind_instr(ri10_list, HLGTI, RT, RA, si10);
-	bind_instr(ri10_list, MPYI, RT, RA, si10);
-	bind_instr(ri10_list, MPYUI, RT, RA, si10);
-	bind_instr(ri10_list, CEQI, RT, RA, si10);
-	bind_instr(ri10_list, CEQHI, RT, RA, si10);
-	bind_instr(ri10_list, CEQBI, RT, RA, i10);
-	bind_instr(ri10_list, HEQI, RT, RA, si10);
-
-	bind_instr(ri18_list, HBRA, RO, i16s2);
-	bind_instr(ri18_list, HBRR, RO, si16);
-	bind_instr(ri18_list, ILA, RT, i18);
-
-	bind_instr(rrr_list, SELB, RC, RA, RB, RT);
-	bind_instr(rrr_list, SHUFB, RC, RA, RB, RT);
-	bind_instr(rrr_list, MPYA, RC, RA, RB, RT);
-	bind_instr(rrr_list, FNMS, RC, RA, RB, RT);
-	bind_instr(rrr_list, FMA, RC, RA, RB, RT);
-	bind_instr(rrr_list, FMS, RC, RA, RB, RT);
-
-	#undef bind_instr
-};
\ No newline at end of file
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.cpp b/rpcs3/Emu/Cell/SPUInterpreter.cpp
index 6cebe2def5..d2525c02a1 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.cpp
+++ b/rpcs3/Emu/Cell/SPUInterpreter.cpp
@@ -4,1245 +4,2081 @@
 #include "Emu/System.h"
 
 #include "SPUThread.h"
-#include "SPUInstrTable.h"
 #include "SPUInterpreter.h"
-#include "SPUInterpreter2.h"
 
-#ifdef _MSC_VER
-#include <intrin.h>
-#define rotl32 _rotl
-#define rotl16 _rotl16
-#else
-#include <x86intrin.h>
-#define rotl16(x,r) (((u16)(x) << (r)) | ((u16)(x) >> (16 - (r))))
-#define rotl32(x,r) (((u32)(x) << (r)) | ((u32)(x) >> (32 - (r))))
-#endif
+#include <fenv.h>
 
-
-void spu_interpreter::DEFAULT(SPUThread& CPU, spu_opcode_t op)
+namespace spu_interpreter
 {
-	SPUInterpreter inter(CPU); (*SPU_instr::rrr_list)(&inter, op.opcode);
+	namespace fast
+	{
+		const spu_opcode_table_t<spu_inter_func_t> g_spu_opcode_table{ DEFINE_SPU_OPCODES(+), default_function };
+	}
+
+	namespace precise
+	{
+		const spu_opcode_table_t<spu_inter_func_t> g_spu_opcode_table{ DEFINE_SPU_OPCODES(+), default_function };
+	}
+}
+
+void spu_interpreter::default_function(SPUThread& spu, spu_opcode_t op)
+{
+	throw EXCEPTION("Unknown/Illegal instruction (0x%08x)", op.opcode);
 }
 
 
-void spu_interpreter::set_interrupt_status(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::set_interrupt_status(SPUThread& spu, spu_opcode_t op)
 {
 	if (op.e)
 	{
-		CPU.set_interrupt_status(true);
-
 		if (op.d)
 		{
 			throw EXCEPTION("Undefined behaviour");
 		}
+
+		spu.set_interrupt_status(true);
 	}
 	else if (op.d)
 	{
-		CPU.set_interrupt_status(false);
+		spu.set_interrupt_status(false);
 	}
 }
 
 
-void spu_interpreter::STOP(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::STOP(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.stop_and_signal(op.opcode & 0x3fff);
+	spu.stop_and_signal(op.opcode & 0x3fff);
 }
 
-void spu_interpreter::LNOP(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::LNOP(SPUThread& spu, spu_opcode_t op)
 {
 }
 
-void spu_interpreter::SYNC(SPUThread& CPU, spu_opcode_t op)
+// This instruction must be used following a store instruction that modifies the instruction stream.
+void spu_interpreter::SYNC(SPUThread& spu, spu_opcode_t op)
+{
+	_mm_mfence(); 
+}
+
+// This instruction forces all earlier load, store, and channel instructions to complete before proceeding.
+void spu_interpreter::DSYNC(SPUThread& spu, spu_opcode_t op)
 {
 	_mm_mfence();
 }
 
-void spu_interpreter::DSYNC(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MFSPR(SPUThread& spu, spu_opcode_t op)
 {
-	_mm_mfence();
+	spu.gpr[op.rt].clear(); // All SPRs read as zero. TODO: check it.
 }
 
-void spu_interpreter::MFSPR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::RDCH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].clear();
+	spu.gpr[op.rt] = v128::from32r(spu.get_ch_value(op.ra));
 }
 
-void spu_interpreter::RDCH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::RCHCNT(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::from32r(CPU.get_ch_value(op.ra));
+	spu.gpr[op.rt] = v128::from32r(spu.get_ch_count(op.ra));
 }
 
-void spu_interpreter::RCHCNT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SF(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::from32r(CPU.get_ch_count(op.ra));
+	spu.gpr[op.rt] = v128::sub32(spu.gpr[op.rb], spu.gpr[op.ra]);
 }
 
-void spu_interpreter::SF(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::OR(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::sub32(CPU.GPR[op.rb], CPU.GPR[op.ra]);
+	spu.gpr[op.rt] = spu.gpr[op.ra] | spu.gpr[op.rb];
 }
 
-void spu_interpreter::OR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BG(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.GPR[op.ra] | CPU.GPR[op.rb];
+	spu.gpr[op.rt].vi = _mm_add_epi32(sse_cmpgt_epu32(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi), _mm_set1_epi32(1));
 }
 
-void spu_interpreter::BG(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SFH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_add_epi32(sse_cmpgt_epu32(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi), _mm_set1_epi32(1));
+	spu.gpr[op.rt] = v128::sub16(spu.gpr[op.rb], spu.gpr[op.ra]);
 }
 
-void spu_interpreter::SFH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::NOR(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::sub16(CPU.GPR[op.rb], CPU.GPR[op.ra]);
+	spu.gpr[op.rt] = ~(spu.gpr[op.ra] | spu.gpr[op.rb]);
 }
 
-void spu_interpreter::NOR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ABSDB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = ~(CPU.GPR[op.ra] | CPU.GPR[op.rb]);
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
+	spu.gpr[op.rt] = v128::sub8(v128::maxu8(a, b), v128::minu8(a, b));
 }
 
-void spu_interpreter::ABSDB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROT(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
-	CPU.GPR[op.rt] = v128::sub8(v128::maxu8(a, b), v128::minu8(a, b));
-}
-
-void spu_interpreter::ROT(SPUThread& CPU, spu_opcode_t op)
-{
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 4; i++)
 	{
-		CPU.GPR[op.rt]._u32[i] = rotl32(a._u32[i], b._s32[i]);
+		spu.gpr[op.rt]._u32[i] = (a._u32[i] << b._s32[i]) | (a._u32[i] >> (32 - b._s32[i]));
 	}
 }
 
-void spu_interpreter::ROTM(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTM(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 4; i++)
 	{
 		const u64 value = a._u32[i];
-		CPU.GPR[op.rt]._u32[i] = static_cast<u32>(value >> (0 - b._u32[i]));
+		spu.gpr[op.rt]._u32[i] = static_cast<u32>(value >> (0 - b._u32[i]));
 	}
 }
 
-void spu_interpreter::ROTMA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTMA(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 4; i++)
 	{
 		const s64 value = a._s32[i];
-		CPU.GPR[op.rt]._s32[i] = static_cast<s32>(value >> (0 - b._u32[i]));
+		spu.gpr[op.rt]._s32[i] = static_cast<s32>(value >> (0 - b._u32[i]));
 	}
 }
 
-void spu_interpreter::SHL(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHL(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 4; i++)
 	{
 		const u64 value = a._u32[i];
-		CPU.GPR[op.rt]._u32[i] = static_cast<u32>(value << b._u32[i]);
+		spu.gpr[op.rt]._u32[i] = static_cast<u32>(value << b._u32[i]);
 	}
 }
 
-void spu_interpreter::ROTH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTH(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 8; i++)
 	{
-		CPU.GPR[op.rt]._u16[i] = rotl16(a._u16[i], b._u8[i * 2]);
+		spu.gpr[op.rt]._u16[i] = (a._u16[i] << b._s16[i]) | (a._u16[i] >> (16 - b._s16[i]));
 	}
 }
 
-void spu_interpreter::ROTHM(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTHM(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 8; i++)
 	{
 		const u32 value = a._u16[i];
-		CPU.GPR[op.rt]._u16[i] = static_cast<u16>(value >> (0 - b._u16[i]));
+		spu.gpr[op.rt]._u16[i] = static_cast<u16>(value >> (0 - b._u16[i]));
 	}
 }
 
-void spu_interpreter::ROTMAH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTMAH(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 8; i++)
 	{
 		const s32 value = a._s16[i];
-		CPU.GPR[op.rt]._s16[i] = static_cast<s16>(value >> (0 - b._u16[i]));
+		spu.gpr[op.rt]._s16[i] = static_cast<s16>(value >> (0 - b._u16[i]));
 	}
 }
 
-void spu_interpreter::SHLH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLH(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra];
-	const auto b = CPU.GPR[op.rb];
+	const auto a = spu.gpr[op.ra];
+	const auto b = spu.gpr[op.rb];
 
 	for (u32 i = 0; i < 8; i++)
 	{
 		const u32 value = a._u16[i];
-		CPU.GPR[op.rt]._u16[i] = static_cast<u16>(value << b._u16[i]);
+		spu.gpr[op.rt]._u16[i] = static_cast<u16>(value << b._u16[i]);
 	}
 }
 
-void spu_interpreter::ROTI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTI(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const s32 n = op.si7 & 0x1f;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi32(a, n), _mm_srli_epi32(a, 32 - n));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi32(a, n), _mm_srli_epi32(a, 32 - n));
 }
 
-void spu_interpreter::ROTMI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTMI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srli_epi32(CPU.GPR[op.ra].vi, -op.si7 & 0x3f);
+	spu.gpr[op.rt].vi = _mm_srli_epi32(spu.gpr[op.ra].vi, -op.si7 & 0x3f);
 }
 
-void spu_interpreter::ROTMAI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTMAI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srai_epi32(CPU.GPR[op.ra].vi, -op.si7 & 0x3f);
+	spu.gpr[op.rt].vi = _mm_srai_epi32(spu.gpr[op.ra].vi, -op.si7 & 0x3f);
 }
 
-void spu_interpreter::SHLI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_slli_epi32(CPU.GPR[op.ra].vi, op.si7 & 0x3f);
+	spu.gpr[op.rt].vi = _mm_slli_epi32(spu.gpr[op.ra].vi, op.si7 & 0x3f);
 }
 
-void spu_interpreter::ROTHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTHI(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const s32 n = op.si7 & 0xf;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi16(a, n), _mm_srli_epi16(a, 16 - n));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi16(a, n), _mm_srli_epi16(a, 16 - n));
 }
 
-void spu_interpreter::ROTHMI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTHMI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srli_epi16(CPU.GPR[op.ra].vi, -op.si7 & 0x1f);
+	spu.gpr[op.rt].vi = _mm_srli_epi16(spu.gpr[op.ra].vi, -op.si7 & 0x1f);
 }
 
-void spu_interpreter::ROTMAHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTMAHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srai_epi16(CPU.GPR[op.ra].vi, -op.si7 & 0x1f);
+	spu.gpr[op.rt].vi = _mm_srai_epi16(spu.gpr[op.ra].vi, -op.si7 & 0x1f);
 }
 
-void spu_interpreter::SHLHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_slli_epi16(CPU.GPR[op.ra].vi, op.si7 & 0x1f);
+	spu.gpr[op.rt].vi = _mm_slli_epi16(spu.gpr[op.ra].vi, op.si7 & 0x1f);
 }
 
-void spu_interpreter::A(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::A(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::add32(CPU.GPR[op.ra], CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = v128::add32(spu.gpr[op.ra], spu.gpr[op.rb]);
 }
 
-void spu_interpreter::AND(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::AND(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.GPR[op.ra] & CPU.GPR[op.rb];
+	spu.gpr[op.rt] = spu.gpr[op.ra] & spu.gpr[op.rb];
 }
 
-void spu_interpreter::CG(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CG(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = _mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(0x7fffffff));
-	const auto b = _mm_xor_si128(CPU.GPR[op.rb].vi, _mm_set1_epi32(0x80000000));
-	CPU.GPR[op.rt].vi = _mm_srli_epi32(_mm_cmpgt_epi32(b, a), 31);
+	const auto a = _mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(0x7fffffff));
+	const auto b = _mm_xor_si128(spu.gpr[op.rb].vi, _mm_set1_epi32(0x80000000));
+	spu.gpr[op.rt].vi = _mm_srli_epi32(_mm_cmpgt_epi32(b, a), 31);
 }
 
-void spu_interpreter::AH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::AH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::add16(CPU.GPR[op.ra], CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = v128::add16(spu.gpr[op.ra], spu.gpr[op.rb]);
 }
 
-void spu_interpreter::NAND(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::NAND(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = ~(CPU.GPR[op.ra] & CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = ~(spu.gpr[op.ra] & spu.gpr[op.rb]);
 }
 
-void spu_interpreter::AVGB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::AVGB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_avg_epu8(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_avg_epu8(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::MTSPR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MTSPR(SPUThread& spu, spu_opcode_t op)
 {
+	// SPR writes are ignored. TODO: check it.
 }
 
-void spu_interpreter::WRCH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::WRCH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.set_ch_value(op.ra, CPU.GPR[op.rt]._u32[3]);
+	spu.set_ch_value(op.ra, spu.gpr[op.rt]._u32[3]);
 }
 
-void spu_interpreter::BIZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BIZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u32[3] == 0)
+	if (spu.gpr[op.rt]._u32[3] == 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.GPR[op.ra]._u32[3], 0) - 4;
-		set_interrupt_status(CPU, op);
+		set_interrupt_status(spu, op);
+		spu.pc = spu_branch_target(spu.gpr[op.ra]._u32[3], 0) - 4;
 	}
 }
 
-void spu_interpreter::BINZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BINZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u32[3] != 0)
+	if (spu.gpr[op.rt]._u32[3] != 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.GPR[op.ra]._u32[3], 0) - 4;
-		set_interrupt_status(CPU, op);
+		set_interrupt_status(spu, op);
+		spu.pc = spu_branch_target(spu.gpr[op.ra]._u32[3], 0) - 4;
 	}
 }
 
-void spu_interpreter::BIHZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BIHZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u16[6] == 0)
+	if (spu.gpr[op.rt]._u16[6] == 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.GPR[op.ra]._u32[3], 0) - 4;
-		set_interrupt_status(CPU, op);
+		set_interrupt_status(spu, op);
+		spu.pc = spu_branch_target(spu.gpr[op.ra]._u32[3], 0) - 4;
 	}
 }
 
-void spu_interpreter::BIHNZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BIHNZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u16[6] != 0)
+	if (spu.gpr[op.rt]._u16[6] != 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.GPR[op.ra]._u32[3], 0) - 4;
-		set_interrupt_status(CPU, op);
+		set_interrupt_status(spu, op);
+		spu.pc = spu_branch_target(spu.gpr[op.ra]._u32[3], 0) - 4;
 	}
 }
 
-void spu_interpreter::STOPD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::STOPD(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::STQX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::STQX(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.write128((CPU.GPR[op.ra]._u32[3] + CPU.GPR[op.rb]._u32[3]) & 0x3fff0, CPU.GPR[op.rt]);
+	spu.write128((spu.gpr[op.ra]._u32[3] + spu.gpr[op.rb]._u32[3]) & 0x3fff0, spu.gpr[op.rt]);
 }
 
-void spu_interpreter::BI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.PC = SPUOpcodes::branchTarget(CPU.GPR[op.ra]._u32[3], 0) - 4;
-	set_interrupt_status(CPU, op);
+	set_interrupt_status(spu, op);
+	spu.pc = spu_branch_target(spu.gpr[op.ra]._u32[3], 0) - 4;
 }
 
-void spu_interpreter::BISL(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BISL(SPUThread& spu, spu_opcode_t op)
 {
-	const u32 target = SPUOpcodes::branchTarget(CPU.GPR[op.ra]._u32[3], 0);
-	CPU.GPR[op.rt] = v128::from32r(CPU.PC + 4);
-	CPU.PC = target - 4;
-	set_interrupt_status(CPU, op);
+	set_interrupt_status(spu, op);
+	const u32 target = spu_branch_target(spu.gpr[op.ra]._u32[3], 0);
+	spu.gpr[op.rt] = v128::from32r(spu.pc + 4);
+	spu.pc = target - 4;
 }
 
-void spu_interpreter::IRET(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::IRET(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::BISLED(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BISLED(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::HBR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HBR(SPUThread& spu, spu_opcode_t op)
 {
 }
 
-void spu_interpreter::GB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::GB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::from32r(_mm_movemask_epi8(_mm_slli_epi64(_mm_shuffle_epi8(CPU.GPR[op.ra].vi, _mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 12, 8, 4, 0)), 7)));
+	spu.gpr[op.rt] = v128::from32r(_mm_movemask_epi8(_mm_slli_epi64(_mm_shuffle_epi8(spu.gpr[op.ra].vi, _mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 12, 8, 4, 0)), 7)));
 }
 
-void spu_interpreter::GBH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::GBH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::from32r(_mm_movemask_epi8(_mm_slli_epi64(_mm_shuffle_epi8(CPU.GPR[op.ra].vi, _mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 14, 12, 10, 8, 6, 4, 2, 0)), 7)));
+	spu.gpr[op.rt] = v128::from32r(_mm_movemask_epi8(_mm_slli_epi64(_mm_shuffle_epi8(spu.gpr[op.ra].vi, _mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 14, 12, 10, 8, 6, 4, 2, 0)), 7)));
 }
 
-void spu_interpreter::GBB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::GBB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::from32r(_mm_movemask_epi8(_mm_slli_epi64(CPU.GPR[op.ra].vi, 7)));
+	spu.gpr[op.rt] = v128::from32r(_mm_movemask_epi8(_mm_slli_epi64(spu.gpr[op.ra].vi, 7)));
 }
 
-void spu_interpreter::FSM(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::FSM(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = g_spu_imm.fsm[CPU.GPR[op.ra]._u32[3] & 0xf];
+	spu.gpr[op.rt] = g_spu_imm.fsm[spu.gpr[op.ra]._u32[3] & 0xf];
 }
 
-void spu_interpreter::FSMH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::FSMH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = g_spu_imm.fsmh[CPU.GPR[op.ra]._u32[3] & 0xff];
+	spu.gpr[op.rt] = g_spu_imm.fsmh[spu.gpr[op.ra]._u32[3] & 0xff];
 }
 
-void spu_interpreter::FSMB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::FSMB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = g_spu_imm.fsmb[CPU.GPR[op.ra]._u32[3] & 0xffff];
+	spu.gpr[op.rt] = g_spu_imm.fsmb[spu.gpr[op.ra]._u32[3] & 0xffff];
 }
 
-void spu_interpreter::FREST(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FREST(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vf = _mm_rcp_ps(CPU.GPR[op.ra].vf);
+	spu.gpr[op.rt].vf = _mm_rcp_ps(spu.gpr[op.ra].vf);
 }
 
-void spu_interpreter::FRSQEST(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FRSQEST(SPUThread& spu, spu_opcode_t op)
 {
 	const auto mask = _mm_castsi128_ps(_mm_set1_epi32(0x7fffffff));
-	CPU.GPR[op.rt].vf = _mm_rsqrt_ps(_mm_and_ps(CPU.GPR[op.ra].vf, mask));
+	spu.gpr[op.rt].vf = _mm_rsqrt_ps(_mm_and_ps(spu.gpr[op.ra].vf, mask));
 }
 
-void spu_interpreter::LQX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::LQX(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.read128((CPU.GPR[op.ra]._u32[3] + CPU.GPR[op.rb]._u32[3]) & 0x3fff0);
+	spu.gpr[op.rt] = spu.read128((spu.gpr[op.ra]._u32[3] + spu.gpr[op.rb]._u32[3]) & 0x3fff0);
 }
 
-void spu_interpreter::ROTQBYBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQBYBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.rldq_pshufb[CPU.GPR[op.rb]._u32[3] >> 3 & 0xf].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.rldq_pshufb[spu.gpr[op.rb]._u32[3] >> 3 & 0xf].vi);
 }
 
-void spu_interpreter::ROTQMBYBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQMBYBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.srdq_pshufb[-(CPU.GPR[op.rb]._s32[3] >> 3) & 0x1f].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.srdq_pshufb[-(spu.gpr[op.rb]._s32[3] >> 3) & 0x1f].vi);
 }
 
-void spu_interpreter::SHLQBYBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLQBYBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.sldq_pshufb[CPU.GPR[op.rb]._u32[3] >> 3 & 0x1f].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.sldq_pshufb[spu.gpr[op.rb]._u32[3] >> 3 & 0x1f].vi);
 }
 
-void spu_interpreter::CBX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CBX(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = ~(CPU.GPR[op.rb]._u32[3] + CPU.GPR[op.ra]._u32[3]) & 0xf;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u8[t] = 0x03;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = ~(spu.gpr[op.rb]._u32[3] + spu.gpr[op.ra]._u32[3]) & 0xf;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u8[t] = 0x03;
 }
 
-void spu_interpreter::CHX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CHX(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = (~(CPU.GPR[op.rb]._u32[3] + CPU.GPR[op.ra]._u32[3]) & 0xe) >> 1;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u16[t] = 0x0203;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = (~(spu.gpr[op.rb]._u32[3] + spu.gpr[op.ra]._u32[3]) & 0xe) >> 1;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u16[t] = 0x0203;
 }
 
-void spu_interpreter::CWX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CWX(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = (~(CPU.GPR[op.rb]._u32[3] + CPU.GPR[op.ra]._u32[3]) & 0xc) >> 2;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u32[t] = 0x00010203;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = (~(spu.gpr[op.rb]._u32[3] + spu.gpr[op.ra]._u32[3]) & 0xc) >> 2;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u32[t] = 0x00010203;
 }
 
-void spu_interpreter::CDX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CDX(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = (~(CPU.GPR[op.rb]._u32[3] + CPU.GPR[op.ra]._u32[3]) & 0x8) >> 3;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u64[t] = 0x0001020304050607ull;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = (~(spu.gpr[op.rb]._u32[3] + spu.gpr[op.ra]._u32[3]) & 0x8) >> 3;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u64[t] = 0x0001020304050607ull;
 }
 
-void spu_interpreter::ROTQBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQBI(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
-	const s32 n = CPU.GPR[op.rb]._s32[3] & 0x7;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_alignr_epi8(a, a, 8), 64 - n));
+	const auto a = spu.gpr[op.ra].vi;
+	const s32 n = spu.gpr[op.rb]._s32[3] & 0x7;
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_alignr_epi8(a, a, 8), 64 - n));
 }
 
-void spu_interpreter::ROTQMBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQMBI(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
-	const s32 n = -CPU.GPR[op.rb]._s32[3] & 0x7;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_srli_epi64(a, n), _mm_slli_epi64(_mm_srli_si128(a, 8), 64 - n));
+	const auto a = spu.gpr[op.ra].vi;
+	const s32 n = -spu.gpr[op.rb]._s32[3] & 0x7;
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_srli_epi64(a, n), _mm_slli_epi64(_mm_srli_si128(a, 8), 64 - n));
 }
 
-void spu_interpreter::SHLQBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLQBI(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
-	const s32 n = CPU.GPR[op.rb]._u32[3] & 0x7;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_slli_si128(a, 8), 64 - n));
+	const auto a = spu.gpr[op.ra].vi;
+	const s32 n = spu.gpr[op.rb]._u32[3] & 0x7;
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_slli_si128(a, 8), 64 - n));
 }
 
-void spu_interpreter::ROTQBY(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQBY(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.rldq_pshufb[CPU.GPR[op.rb]._u32[3] & 0xf].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.rldq_pshufb[spu.gpr[op.rb]._u32[3] & 0xf].vi);
 }
 
-void spu_interpreter::ROTQMBY(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQMBY(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.srdq_pshufb[-CPU.GPR[op.rb]._s32[3] & 0x1f].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.srdq_pshufb[-spu.gpr[op.rb]._s32[3] & 0x1f].vi);
 }
 
-void spu_interpreter::SHLQBY(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLQBY(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.sldq_pshufb[CPU.GPR[op.rb]._u32[3] & 0x1f].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.sldq_pshufb[spu.gpr[op.rb]._u32[3] & 0x1f].vi);
 }
 
-void spu_interpreter::ORX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ORX(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::from32r(CPU.GPR[op.ra]._u32[0] | CPU.GPR[op.ra]._u32[1] | CPU.GPR[op.ra]._u32[2] | CPU.GPR[op.ra]._u32[3]);
+	spu.gpr[op.rt] = v128::from32r(spu.gpr[op.ra]._u32[0] | spu.gpr[op.ra]._u32[1] | spu.gpr[op.ra]._u32[2] | spu.gpr[op.ra]._u32[3]);
 }
 
-void spu_interpreter::CBD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CBD(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = ~(op.i7 + CPU.GPR[op.ra]._u32[3]) & 0xf;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u8[t] = 0x03;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = ~(op.i7 + spu.gpr[op.ra]._u32[3]) & 0xf;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u8[t] = 0x03;
 }
 
-void spu_interpreter::CHD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CHD(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = (~(op.i7 + CPU.GPR[op.ra]._u32[3]) & 0xe) >> 1;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u16[t] = 0x0203;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = (~(op.i7 + spu.gpr[op.ra]._u32[3]) & 0xe) >> 1;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u16[t] = 0x0203;
 }
 
-void spu_interpreter::CWD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CWD(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = (~(op.i7 + CPU.GPR[op.ra]._u32[3]) & 0xc) >> 2;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u32[t] = 0x00010203;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = (~(op.i7 + spu.gpr[op.ra]._u32[3]) & 0xc) >> 2;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u32[t] = 0x00010203;
 }
 
-void spu_interpreter::CDD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CDD(SPUThread& spu, spu_opcode_t op)
 {
-	const s32 t = (~(op.i7 + CPU.GPR[op.ra]._u32[3]) & 0x8) >> 3;
-	CPU.GPR[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
-	CPU.GPR[op.rt]._u64[t] = 0x0001020304050607ull;
+	if (op.ra == 1 && (spu.gpr[1]._u32[3] & 0xF))
+	{
+		throw EXCEPTION("Unexpected SP value: LS:0x%05x", spu.gpr[1]._u32[3]);
+	}
+
+	const s32 t = (~(op.i7 + spu.gpr[op.ra]._u32[3]) & 0x8) >> 3;
+	spu.gpr[op.rt] = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
+	spu.gpr[op.rt]._u64[t] = 0x0001020304050607ull;
 }
 
-void spu_interpreter::ROTQBII(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQBII(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const s32 n = op.i7 & 0x7;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_alignr_epi8(a, a, 8), 64 - n));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_alignr_epi8(a, a, 8), 64 - n));
 }
 
-void spu_interpreter::ROTQMBII(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQMBII(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const s32 n = -op.si7 & 0x7;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_srli_epi64(a, n), _mm_slli_epi64(_mm_srli_si128(a, 8), 64 - n));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_srli_epi64(a, n), _mm_slli_epi64(_mm_srli_si128(a, 8), 64 - n));
 }
 
-void spu_interpreter::SHLQBII(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLQBII(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const s32 n = op.i7 & 0x7;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_slli_si128(a, 8), 64 - n));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi64(a, n), _mm_srli_epi64(_mm_slli_si128(a, 8), 64 - n));
 }
 
-void spu_interpreter::ROTQBYI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQBYI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.rldq_pshufb[op.i7 & 0xf].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.rldq_pshufb[op.i7 & 0xf].vi);
 }
 
-void spu_interpreter::ROTQMBYI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ROTQMBYI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.srdq_pshufb[-op.si7 & 0x1f].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.srdq_pshufb[-op.si7 & 0x1f].vi);
 }
 
-void spu_interpreter::SHLQBYI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHLQBYI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, g_spu_imm.sldq_pshufb[op.i7 & 0x1f].vi);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(spu.gpr[op.ra].vi, g_spu_imm.sldq_pshufb[op.i7 & 0x1f].vi);
 }
 
-void spu_interpreter::NOP(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::NOP(SPUThread& spu, spu_opcode_t op)
 {
 }
 
-void spu_interpreter::CGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGT(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi32(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi32(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::XOR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XOR(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.GPR[op.ra] ^ CPU.GPR[op.rb];
+	spu.gpr[op.rt] = spu.gpr[op.ra] ^ spu.gpr[op.rb];
 }
 
-void spu_interpreter::CGTH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGTH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi16(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi16(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::EQV(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::EQV(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = ~(CPU.GPR[op.ra] ^ CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = ~(spu.gpr[op.ra] ^ spu.gpr[op.rb]);
 }
 
-void spu_interpreter::CGTB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGTB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi8(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi8(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::SUMB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SUMB(SPUThread& spu, spu_opcode_t op)
 {
 	const auto ones = _mm_set1_epi8(1);
-	const auto a = _mm_maddubs_epi16(CPU.GPR[op.ra].vi, ones);
-	const auto b = _mm_maddubs_epi16(CPU.GPR[op.rb].vi, ones);
-	CPU.GPR[op.rt].vi = _mm_shuffle_epi8(_mm_hadd_epi16(a, b), _mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0));
+	const auto a = _mm_maddubs_epi16(spu.gpr[op.ra].vi, ones);
+	const auto b = _mm_maddubs_epi16(spu.gpr[op.rb].vi, ones);
+	spu.gpr[op.rt].vi = _mm_shuffle_epi8(_mm_hadd_epi16(a, b), _mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0));
 }
 
-void spu_interpreter::HGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HGT(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.ra]._s32[3] > CPU.GPR[op.rb]._s32[3])
+	if (spu.gpr[op.ra]._s32[3] > spu.gpr[op.rb]._s32[3])
 	{
-		CPU.halt();
+		spu.halt();
 	}
 }
 
-void spu_interpreter::CLZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLZ(SPUThread& spu, spu_opcode_t op)
 {
 	for (u32 i = 0; i < 4; i++)
 	{
-		CPU.GPR[op.rt]._u32[i] = cntlz32(CPU.GPR[op.ra]._u32[i]);
+		spu.gpr[op.rt]._u32[i] = cntlz32(spu.gpr[op.ra]._u32[i]);
 	}
 }
 
-void spu_interpreter::XSWD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XSWD(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt]._s64[0] = CPU.GPR[op.ra]._s32[0];
-	CPU.GPR[op.rt]._s64[1] = CPU.GPR[op.ra]._s32[2];
+	spu.gpr[op.rt]._s64[0] = spu.gpr[op.ra]._s32[0];
+	spu.gpr[op.rt]._s64[1] = spu.gpr[op.ra]._s32[2];
 }
 
-void spu_interpreter::XSHW(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XSHW(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srai_epi32(_mm_slli_epi32(CPU.GPR[op.ra].vi, 16), 16);
+	spu.gpr[op.rt].vi = _mm_srai_epi32(_mm_slli_epi32(spu.gpr[op.ra].vi, 16), 16);
 }
 
-void spu_interpreter::CNTB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CNTB(SPUThread& spu, spu_opcode_t op)
 {
 	const auto counts = _mm_set_epi8(4, 3, 3, 2, 3, 2, 2, 1, 3, 2, 2, 1, 2, 1, 1, 0);
 	const auto mask = _mm_set1_epi8(0xf);
-	const auto a = CPU.GPR[op.ra].vi;
-	CPU.GPR[op.rt].vi = _mm_add_epi8(_mm_shuffle_epi8(counts, _mm_and_si128(a, mask)), _mm_shuffle_epi8(counts, _mm_and_si128(_mm_srli_epi64(a, 4), mask)));
+	const auto a = spu.gpr[op.ra].vi;
+	spu.gpr[op.rt].vi = _mm_add_epi8(_mm_shuffle_epi8(counts, _mm_and_si128(a, mask)), _mm_shuffle_epi8(counts, _mm_and_si128(_mm_srli_epi64(a, 4), mask)));
 }
 
-void spu_interpreter::XSBH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XSBH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srai_epi16(_mm_slli_epi16(CPU.GPR[op.ra].vi, 8), 8);
+	spu.gpr[op.rt].vi = _mm_srai_epi16(_mm_slli_epi16(spu.gpr[op.ra].vi, 8), 8);
 }
 
-void spu_interpreter::CLGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLGT(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = sse_cmpgt_epu32(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = sse_cmpgt_epu32(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::ANDC(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ANDC(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::andnot(CPU.GPR[op.rb], CPU.GPR[op.ra]);
+	spu.gpr[op.rt] = v128::andnot(spu.gpr[op.rb], spu.gpr[op.ra]);
 }
 
-void spu_interpreter::FCGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FCGT(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vf = _mm_cmplt_ps(CPU.GPR[op.rb].vf, CPU.GPR[op.ra].vf);
+	spu.gpr[op.rt].vf = _mm_cmplt_ps(spu.gpr[op.rb].vf, spu.gpr[op.ra].vf);
 }
 
-void spu_interpreter::DFCGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::DFCGT(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::FA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::addfs(CPU.GPR[op.ra], CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = v128::addfs(spu.gpr[op.ra], spu.gpr[op.rb]);
 }
 
-void spu_interpreter::FS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FS(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::subfs(CPU.GPR[op.ra], CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = v128::subfs(spu.gpr[op.ra], spu.gpr[op.rb]);
 }
 
-void spu_interpreter::FM(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FM(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vf = _mm_mul_ps(CPU.GPR[op.ra].vf, CPU.GPR[op.rb].vf);
+	spu.gpr[op.rt].vf = _mm_mul_ps(spu.gpr[op.ra].vf, spu.gpr[op.rb].vf);
 }
 
-void spu_interpreter::CLGTH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLGTH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = sse_cmpgt_epu16(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = sse_cmpgt_epu16(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::ORC(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ORC(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.GPR[op.ra] | ~CPU.GPR[op.rb];
+	spu.gpr[op.rt] = spu.gpr[op.ra] | ~spu.gpr[op.rb];
 }
 
-void spu_interpreter::FCMGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FCMGT(SPUThread& spu, spu_opcode_t op)
 {
 	const auto mask = _mm_castsi128_ps(_mm_set1_epi32(0x7fffffff));
-	CPU.GPR[op.rt].vf = _mm_cmplt_ps(_mm_and_ps(CPU.GPR[op.rb].vf, mask), _mm_and_ps(CPU.GPR[op.ra].vf, mask));
+	spu.gpr[op.rt].vf = _mm_cmplt_ps(_mm_and_ps(spu.gpr[op.rb].vf, mask), _mm_and_ps(spu.gpr[op.ra].vf, mask));
 }
 
-void spu_interpreter::DFCMGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::DFCMGT(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::DFA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::addfd(CPU.GPR[op.ra], CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = v128::addfd(spu.gpr[op.ra], spu.gpr[op.rb]);
 }
 
-void spu_interpreter::DFS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFS(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::subfd(CPU.GPR[op.ra], CPU.GPR[op.rb]);
+	spu.gpr[op.rt] = v128::subfd(spu.gpr[op.ra], spu.gpr[op.rb]);
 }
 
-void spu_interpreter::DFM(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFM(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vd = _mm_mul_pd(CPU.GPR[op.ra].vd, CPU.GPR[op.rb].vd);
+	spu.gpr[op.rt].vd = _mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd);
 }
 
-void spu_interpreter::CLGTB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLGTB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = sse_cmpgt_epu8(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = sse_cmpgt_epu8(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::HLGT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HLGT(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.ra]._u32[3] > CPU.GPR[op.rb]._u32[3])
+	if (spu.gpr[op.ra]._u32[3] > spu.gpr[op.rb]._u32[3])
 	{
-		CPU.halt();
+		spu.halt();
 	}
 }
 
-void spu_interpreter::DFMA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFMA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vd = _mm_add_pd(_mm_mul_pd(CPU.GPR[op.ra].vd, CPU.GPR[op.rb].vd), CPU.GPR[op.rt].vd);
+	spu.gpr[op.rt].vd = _mm_add_pd(_mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd), spu.gpr[op.rt].vd);
 }
 
-void spu_interpreter::DFMS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFMS(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vd = _mm_sub_pd(_mm_mul_pd(CPU.GPR[op.ra].vd, CPU.GPR[op.rb].vd), CPU.GPR[op.rt].vd);
+	spu.gpr[op.rt].vd = _mm_sub_pd(_mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd), spu.gpr[op.rt].vd);
 }
 
-void spu_interpreter::DFNMS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFNMS(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vd = _mm_sub_pd(CPU.GPR[op.rt].vd, _mm_mul_pd(CPU.GPR[op.ra].vd, CPU.GPR[op.rb].vd));
+	spu.gpr[op.rt].vd = _mm_sub_pd(spu.gpr[op.rt].vd, _mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd));
 }
 
-void spu_interpreter::DFNMA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::DFNMA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vd = _mm_sub_pd(_mm_set1_pd(0.0), _mm_add_pd(_mm_mul_pd(CPU.GPR[op.ra].vd, CPU.GPR[op.rb].vd), CPU.GPR[op.rt].vd));
+	spu.gpr[op.rt].vd = _mm_sub_pd(_mm_set1_pd(0.0), _mm_add_pd(_mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd), spu.gpr[op.rt].vd));
 }
 
-void spu_interpreter::CEQ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CEQ(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpeq_epi32(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_cmpeq_epi32(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::MPYHHU(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYHHU(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
-	const auto b = CPU.GPR[op.rb].vi;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_srli_epi32(_mm_mullo_epi16(a, b), 16), _mm_and_si128(_mm_mulhi_epu16(a, b), _mm_set1_epi32(0xffff0000)));
+	const auto a = spu.gpr[op.ra].vi;
+	const auto b = spu.gpr[op.rb].vi;
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_srli_epi32(_mm_mullo_epi16(a, b), 16), _mm_and_si128(_mm_mulhi_epu16(a, b), _mm_set1_epi32(0xffff0000)));
 }
 
-void spu_interpreter::ADDX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ADDX(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::add32(v128::add32(CPU.GPR[op.ra], CPU.GPR[op.rb]), CPU.GPR[op.rt] & v128::from32p(1));
+	spu.gpr[op.rt] = v128::add32(v128::add32(spu.gpr[op.ra], spu.gpr[op.rb]), spu.gpr[op.rt] & v128::from32p(1));
 }
 
-void spu_interpreter::SFX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SFX(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = v128::sub32(v128::sub32(CPU.GPR[op.rb], CPU.GPR[op.ra]), v128::andnot(CPU.GPR[op.rt], v128::from32p(1)));
+	spu.gpr[op.rt] = v128::sub32(v128::sub32(spu.gpr[op.rb], spu.gpr[op.ra]), v128::andnot(spu.gpr[op.rt], v128::from32p(1)));
 }
 
-void spu_interpreter::CGX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGX(SPUThread& spu, spu_opcode_t op)
 {
 	for (s32 i = 0; i < 4; i++)
 	{
-		const u64 carry = CPU.GPR[op.rt]._u32[i] & 1;
-		CPU.GPR[op.rt]._u32[i] = (carry + CPU.GPR[op.ra]._u32[i] + CPU.GPR[op.rb]._u32[i]) >> 32;
+		const u64 carry = spu.gpr[op.rt]._u32[i] & 1;
+		spu.gpr[op.rt]._u32[i] = (carry + spu.gpr[op.ra]._u32[i] + spu.gpr[op.rb]._u32[i]) >> 32;
 	}
 }
 
-void spu_interpreter::BGX(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BGX(SPUThread& spu, spu_opcode_t op)
 {
 	for (s32 i = 0; i < 4; i++)
 	{
-		const s64 result = (u64)CPU.GPR[op.rb]._u32[i] - (u64)CPU.GPR[op.ra]._u32[i] - (u64)(1 - (CPU.GPR[op.rt]._u32[i] & 1));
-		CPU.GPR[op.rt]._u32[i] = result >= 0;
+		const s64 result = (u64)spu.gpr[op.rb]._u32[i] - (u64)spu.gpr[op.ra]._u32[i] - (u64)(1 - (spu.gpr[op.rt]._u32[i] & 1));
+		spu.gpr[op.rt]._u32[i] = result >= 0;
 	}
 }
 
-void spu_interpreter::MPYHHA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYHHA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_add_epi32(CPU.GPR[op.rt].vi, _mm_madd_epi16(_mm_srli_epi32(CPU.GPR[op.ra].vi, 16), _mm_srli_epi32(CPU.GPR[op.rb].vi, 16)));
+	spu.gpr[op.rt].vi = _mm_add_epi32(spu.gpr[op.rt].vi, _mm_madd_epi16(_mm_srli_epi32(spu.gpr[op.ra].vi, 16), _mm_srli_epi32(spu.gpr[op.rb].vi, 16)));
 }
 
-void spu_interpreter::MPYHHAU(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYHHAU(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
-	const auto b = CPU.GPR[op.rb].vi;
-	CPU.GPR[op.rt].vi = _mm_add_epi32(CPU.GPR[op.rt].vi, _mm_or_si128(_mm_srli_epi32(_mm_mullo_epi16(a, b), 16), _mm_and_si128(_mm_mulhi_epu16(a, b), _mm_set1_epi32(0xffff0000))));
+	const auto a = spu.gpr[op.ra].vi;
+	const auto b = spu.gpr[op.rb].vi;
+	spu.gpr[op.rt].vi = _mm_add_epi32(spu.gpr[op.rt].vi, _mm_or_si128(_mm_srli_epi32(_mm_mullo_epi16(a, b), 16), _mm_and_si128(_mm_mulhi_epu16(a, b), _mm_set1_epi32(0xffff0000))));
 }
 
-void spu_interpreter::FSCRRD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FSCRRD(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].clear();
+	spu.gpr[op.rt].clear();
 }
 
-void spu_interpreter::FESD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FESD(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vf;
-	CPU.GPR[op.rt].vd = _mm_cvtps_pd(_mm_shuffle_ps(a, a, 0x8d));
+	const auto a = spu.gpr[op.ra].vf;
+	spu.gpr[op.rt].vd = _mm_cvtps_pd(_mm_shuffle_ps(a, a, 0x8d));
 }
 
-void spu_interpreter::FRDS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FRDS(SPUThread& spu, spu_opcode_t op)
 {
-	const auto t = _mm_cvtpd_ps(CPU.GPR[op.ra].vd);
-	CPU.GPR[op.rt].vf = _mm_shuffle_ps(t, t, 0x72);
+	const auto t = _mm_cvtpd_ps(spu.gpr[op.ra].vd);
+	spu.gpr[op.rt].vf = _mm_shuffle_ps(t, t, 0x72);
 }
 
-void spu_interpreter::FSCRWR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FSCRWR(SPUThread& spu, spu_opcode_t op)
 {
 }
 
-void spu_interpreter::DFTSV(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::DFTSV(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::FCEQ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FCEQ(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vf = _mm_cmpeq_ps(CPU.GPR[op.rb].vf, CPU.GPR[op.ra].vf);
+	spu.gpr[op.rt].vf = _mm_cmpeq_ps(spu.gpr[op.rb].vf, spu.gpr[op.ra].vf);
 }
 
-void spu_interpreter::DFCEQ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::DFCEQ(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::MPY(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPY(SPUThread& spu, spu_opcode_t op)
 {
 	const auto mask = _mm_set1_epi32(0xffff);
-	CPU.GPR[op.rt].vi = _mm_madd_epi16(_mm_and_si128(CPU.GPR[op.ra].vi, mask), _mm_and_si128(CPU.GPR[op.rb].vi, mask));
+	spu.gpr[op.rt].vi = _mm_madd_epi16(_mm_and_si128(spu.gpr[op.ra].vi, mask), _mm_and_si128(spu.gpr[op.rb].vi, mask));
 }
 
-void spu_interpreter::MPYH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_slli_epi32(_mm_mullo_epi16(_mm_srli_epi32(CPU.GPR[op.ra].vi, 16), CPU.GPR[op.rb].vi), 16);
+	spu.gpr[op.rt].vi = _mm_slli_epi32(_mm_mullo_epi16(_mm_srli_epi32(spu.gpr[op.ra].vi, 16), spu.gpr[op.rb].vi), 16);
 }
 
-void spu_interpreter::MPYHH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYHH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_madd_epi16(_mm_srli_epi32(CPU.GPR[op.ra].vi, 16), _mm_srli_epi32(CPU.GPR[op.rb].vi, 16));
+	spu.gpr[op.rt].vi = _mm_madd_epi16(_mm_srli_epi32(spu.gpr[op.ra].vi, 16), _mm_srli_epi32(spu.gpr[op.rb].vi, 16));
 }
 
-void spu_interpreter::MPYS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYS(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_srai_epi32(_mm_slli_epi32(_mm_mulhi_epi16(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi), 16), 16);
+	spu.gpr[op.rt].vi = _mm_srai_epi32(_mm_slli_epi32(_mm_mulhi_epi16(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi), 16), 16);
 }
 
-void spu_interpreter::CEQH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CEQH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpeq_epi16(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_cmpeq_epi16(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::FCMEQ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FCMEQ(SPUThread& spu, spu_opcode_t op)
 {
 	const auto mask = _mm_castsi128_ps(_mm_set1_epi32(0x7fffffff));
-	CPU.GPR[op.rt].vf = _mm_cmpeq_ps(_mm_and_ps(CPU.GPR[op.rb].vf, mask), _mm_and_ps(CPU.GPR[op.ra].vf, mask));
+	spu.gpr[op.rt].vf = _mm_cmpeq_ps(_mm_and_ps(spu.gpr[op.rb].vf, mask), _mm_and_ps(spu.gpr[op.ra].vf, mask));
 }
 
-void spu_interpreter::DFCMEQ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::DFCMEQ(SPUThread& spu, spu_opcode_t op)
 {
 	throw EXCEPTION("Unexpected instruction");
 }
 
-void spu_interpreter::MPYU(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYU(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
-	const auto b = CPU.GPR[op.rb].vi;
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi32(_mm_mulhi_epu16(a, b), 16), _mm_and_si128(_mm_mullo_epi16(a, b), _mm_set1_epi32(0xffff)));
+	const auto a = spu.gpr[op.ra].vi;
+	const auto b = spu.gpr[op.rb].vi;
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi32(_mm_mulhi_epu16(a, b), 16), _mm_and_si128(_mm_mullo_epi16(a, b), _mm_set1_epi32(0xffff)));
 }
 
-void spu_interpreter::CEQB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CEQB(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpeq_epi8(CPU.GPR[op.ra].vi, CPU.GPR[op.rb].vi);
+	spu.gpr[op.rt].vi = _mm_cmpeq_epi8(spu.gpr[op.ra].vi, spu.gpr[op.rb].vi);
 }
 
-void spu_interpreter::FI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FI(SPUThread& spu, spu_opcode_t op)
 {
+	// TODO
 	const auto mask_se = _mm_castsi128_ps(_mm_set1_epi32(0xff800000)); // sign and exponent mask
 	const auto mask_bf = _mm_castsi128_ps(_mm_set1_epi32(0x007ffc00)); // base fraction mask
 	const auto mask_sf = _mm_set1_epi32(0x000003ff); // step fraction mask
 	const auto mask_yf = _mm_set1_epi32(0x0007ffff); // Y fraction mask (bits 13..31)
-	const auto base = _mm_or_ps(_mm_and_ps(CPU.GPR[op.rb].vf, mask_bf), _mm_castsi128_ps(_mm_set1_epi32(0x3f800000)));
-	const auto step = _mm_mul_ps(_mm_cvtepi32_ps(_mm_and_si128(CPU.GPR[op.rb].vi, mask_sf)), _mm_set1_ps(exp2f(-13)));
-	const auto y = _mm_mul_ps(_mm_cvtepi32_ps(_mm_and_si128(CPU.GPR[op.ra].vi, mask_yf)), _mm_set1_ps(exp2f(-19)));
-	CPU.GPR[op.rt].vf = _mm_or_ps(_mm_and_ps(mask_se, CPU.GPR[op.rb].vf), _mm_andnot_ps(mask_se, _mm_sub_ps(base, _mm_mul_ps(step, y))));
+	const auto base = _mm_or_ps(_mm_and_ps(spu.gpr[op.rb].vf, mask_bf), _mm_castsi128_ps(_mm_set1_epi32(0x3f800000)));
+	const auto step = _mm_mul_ps(_mm_cvtepi32_ps(_mm_and_si128(spu.gpr[op.rb].vi, mask_sf)), _mm_set1_ps(exp2f(-13)));
+	const auto y = _mm_mul_ps(_mm_cvtepi32_ps(_mm_and_si128(spu.gpr[op.ra].vi, mask_yf)), _mm_set1_ps(exp2f(-19)));
+	spu.gpr[op.rt].vf = _mm_or_ps(_mm_and_ps(mask_se, spu.gpr[op.rb].vf), _mm_andnot_ps(mask_se, _mm_sub_ps(base, _mm_mul_ps(step, y))));
 }
 
-void spu_interpreter::HEQ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HEQ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.ra]._s32[3] == CPU.GPR[op.rb]._s32[3])
+	if (spu.gpr[op.ra]._s32[3] == spu.gpr[op.rb]._s32[3])
 	{
-		CPU.halt();
+		spu.halt();
 	}
 }
 
 
-void spu_interpreter::CFLTS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::CFLTS(SPUThread& spu, spu_opcode_t op)
 {
-	const auto scaled = _mm_mul_ps(CPU.GPR[op.ra].vf, g_spu_imm.scale[173 - op.i8]);
-	CPU.GPR[op.rt].vi = _mm_xor_si128(_mm_cvttps_epi32(scaled), _mm_castps_si128(_mm_cmpge_ps(scaled, _mm_set1_ps(0x80000000))));
+	const auto scaled = _mm_mul_ps(spu.gpr[op.ra].vf, g_spu_imm.scale[173 - op.i8]);
+	spu.gpr[op.rt].vi = _mm_xor_si128(_mm_cvttps_epi32(scaled), _mm_castps_si128(_mm_cmpge_ps(scaled, _mm_set1_ps(0x80000000))));
 }
 
-void spu_interpreter::CFLTU(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::CFLTU(SPUThread& spu, spu_opcode_t op)
 {
-	const auto scaled1 = _mm_max_ps(_mm_mul_ps(CPU.GPR[op.ra].vf, g_spu_imm.scale[173 - op.i8]), _mm_set1_ps(0.0f));
+	const auto scaled1 = _mm_max_ps(_mm_mul_ps(spu.gpr[op.ra].vf, g_spu_imm.scale[173 - op.i8]), _mm_set1_ps(0.0f));
 	const auto scaled2 = _mm_and_ps(_mm_sub_ps(scaled1, _mm_set1_ps(0x80000000)), _mm_cmpge_ps(scaled1, _mm_set1_ps(0x80000000)));
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_or_si128(_mm_cvttps_epi32(scaled1), _mm_cvttps_epi32(scaled2)), _mm_castps_si128(_mm_cmpge_ps(scaled1, _mm_set1_ps(0x100000000))));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_or_si128(_mm_cvttps_epi32(scaled1), _mm_cvttps_epi32(scaled2)), _mm_castps_si128(_mm_cmpge_ps(scaled1, _mm_set1_ps(0x100000000))));
 }
 
-void spu_interpreter::CSFLT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::CSFLT(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vf = _mm_mul_ps(_mm_cvtepi32_ps(CPU.GPR[op.ra].vi), g_spu_imm.scale[op.i8 - 155]);
+	spu.gpr[op.rt].vf = _mm_mul_ps(_mm_cvtepi32_ps(spu.gpr[op.ra].vi), g_spu_imm.scale[op.i8 - 155]);
 }
 
-void spu_interpreter::CUFLT(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::CUFLT(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const auto fix = _mm_and_ps(_mm_castsi128_ps(_mm_srai_epi32(a, 31)), _mm_set1_ps(0x80000000));
-	CPU.GPR[op.rt].vf = _mm_mul_ps(_mm_add_ps(_mm_cvtepi32_ps(_mm_and_si128(a, _mm_set1_epi32(0x7fffffff))), fix), g_spu_imm.scale[op.i8 - 155]);
+	spu.gpr[op.rt].vf = _mm_mul_ps(_mm_add_ps(_mm_cvtepi32_ps(_mm_and_si128(a, _mm_set1_epi32(0x7fffffff))), fix), g_spu_imm.scale[op.i8 - 155]);
 }
 
 
-void spu_interpreter::BRZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u32[3] == 0)
+	if (spu.gpr[op.rt]._u32[3] == 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.PC, op.i16) - 4;
+		spu.pc = spu_branch_target(spu.pc, op.i16) - 4;
 	}
 }
 
-void spu_interpreter::STQA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::STQA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.write128((op.i16 << 2) & 0x3fff0, CPU.GPR[op.rt]);
+	spu.write128((op.i16 << 2) & 0x3fff0, spu.gpr[op.rt]);
 }
 
-void spu_interpreter::BRNZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRNZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u32[3] != 0)
+	if (spu.gpr[op.rt]._u32[3] != 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.PC, op.i16) - 4;
+		spu.pc = spu_branch_target(spu.pc, op.i16) - 4;
 	}
 }
 
-void spu_interpreter::BRHZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRHZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u16[6] == 0)
+	if (spu.gpr[op.rt]._u16[6] == 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.PC, op.i16) - 4;
+		spu.pc = spu_branch_target(spu.pc, op.i16) - 4;
 	}
 }
 
-void spu_interpreter::BRHNZ(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRHNZ(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.rt]._u16[6] != 0)
+	if (spu.gpr[op.rt]._u16[6] != 0)
 	{
-		CPU.PC = SPUOpcodes::branchTarget(CPU.PC, op.i16) - 4;
+		spu.pc = spu_branch_target(spu.pc, op.i16) - 4;
 	}
 }
 
-void spu_interpreter::STQR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::STQR(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.write128(SPUOpcodes::branchTarget(CPU.PC, op.i16) & 0x3fff0, CPU.GPR[op.rt]);
+	spu.write128(spu_branch_target(spu.pc, op.i16) & 0x3fff0, spu.gpr[op.rt]);
 }
 
-void spu_interpreter::BRA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.PC = SPUOpcodes::branchTarget(0, op.i16) - 4;
+	spu.pc = spu_branch_target(0, op.i16) - 4;
 }
 
-void spu_interpreter::LQA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::LQA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.read128((op.i16 << 2) & 0x3fff0);
+	spu.gpr[op.rt] = spu.read128((op.i16 << 2) & 0x3fff0);
 }
 
-void spu_interpreter::BRASL(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRASL(SPUThread& spu, spu_opcode_t op)
 {
-	const u32 target = SPUOpcodes::branchTarget(0, op.i16);
-	CPU.GPR[op.rt] = v128::from32r(CPU.PC + 4);
-	CPU.PC = target - 4;
+	const u32 target = spu_branch_target(0, op.i16);
+	spu.gpr[op.rt] = v128::from32r(spu.pc + 4);
+	spu.pc = target - 4;
 }
 
-void spu_interpreter::BR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BR(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.PC = SPUOpcodes::branchTarget(CPU.PC, op.i16) - 4;
+	spu.pc = spu_branch_target(spu.pc, op.i16) - 4;
 }
 
-void spu_interpreter::FSMBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::FSMBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = g_spu_imm.fsmb[op.i16];
+	spu.gpr[op.rt] = g_spu_imm.fsmb[op.i16];
 }
 
-void spu_interpreter::BRSL(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::BRSL(SPUThread& spu, spu_opcode_t op)
 {
-	const u32 target = SPUOpcodes::branchTarget(CPU.PC, op.i16);
-	CPU.GPR[op.rt] = v128::from32r(CPU.PC + 4);
-	CPU.PC = target - 4;
+	const u32 target = spu_branch_target(spu.pc, op.i16);
+	spu.gpr[op.rt] = v128::from32r(spu.pc + 4);
+	spu.pc = target - 4;
 }
 
-void spu_interpreter::LQR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::LQR(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.read128(SPUOpcodes::branchTarget(CPU.PC, op.i16) & 0x3fff0);
+	spu.gpr[op.rt] = spu.read128(spu_branch_target(spu.pc, op.i16) & 0x3fff0);
 }
 
-void spu_interpreter::IL(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::IL(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_set1_epi32(op.si16);
+	spu.gpr[op.rt].vi = _mm_set1_epi32(op.si16);
 }
 
-void spu_interpreter::ILHU(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ILHU(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_set1_epi32(op.i16 << 16);
+	spu.gpr[op.rt].vi = _mm_set1_epi32(op.i16 << 16);
 }
 
-void spu_interpreter::ILH(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ILH(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_set1_epi16(op.i16);
+	spu.gpr[op.rt].vi = _mm_set1_epi16(op.i16);
 }
 
-void spu_interpreter::IOHL(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::IOHL(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_or_si128(CPU.GPR[op.rt].vi, _mm_set1_epi32(op.i16));
+	spu.gpr[op.rt].vi = _mm_or_si128(spu.gpr[op.rt].vi, _mm_set1_epi32(op.i16));
 }
 
 
-void spu_interpreter::ORI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ORI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_or_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(op.si10));
+	spu.gpr[op.rt].vi = _mm_or_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(op.si10));
 }
 
-void spu_interpreter::ORHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ORHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_or_si128(CPU.GPR[op.ra].vi, _mm_set1_epi16(op.si10));
+	spu.gpr[op.rt].vi = _mm_or_si128(spu.gpr[op.ra].vi, _mm_set1_epi16(op.si10));
 }
 
-void spu_interpreter::ORBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ORBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_or_si128(CPU.GPR[op.ra].vi, _mm_set1_epi8(op.i8));
+	spu.gpr[op.rt].vi = _mm_or_si128(spu.gpr[op.ra].vi, _mm_set1_epi8(op.i8));
 }
 
-void spu_interpreter::SFI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SFI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_sub_epi32(_mm_set1_epi32(op.si10), CPU.GPR[op.ra].vi);
+	spu.gpr[op.rt].vi = _mm_sub_epi32(_mm_set1_epi32(op.si10), spu.gpr[op.ra].vi);
 }
 
-void spu_interpreter::SFHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SFHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_sub_epi16(_mm_set1_epi16(op.si10), CPU.GPR[op.ra].vi);
+	spu.gpr[op.rt].vi = _mm_sub_epi16(_mm_set1_epi16(op.si10), spu.gpr[op.ra].vi);
 }
 
-void spu_interpreter::ANDI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ANDI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_and_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(op.si10));
+	spu.gpr[op.rt].vi = _mm_and_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(op.si10));
 }
 
-void spu_interpreter::ANDHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ANDHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_and_si128(CPU.GPR[op.ra].vi, _mm_set1_epi16(op.si10));
+	spu.gpr[op.rt].vi = _mm_and_si128(spu.gpr[op.ra].vi, _mm_set1_epi16(op.si10));
 }
 
-void spu_interpreter::ANDBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ANDBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_and_si128(CPU.GPR[op.ra].vi, _mm_set1_epi8(op.i8));
+	spu.gpr[op.rt].vi = _mm_and_si128(spu.gpr[op.ra].vi, _mm_set1_epi8(op.i8));
 }
 
-void spu_interpreter::AI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::AI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_add_epi32(_mm_set1_epi32(op.si10), CPU.GPR[op.ra].vi);
+	spu.gpr[op.rt].vi = _mm_add_epi32(_mm_set1_epi32(op.si10), spu.gpr[op.ra].vi);
 }
 
-void spu_interpreter::AHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::AHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_add_epi16(_mm_set1_epi16(op.si10), CPU.GPR[op.ra].vi);
+	spu.gpr[op.rt].vi = _mm_add_epi16(_mm_set1_epi16(op.si10), spu.gpr[op.ra].vi);
 }
 
-void spu_interpreter::STQD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::STQD(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.write128((CPU.GPR[op.ra]._s32[3] + (op.si10 << 4)) & 0x3fff0, CPU.GPR[op.rt]);
+	spu.write128((spu.gpr[op.ra]._s32[3] + (op.si10 << 4)) & 0x3fff0, spu.gpr[op.rt]);
 }
 
-void spu_interpreter::LQD(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::LQD(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt] = CPU.read128((CPU.GPR[op.ra]._s32[3] + (op.si10 << 4)) & 0x3fff0);
+	spu.gpr[op.rt] = spu.read128((spu.gpr[op.ra]._s32[3] + (op.si10 << 4)) & 0x3fff0);
 }
 
-void spu_interpreter::XORI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XORI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(op.si10));
+	spu.gpr[op.rt].vi = _mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(op.si10));
 }
 
-void spu_interpreter::XORHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XORHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi16(op.si10));
+	spu.gpr[op.rt].vi = _mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi16(op.si10));
 }
 
-void spu_interpreter::XORBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::XORBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi8(op.i8));
+	spu.gpr[op.rt].vi = _mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi8(op.i8));
 }
 
-void spu_interpreter::CGTI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGTI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi32(CPU.GPR[op.ra].vi, _mm_set1_epi32(op.si10));
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi32(spu.gpr[op.ra].vi, _mm_set1_epi32(op.si10));
 }
 
-void spu_interpreter::CGTHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGTHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi16(CPU.GPR[op.ra].vi, _mm_set1_epi16(op.si10));
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi16(spu.gpr[op.ra].vi, _mm_set1_epi16(op.si10));
 }
 
-void spu_interpreter::CGTBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CGTBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi8(CPU.GPR[op.ra].vi, _mm_set1_epi8(op.i8));
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi8(spu.gpr[op.ra].vi, _mm_set1_epi8(op.i8));
 }
 
-void spu_interpreter::HGTI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HGTI(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.ra]._s32[3] > op.si10)
+	if (spu.gpr[op.ra]._s32[3] > op.si10)
 	{
-		CPU.halt();
+		spu.halt();
 	}
 }
 
-void spu_interpreter::CLGTI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLGTI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi32(_mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(0x80000000)), _mm_set1_epi32(op.si10 ^ 0x80000000));
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi32(_mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(0x80000000)), _mm_set1_epi32(op.si10 ^ 0x80000000));
 }
 
-void spu_interpreter::CLGTHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLGTHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi16(_mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(0x80008000)), _mm_set1_epi16(op.si10 ^ 0x8000));
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi16(_mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(0x80008000)), _mm_set1_epi16(op.si10 ^ 0x8000));
 }
 
-void spu_interpreter::CLGTBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CLGTBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpgt_epi8(_mm_xor_si128(CPU.GPR[op.ra].vi, _mm_set1_epi32(0x80808080)), _mm_set1_epi8(op.i8 ^ 0x80));
+	spu.gpr[op.rt].vi = _mm_cmpgt_epi8(_mm_xor_si128(spu.gpr[op.ra].vi, _mm_set1_epi32(0x80808080)), _mm_set1_epi8(op.i8 ^ 0x80));
 }
 
-void spu_interpreter::HLGTI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HLGTI(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.ra]._u32[3] > static_cast<u32>(op.si10))
+	if (spu.gpr[op.ra]._u32[3] > static_cast<u32>(op.si10))
 	{
-		CPU.halt();
+		spu.halt();
 	}
 }
 
-void spu_interpreter::MPYI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_madd_epi16(CPU.GPR[op.ra].vi, _mm_set1_epi32(op.si10 & 0xffff));
+	spu.gpr[op.rt].vi = _mm_madd_epi16(spu.gpr[op.ra].vi, _mm_set1_epi32(op.si10 & 0xffff));
 }
 
-void spu_interpreter::MPYUI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYUI(SPUThread& spu, spu_opcode_t op)
 {
-	const auto a = CPU.GPR[op.ra].vi;
+	const auto a = spu.gpr[op.ra].vi;
 	const auto i = _mm_set1_epi32(op.si10 & 0xffff);
-	CPU.GPR[op.rt].vi = _mm_or_si128(_mm_slli_epi32(_mm_mulhi_epu16(a, i), 16), _mm_mullo_epi16(a, i));
+	spu.gpr[op.rt].vi = _mm_or_si128(_mm_slli_epi32(_mm_mulhi_epu16(a, i), 16), _mm_mullo_epi16(a, i));
 }
 
-void spu_interpreter::CEQI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CEQI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpeq_epi32(CPU.GPR[op.ra].vi, _mm_set1_epi32(op.si10));
+	spu.gpr[op.rt].vi = _mm_cmpeq_epi32(spu.gpr[op.ra].vi, _mm_set1_epi32(op.si10));
 }
 
-void spu_interpreter::CEQHI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CEQHI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpeq_epi16(CPU.GPR[op.ra].vi, _mm_set1_epi16(op.si10));
+	spu.gpr[op.rt].vi = _mm_cmpeq_epi16(spu.gpr[op.ra].vi, _mm_set1_epi16(op.si10));
 }
 
-void spu_interpreter::CEQBI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::CEQBI(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_cmpeq_epi8(CPU.GPR[op.ra].vi, _mm_set1_epi8(op.i8));
+	spu.gpr[op.rt].vi = _mm_cmpeq_epi8(spu.gpr[op.ra].vi, _mm_set1_epi8(op.i8));
 }
 
-void spu_interpreter::HEQI(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HEQI(SPUThread& spu, spu_opcode_t op)
 {
-	if (CPU.GPR[op.ra]._s32[3] == op.si10)
+	if (spu.gpr[op.ra]._s32[3] == op.si10)
 	{
-		CPU.halt();
+		spu.halt();
 	}
 }
 
 
-void spu_interpreter::HBRA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HBRA(SPUThread& spu, spu_opcode_t op)
 {
 }
 
-void spu_interpreter::HBRR(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::HBRR(SPUThread& spu, spu_opcode_t op)
 {
 }
 
-void spu_interpreter::ILA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::ILA(SPUThread& spu, spu_opcode_t op)
 {
-	CPU.GPR[op.rt].vi = _mm_set1_epi32(op.i18);
+	spu.gpr[op.rt].vi = _mm_set1_epi32(op.i18);
 }
 
 
-void spu_interpreter::SELB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SELB(SPUThread& spu, spu_opcode_t op)
 {
 	// rt <> rc
-	CPU.GPR[op.rc] = (CPU.GPR[op.rt] & CPU.GPR[op.rb]) | v128::andnot(CPU.GPR[op.rt], CPU.GPR[op.ra]);
+	spu.gpr[op.rc] = (spu.gpr[op.rt] & spu.gpr[op.rb]) | v128::andnot(spu.gpr[op.rt], spu.gpr[op.ra]);
 }
 
-void spu_interpreter::SHUFB(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::SHUFB(SPUThread& spu, spu_opcode_t op)
 {
 	// rt <> rc
-	const auto index = _mm_xor_si128(CPU.GPR[op.rt].vi, _mm_set1_epi32(0x0f0f0f0f));
-	const auto res1 = _mm_shuffle_epi8(CPU.GPR[op.ra].vi, index);
+	const auto index = _mm_xor_si128(spu.gpr[op.rt].vi, _mm_set1_epi32(0x0f0f0f0f));
+	const auto res1 = _mm_shuffle_epi8(spu.gpr[op.ra].vi, index);
 	const auto bit4 = _mm_set1_epi32(0x10101010);
 	const auto k1 = _mm_cmpeq_epi8(_mm_and_si128(index, bit4), bit4);
-	const auto res2 = _mm_or_si128(_mm_and_si128(k1, _mm_shuffle_epi8(CPU.GPR[op.rb].vi, index)), _mm_andnot_si128(k1, res1));
+	const auto res2 = _mm_or_si128(_mm_and_si128(k1, _mm_shuffle_epi8(spu.gpr[op.rb].vi, index)), _mm_andnot_si128(k1, res1));
 	const auto bit67 = _mm_set1_epi32(0xc0c0c0c0);
 	const auto k2 = _mm_cmpeq_epi8(_mm_and_si128(index, bit67), bit67);
 	const auto res3 = _mm_or_si128(res2, k2);
 	const auto bit567 = _mm_set1_epi32(0xe0e0e0e0);
 	const auto k3 = _mm_cmpeq_epi8(_mm_and_si128(index, bit567), bit567);
-	CPU.GPR[op.rc].vi = _mm_sub_epi8(res3, _mm_and_si128(k3, _mm_set1_epi32(0x7f7f7f7f)));
+	spu.gpr[op.rc].vi = _mm_sub_epi8(res3, _mm_and_si128(k3, _mm_set1_epi32(0x7f7f7f7f)));
 }
 
-void spu_interpreter::MPYA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::MPYA(SPUThread& spu, spu_opcode_t op)
 {
 	// rt <> rc
 	const auto mask = _mm_set1_epi32(0xffff);
-	CPU.GPR[op.rc].vi = _mm_add_epi32(CPU.GPR[op.rt].vi, _mm_madd_epi16(_mm_and_si128(CPU.GPR[op.ra].vi, mask), _mm_and_si128(CPU.GPR[op.rb].vi, mask)));
+	spu.gpr[op.rc].vi = _mm_add_epi32(spu.gpr[op.rt].vi, _mm_madd_epi16(_mm_and_si128(spu.gpr[op.ra].vi, mask), _mm_and_si128(spu.gpr[op.rb].vi, mask)));
 }
 
-void spu_interpreter::FNMS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FNMS(SPUThread& spu, spu_opcode_t op)
 {
 	// rt <> rc
-	CPU.GPR[op.rc].vf = _mm_sub_ps(CPU.GPR[op.rt].vf, _mm_mul_ps(CPU.GPR[op.ra].vf, CPU.GPR[op.rb].vf));
+	spu.gpr[op.rc].vf = _mm_sub_ps(spu.gpr[op.rt].vf, _mm_mul_ps(spu.gpr[op.ra].vf, spu.gpr[op.rb].vf));
 }
 
-void spu_interpreter::FMA(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FMA(SPUThread& spu, spu_opcode_t op)
 {
 	// rt <> rc
-	CPU.GPR[op.rc].vf = _mm_add_ps(_mm_mul_ps(CPU.GPR[op.ra].vf, CPU.GPR[op.rb].vf), CPU.GPR[op.rt].vf);
+	spu.gpr[op.rc].vf = _mm_add_ps(_mm_mul_ps(spu.gpr[op.ra].vf, spu.gpr[op.rb].vf), spu.gpr[op.rt].vf);
 }
 
-void spu_interpreter::FMS(SPUThread& CPU, spu_opcode_t op)
+void spu_interpreter::fast::FMS(SPUThread& spu, spu_opcode_t op)
 {
 	// rt <> rc
-	CPU.GPR[op.rc].vf = _mm_sub_ps(_mm_mul_ps(CPU.GPR[op.ra].vf, CPU.GPR[op.rb].vf), CPU.GPR[op.rt].vf);
+	spu.gpr[op.rc].vf = _mm_sub_ps(_mm_mul_ps(spu.gpr[op.ra].vf, spu.gpr[op.rb].vf), spu.gpr[op.rt].vf);
 }
 
-
-void spu_interpreter::UNK(SPUThread& CPU, spu_opcode_t op)
+static void SetHostRoundingMode(u32 rn)
 {
-	throw EXCEPTION("Unknown instruction (op=0x%08x)", op.opcode);
+	switch (rn)
+	{
+	case FPSCR_RN_NEAR:
+		fesetround(FE_TONEAREST);
+		break;
+	case FPSCR_RN_ZERO:
+		fesetround(FE_TOWARDZERO);
+		break;
+	case FPSCR_RN_PINF:
+		fesetround(FE_UPWARD);
+		break;
+	case FPSCR_RN_MINF:
+		fesetround(FE_DOWNWARD);
+		break;
+	}
 }
+
+// Floating-point utility constants and functions
+static const u32 FLOAT_MAX_NORMAL_I = 0x7F7FFFFF;
+static const float& FLOAT_MAX_NORMAL = (float&)FLOAT_MAX_NORMAL_I;
+static const u32 FLOAT_NAN_I = 0x7FC00000;
+static const float& FLOAT_NAN = (float&)FLOAT_NAN_I;
+static const u64 DOUBLE_NAN_I = 0x7FF8000000000000ULL;
+static const double DOUBLE_NAN = (double&)DOUBLE_NAN_I;
+
+inline bool issnan(double x)
+{
+	return isnan(x) && ((s64&)x) << 12 > 0;
+}
+
+inline bool issnan(float x)
+{
+	return isnan(x) && ((s32&)x) << 9 > 0;
+}
+
+inline int fexpf(float x)
+{
+	return ((u32&)x >> 23) & 0xFF;
+}
+
+inline bool isextended(float x)
+{
+	return fexpf(x) == 255;
+}
+
+inline float extended(bool sign, u32 mantissa) // returns -1^sign * 2^127 * (1.mantissa)
+{
+	u32 bits = sign << 31 | 0x7F800000 | mantissa;
+	return (float&)bits;
+}
+
+inline float ldexpf_extended(float x, int exp)  // ldexpf() for extended values, assumes result is in range
+{
+	u32 bits = (u32&)x;
+	if (bits << 1 != 0) bits += exp * 0x00800000;
+	return (float&)bits;
+}
+
+inline bool isdenormal(float x)
+{
+	const int fpc = _fpclass(x);
+#ifdef __GNUG__
+	return fpc == FP_SUBNORMAL;
+#else
+	return (fpc & (_FPCLASS_PD | _FPCLASS_ND)) != 0;
+#endif
+}
+
+inline bool isdenormal(double x)
+{
+	const int fpc = _fpclass(x);
+#ifdef __GNUG__
+	return fpc == FP_SUBNORMAL;
+#else
+	return (fpc & (_FPCLASS_PD | _FPCLASS_ND)) != 0;
+#endif
+}
+
+void spu_interpreter::precise::FREST(SPUThread& spu, spu_opcode_t op)
+{
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	for (int i = 0; i < 4; i++)
+	{
+		const float a = spu.gpr[op.ra]._f[i];
+		float result;
+		if (fexpf(a) == 0)
+		{
+			spu.fpscr.setDivideByZeroFlag(i);
+			result = extended(std::signbit(a), 0x7FFFFF);
+		}
+		else if (isextended(a))
+			result = 0.0f;
+		else
+			result = 1 / a;
+		spu.gpr[op.rt]._f[i] = result;
+	}
+}
+
+void spu_interpreter::precise::FRSQEST(SPUThread& spu, spu_opcode_t op)
+{
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	for (int i = 0; i < 4; i++)
+	{
+		const float a = spu.gpr[op.ra]._f[i];
+		float result;
+		if (fexpf(a) == 0)
+		{
+			spu.fpscr.setDivideByZeroFlag(i);
+			result = extended(0, 0x7FFFFF);
+		}
+		else if (isextended(a))
+			result = 0.5f / sqrtf(fabsf(ldexpf_extended(a, -2)));
+		else
+			result = 1 / sqrtf(fabsf(a));
+		spu.gpr[op.rt]._f[i] = result;
+	}
+}
+
+void spu_interpreter::precise::FCGT(SPUThread& spu, spu_opcode_t op)
+{
+	for (int i = 0; i < 4; i++)
+	{
+		const u32 a = spu.gpr[op.ra]._u32[i];
+		const u32 b = spu.gpr[op.rb]._u32[i];
+		const u32 abs_a = a & 0x7FFFFFFF;
+		const u32 abs_b = b & 0x7FFFFFFF;
+		const bool a_zero = (abs_a < 0x00800000);
+		const bool b_zero = (abs_b < 0x00800000);
+		bool pass;
+		if (a_zero)
+			pass = b >= 0x80800000;
+		else if (b_zero)
+			pass = (s32)a >= 0x00800000;
+		else if (a >= 0x80000000)
+			pass = (b >= 0x80000000 && a < b);
+		else
+			pass = (b >= 0x80000000 || a > b);
+		spu.gpr[op.rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
+	}
+}
+
+static void FA_FS(SPUThread& spu, spu_opcode_t op, bool sub)
+{
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	for (int w = 0; w < 4; w++)
+	{
+		const float a = spu.gpr[op.ra]._f[w];
+		const float b = sub ? -spu.gpr[op.rb]._f[w] : spu.gpr[op.rb]._f[w];
+		float result;
+		if (isdenormal(a))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			if (b == 0.0f || isdenormal(b))
+				result = +0.0f;
+			else
+				result = b;
+		}
+		else if (isdenormal(b))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			if (a == 0.0f)
+				result = +0.0f;
+			else
+				result = a;
+		}
+		else if (isextended(a) || isextended(b))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			if (isextended(a) && fexpf(b) < 255 - 32)
+			{
+				if (std::signbit(a) != std::signbit(b))
+				{
+					const u32 bits = (u32&)a - 1;
+					result = (float&)bits;
+				}
+				else
+
+					result = a;
+			}
+			else if (isextended(b) && fexpf(a) < 255 - 32)
+			{
+				if (std::signbit(a) != std::signbit(b))
+				{
+					const u32 bits = (u32&)b - 1;
+					result = (float&)bits;
+				}
+				else
+					result = b;
+			}
+			else
+			{
+				feclearexcept(FE_ALL_EXCEPT);
+				result = ldexpf_extended(a, -1) + ldexpf_extended(b, -1);
+				result = ldexpf_extended(result, 1);
+				if (fetestexcept(FE_OVERFLOW))
+				{
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+					result = extended(std::signbit(result), 0x7FFFFF);
+				}
+			}
+		}
+		else
+		{
+			result = a + b;
+			if (result == copysignf(FLOAT_MAX_NORMAL, result))
+			{
+				result = ldexpf_extended(ldexpf(a, -1) + ldexpf(b, -1), 1);
+				if (isextended(result))
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			}
+			else if (isdenormal(result))
+			{
+				spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
+				result = +0.0f;
+			}
+			else if (result == 0.0f)
+			{
+				if (fabsf(a) != fabsf(b))
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
+				result = +0.0f;
+			}
+		}
+		spu.gpr[op.rt]._f[w] = result;
+	}
+}
+
+void spu_interpreter::precise::FA(SPUThread& spu, spu_opcode_t op) { FA_FS(spu, op, false); }
+
+void spu_interpreter::precise::FS(SPUThread& spu, spu_opcode_t op) { FA_FS(spu, op, true); }
+
+void spu_interpreter::precise::FM(SPUThread& spu, spu_opcode_t op)
+{
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	for (int w = 0; w < 4; w++)
+	{
+		const float a = spu.gpr[op.ra]._f[w];
+		const float b = spu.gpr[op.rb]._f[w];
+		float result;
+		if (isdenormal(a) || isdenormal(b))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			result = +0.0f;
+		}
+		else if (isextended(a) || isextended(b))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			const bool sign = std::signbit(a) ^ std::signbit(b);
+			if (a == 0.0f || b == 0.0f)
+			{
+				result = +0.0f;
+			}
+			else if ((fexpf(a) - 127) + (fexpf(b) - 127) >= 129)
+			{
+				spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+				result = extended(sign, 0x7FFFFF);
+			}
+			else
+			{
+				if (isextended(a))
+					result = ldexpf_extended(a, -1) * b;
+				else
+					result = a * ldexpf_extended(b, -1);
+				if (result == copysignf(FLOAT_MAX_NORMAL, result))
+				{
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+					result = extended(sign, 0x7FFFFF);
+				}
+				else
+					result = ldexpf_extended(result, 1);
+			}
+		}
+		else
+		{
+			result = a * b;
+			if (result == copysignf(FLOAT_MAX_NORMAL, result))
+			{
+				feclearexcept(FE_ALL_EXCEPT);
+				if (fexpf(a) > fexpf(b))
+					result = ldexpf(a, -1) * b;
+				else
+					result = a * ldexpf(b, -1);
+				result = ldexpf_extended(result, 1);
+				if (isextended(result))
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+				if (fetestexcept(FE_OVERFLOW))
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+			}
+			else if (isdenormal(result))
+			{
+				spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
+				result = +0.0f;
+			}
+			else if (result == 0.0f)
+			{
+				if (a != 0.0f && b != 0.0f)
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
+				result = +0.0f;
+			}
+		}
+		spu.gpr[op.rt]._f[w] = result;
+	}
+}
+
+void spu_interpreter::precise::FCMGT(SPUThread& spu, spu_opcode_t op)
+{
+	for (int i = 0; i < 4; i++)
+	{
+		const u32 a = spu.gpr[op.ra]._u32[i];
+		const u32 b = spu.gpr[op.rb]._u32[i];
+		const u32 abs_a = a & 0x7FFFFFFF;
+		const u32 abs_b = b & 0x7FFFFFFF;
+		const bool a_zero = (abs_a < 0x00800000);
+		const bool b_zero = (abs_b < 0x00800000);
+		bool pass;
+		if (a_zero)
+			pass = false;
+		else if (b_zero)
+			pass = !a_zero;
+		else
+			pass = abs_a > abs_b;
+		spu.gpr[op.rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
+	}
+}
+
+enum DoubleOp
+{
+	DFASM_A,
+	DFASM_S,
+	DFASM_M,
+};
+
+static void DFASM(SPUThread& spu, spu_opcode_t op, DoubleOp operation)
+{
+	for (int i = 0; i < 2; i++)
+	{
+		double a = spu.gpr[op.ra]._d[i];
+		double b = spu.gpr[op.rb]._d[i];
+		if (isdenormal(a))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
+			a = copysign(0.0, a);
+		}
+		if (isdenormal(b))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
+			b = copysign(0.0, b);
+		}
+		double result;
+		if (isnan(a) || isnan(b))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
+			if (issnan(a) || issnan(b))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
+			result = DOUBLE_NAN;
+		}
+		else
+		{
+			SetHostRoundingMode(spu.fpscr.checkSliceRounding(i));
+			feclearexcept(FE_ALL_EXCEPT);
+			switch (operation)
+			{
+			case DFASM_A: result = a + b; break;
+			case DFASM_S: result = a - b; break;
+			case DFASM_M: result = a * b; break;
+			}
+			if (fetestexcept(FE_INVALID))
+			{
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
+				result = DOUBLE_NAN;
+			}
+			else
+			{
+				if (fetestexcept(FE_OVERFLOW))
+					spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DOVF);
+				if (fetestexcept(FE_UNDERFLOW))
+					spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DUNF);
+				if (fetestexcept(FE_INEXACT))
+					spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINX);
+			}
+		}
+		spu.gpr[op.rt]._d[i] = result;
+	}
+}
+
+void spu_interpreter::precise::DFA(SPUThread& spu, spu_opcode_t op) { DFASM(spu, op, DFASM_A); }
+
+void spu_interpreter::precise::DFS(SPUThread& spu, spu_opcode_t op) { DFASM(spu, op, DFASM_S); }
+
+void spu_interpreter::precise::DFM(SPUThread& spu, spu_opcode_t op) { DFASM(spu, op, DFASM_M); }
+
+static void DFMA(SPUThread& spu, spu_opcode_t op, bool neg, bool sub)
+{
+	for (int i = 0; i < 2; i++)
+	{
+		double a = spu.gpr[op.ra]._d[i];
+		double b = spu.gpr[op.rb]._d[i];
+		double c = spu.gpr[op.rt]._d[i];
+		if (isdenormal(a))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
+			a = copysign(0.0, a);
+		}
+		if (isdenormal(b))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
+			b = copysign(0.0, b);
+		}
+		if (isdenormal(c))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
+			c = copysign(0.0, c);
+		}
+		double result;
+		if (isnan(a) || isnan(b) || isnan(c))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
+			if (issnan(a) || issnan(b) || issnan(c) || (isinf(a) && b == 0.0f) || (a == 0.0f && isinf(b)))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
+			result = DOUBLE_NAN;
+		}
+		else
+		{
+			SetHostRoundingMode(spu.fpscr.checkSliceRounding(i));
+			feclearexcept(FE_ALL_EXCEPT);
+			result = fma(a, b, sub ? -c : c);
+			if (fetestexcept(FE_INVALID))
+			{
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
+				result = DOUBLE_NAN;
+			}
+			else
+			{
+				if (fetestexcept(FE_OVERFLOW))
+					spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DOVF);
+				if (fetestexcept(FE_UNDERFLOW))
+					spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DUNF);
+				if (fetestexcept(FE_INEXACT))
+					spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINX);
+				if (neg) result = -result;
+			}
+		}
+		spu.gpr[op.rt]._d[i] = result;
+	}
+}
+
+void spu_interpreter::precise::DFMA(SPUThread& spu, spu_opcode_t op) { DFMA(spu, op, false, false); }
+
+void spu_interpreter::precise::DFMS(SPUThread& spu, spu_opcode_t op) { DFMA(spu, op, false, true); }
+
+void spu_interpreter::precise::DFNMS(SPUThread& spu, spu_opcode_t op) { DFMA(spu, op, true, true); }
+
+void spu_interpreter::precise::DFNMA(SPUThread& spu, spu_opcode_t op) { DFMA(spu, op, true, false); }
+
+void spu_interpreter::precise::FSCRRD(SPUThread& spu, spu_opcode_t op)
+{
+	spu.fpscr.Read(spu.gpr[op.rt]);
+}
+
+void spu_interpreter::precise::FESD(SPUThread& spu, spu_opcode_t op)
+{
+	for (int i = 0; i < 2; i++)
+	{
+		const float a = spu.gpr[op.ra]._f[i * 2 + 1];
+		if (isnan(a))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
+			if (issnan(a))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
+			spu.gpr[op.rt]._d[i] = DOUBLE_NAN;
+		}
+		else if (isdenormal(a))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
+			spu.gpr[op.rt]._d[i] = 0.0;
+		}
+		else
+		{
+			spu.gpr[op.rt]._d[i] = (double)a;
+		}
+	}
+}
+
+void spu_interpreter::precise::FRDS(SPUThread& spu, spu_opcode_t op)
+{
+	for (int i = 0; i < 2; i++)
+	{
+		SetHostRoundingMode(spu.fpscr.checkSliceRounding(i));
+		const double a = spu.gpr[op.ra]._d[i];
+		if (isnan(a))
+		{
+			spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
+			if (issnan(a))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
+			spu.gpr[op.rt]._f[i * 2 + 1] = FLOAT_NAN;
+		}
+		else
+		{
+			feclearexcept(FE_ALL_EXCEPT);
+			spu.gpr[op.rt]._f[i * 2 + 1] = (float)a;
+			if (fetestexcept(FE_OVERFLOW))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DOVF);
+			if (fetestexcept(FE_UNDERFLOW))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DUNF);
+			if (fetestexcept(FE_INEXACT))
+				spu.fpscr.setDoublePrecisionExceptionFlags(i, FPSCR_DINX);
+		}
+		spu.gpr[op.rt]._u32[i * 2] = 0;
+	}
+}
+
+void spu_interpreter::precise::FSCRWR(SPUThread& spu, spu_opcode_t op)
+{
+	spu.fpscr.Write(spu.gpr[op.ra]);
+}
+
+void spu_interpreter::precise::FCEQ(SPUThread& spu, spu_opcode_t op)
+{
+	for (int i = 0; i < 4; i++)
+	{
+		const u32 a = spu.gpr[op.ra]._u32[i];
+		const u32 b = spu.gpr[op.rb]._u32[i];
+		const u32 abs_a = a & 0x7FFFFFFF;
+		const u32 abs_b = b & 0x7FFFFFFF;
+		const bool a_zero = (abs_a < 0x00800000);
+		const bool b_zero = (abs_b < 0x00800000);
+		const bool pass = a == b || (a_zero && b_zero);
+		spu.gpr[op.rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
+	}
+}
+
+void spu_interpreter::precise::FCMEQ(SPUThread& spu, spu_opcode_t op)
+{
+	for (int i = 0; i < 4; i++)
+	{
+		const u32 a = spu.gpr[op.ra]._u32[i];
+		const u32 b = spu.gpr[op.rb]._u32[i];
+		const u32 abs_a = a & 0x7FFFFFFF;
+		const u32 abs_b = b & 0x7FFFFFFF;
+		const bool a_zero = (abs_a < 0x00800000);
+		const bool b_zero = (abs_b < 0x00800000);
+		const bool pass = abs_a == abs_b || (a_zero && b_zero);
+		spu.gpr[op.rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
+	}
+}
+
+void spu_interpreter::precise::FI(SPUThread& spu, spu_opcode_t op)
+{
+	// TODO
+	spu.gpr[op.rt] = spu.gpr[op.rb];
+}
+
+void spu_interpreter::precise::CFLTS(SPUThread& spu, spu_opcode_t op)
+{
+	const int scale = 173 - (op.i8 & 0xff); //unsigned immediate
+	for (int i = 0; i < 4; i++)
+	{
+		const float a = spu.gpr[op.ra]._f[i];
+		float scaled;
+		if ((fexpf(a) - 127) + scale >= 32)
+			scaled = copysignf(4294967296.0f, a);
+		else
+			scaled = ldexpf(a, scale);
+		s32 result;
+		if (scaled >= 2147483648.0f)
+			result = 0x7FFFFFFF;
+		else if (scaled < -2147483648.0f)
+			result = 0x80000000;
+		else
+			result = (s32)scaled;
+		spu.gpr[op.rt]._s32[i] = result;
+	}
+}
+
+void spu_interpreter::precise::CFLTU(SPUThread& spu, spu_opcode_t op)
+{
+	const int scale = 173 - (op.i8 & 0xff); //unsigned immediate
+	for (int i = 0; i < 4; i++)
+	{
+		const float a = spu.gpr[op.ra]._f[i];
+		float scaled;
+		if ((fexpf(a) - 127) + scale >= 32)
+			scaled = copysignf(4294967296.0f, a);
+		else
+			scaled = ldexpf(a, scale);
+		u32 result;
+		if (scaled >= 4294967296.0f)
+			result = 0xFFFFFFFF;
+		else if (scaled < 0.0f)
+			result = 0;
+		else
+			result = (u32)scaled;
+		spu.gpr[op.rt]._u32[i] = result;
+	}
+}
+
+void spu_interpreter::precise::CSFLT(SPUThread& spu, spu_opcode_t op)
+{
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	const int scale = 155 - (op.i8 & 0xff); //unsigned immediate
+	for (int i = 0; i < 4; i++)
+	{
+		const s32 a = spu.gpr[op.ra]._s32[i];
+		spu.gpr[op.rt]._f[i] = (float)a;
+
+		u32 exp = ((spu.gpr[op.rt]._u32[i] >> 23) & 0xff) - scale;
+
+		if (exp > 255) //< 0
+			exp = 0;
+
+		spu.gpr[op.rt]._u32[i] = (spu.gpr[op.rt]._u32[i] & 0x807fffff) | (exp << 23);
+		if (isdenormal(spu.gpr[op.rt]._f[i]) || (spu.gpr[op.rt]._f[i] == 0.0f && a != 0))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(i, FPSCR_SUNF | FPSCR_SDIFF);
+			spu.gpr[op.rt]._f[i] = 0.0f;
+		}
+	}
+}
+
+void spu_interpreter::precise::CUFLT(SPUThread& spu, spu_opcode_t op)
+{
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	const int scale = 155 - (op.i8 & 0xff); //unsigned immediate
+	for (int i = 0; i < 4; i++)
+	{
+		const u32 a = spu.gpr[op.ra]._u32[i];
+		spu.gpr[op.rt]._f[i] = (float)a;
+
+		u32 exp = ((spu.gpr[op.rt]._u32[i] >> 23) & 0xff) - scale;
+
+		if (exp > 255) //< 0
+			exp = 0;
+
+		spu.gpr[op.rt]._u32[i] = (spu.gpr[op.rt]._u32[i] & 0x807fffff) | (exp << 23);
+		if (isdenormal(spu.gpr[op.rt]._f[i]) || (spu.gpr[op.rt]._f[i] == 0.0f && a != 0))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(i, FPSCR_SUNF | FPSCR_SDIFF);
+			spu.gpr[op.rt]._f[i] = 0.0f;
+		}
+	}
+}
+
+static void FMA(SPUThread& spu, spu_opcode_t op, bool neg, bool sub)
+{
+	// rt <> rc
+
+	SetHostRoundingMode(FPSCR_RN_ZERO);
+	for (int w = 0; w < 4; w++)
+	{
+		float a = spu.gpr[op.ra]._f[w];
+		float b = neg ? -spu.gpr[op.rb]._f[w] : spu.gpr[op.rb]._f[w];
+		float c = (neg != sub) ? -spu.gpr[op.rt]._f[w] : spu.gpr[op.rt]._f[w];
+		if (isdenormal(a))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			a = 0.0f;
+		}
+		if (isdenormal(b))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			b = 0.0f;
+		}
+		if (isdenormal(c))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			c = 0.0f;
+		}
+
+		const bool sign = std::signbit(a) ^ std::signbit(b);
+		float result;
+
+		if (isextended(a) || isextended(b))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			if (a == 0.0f || b == 0.0f)
+			{
+				result = c;
+			}
+			else if ((fexpf(a) - 127) + (fexpf(b) - 127) >= 130)
+			{
+				spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+				result = extended(sign, 0x7FFFFF);
+			}
+			else
+			{
+				float new_a, new_b;
+				if (isextended(a))
+				{
+					new_a = ldexpf_extended(a, -2);
+					new_b = b;
+				}
+				else
+				{
+					new_a = a;
+					new_b = ldexpf_extended(b, -2);
+				}
+				if (fexpf(c) < 3)
+				{
+					result = new_a * new_b;
+					if (c != 0.0f && std::signbit(c) != sign)
+					{
+						u32 bits = (u32&)result - 1;
+						result = (float&)bits;
+					}
+				}
+				else
+				{
+					result = fmaf(new_a, new_b, ldexpf_extended(c, -2));
+				}
+				if (fabsf(result) >= ldexpf(1.0f, 127))
+				{
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+					result = extended(sign, 0x7FFFFF);
+				}
+				else
+				{
+					result = ldexpf_extended(result, 2);
+				}
+			}
+		}
+		else if (isextended(c))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+			if (a == 0.0f || b == 0.0f)
+			{
+				result = c;
+			}
+			else if ((fexpf(a) - 127) + (fexpf(b) - 127) < 96)
+			{
+				result = c;
+				if (sign != std::signbit(c))
+				{
+					u32 bits = (u32&)result - 1;
+					result = (float&)bits;
+				}
+			}
+			else
+			{
+				result = fmaf(ldexpf(a, -1), ldexpf(b, -1), ldexpf_extended(c, -2));
+				if (fabsf(result) >= ldexpf(1.0f, 127))
+				{
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+					result = extended(sign, 0x7FFFFF);
+				}
+				else
+				{
+					result = ldexpf_extended(result, 2);
+				}
+			}
+		}
+		else
+		{
+			feclearexcept(FE_ALL_EXCEPT);
+			result = fmaf(a, b, c);
+			if (fetestexcept(FE_OVERFLOW))
+			{
+				spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
+				if (fexpf(a) > fexpf(b))
+					result = fmaf(ldexpf(a, -2), b, ldexpf(c, -2));
+				else
+					result = fmaf(a, ldexpf(b, -2), ldexpf(c, -2));
+				if (fabsf(result) >= ldexpf(1.0f, 127))
+				{
+					spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
+					result = extended(sign, 0x7FFFFF);
+				}
+				else
+				{
+					result = ldexpf_extended(result, 2);
+				}
+			}
+			else if (fetestexcept(FE_UNDERFLOW))
+			{
+				spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
+			}
+		}
+		if (isdenormal(result))
+		{
+			spu.fpscr.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
+			result = 0.0f;
+		}
+		else if (result == 0.0f)
+		{
+			result = +0.0f;
+		}
+		spu.gpr[op.rc]._f[w] = result;
+	}
+}
+
+void spu_interpreter::precise::FNMS(SPUThread& spu, spu_opcode_t op) { FMA(spu, op, true, true); }
+
+void spu_interpreter::precise::FMA(SPUThread& spu, spu_opcode_t op) { FMA(spu, op, false, false); }
+
+void spu_interpreter::precise::FMS(SPUThread& spu, spu_opcode_t op) { FMA(spu, op, false, true); }
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.h b/rpcs3/Emu/Cell/SPUInterpreter.h
index 49330328f5..5b57cd671e 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.h
+++ b/rpcs3/Emu/Cell/SPUInterpreter.h
@@ -1,2066 +1,259 @@
 #pragma once
 
-#include <fenv.h>
+#include "SPUOpcodes.h"
 
-static void SetHostRoundingMode(u32 rn)
+class SPUThread;
+
+using spu_inter_func_t = void(*)(SPUThread& spu, spu_opcode_t opcode);
+
+namespace spu_interpreter
 {
-	switch (rn)
+	namespace fast
 	{
-	case FPSCR_RN_NEAR:
-		fesetround(FE_TONEAREST);
-		break;
-	case FPSCR_RN_ZERO:
-		fesetround(FE_TOWARDZERO);
-		break;
-	case FPSCR_RN_PINF:
-		fesetround(FE_UPWARD);
-		break;
-	case FPSCR_RN_MINF:
-		fesetround(FE_DOWNWARD);
-		break;
+		extern const spu_opcode_table_t<spu_inter_func_t> g_spu_opcode_table;
+	}
+
+	namespace precise
+	{
+		extern const spu_opcode_table_t<spu_inter_func_t> g_spu_opcode_table;
+	}
+
+	void default_function(SPUThread& spu, spu_opcode_t op);
+	void set_interrupt_status(SPUThread& spu, spu_opcode_t op);
+
+	void STOP(SPUThread& spu, spu_opcode_t op);
+	void LNOP(SPUThread& spu, spu_opcode_t op);
+	void SYNC(SPUThread& spu, spu_opcode_t op);
+	void DSYNC(SPUThread& spu, spu_opcode_t op);
+	void MFSPR(SPUThread& spu, spu_opcode_t op);
+	void RDCH(SPUThread& spu, spu_opcode_t op);
+	void RCHCNT(SPUThread& spu, spu_opcode_t op);
+	void SF(SPUThread& spu, spu_opcode_t op);
+	void OR(SPUThread& spu, spu_opcode_t op);
+	void BG(SPUThread& spu, spu_opcode_t op);
+	void SFH(SPUThread& spu, spu_opcode_t op);
+	void NOR(SPUThread& spu, spu_opcode_t op);
+	void ABSDB(SPUThread& spu, spu_opcode_t op);
+	void ROT(SPUThread& spu, spu_opcode_t op);
+	void ROTM(SPUThread& spu, spu_opcode_t op);
+	void ROTMA(SPUThread& spu, spu_opcode_t op);
+	void SHL(SPUThread& spu, spu_opcode_t op);
+	void ROTH(SPUThread& spu, spu_opcode_t op);
+	void ROTHM(SPUThread& spu, spu_opcode_t op);
+	void ROTMAH(SPUThread& spu, spu_opcode_t op);
+	void SHLH(SPUThread& spu, spu_opcode_t op);
+	void ROTI(SPUThread& spu, spu_opcode_t op);
+	void ROTMI(SPUThread& spu, spu_opcode_t op);
+	void ROTMAI(SPUThread& spu, spu_opcode_t op);
+	void SHLI(SPUThread& spu, spu_opcode_t op);
+	void ROTHI(SPUThread& spu, spu_opcode_t op);
+	void ROTHMI(SPUThread& spu, spu_opcode_t op);
+	void ROTMAHI(SPUThread& spu, spu_opcode_t op);
+	void SHLHI(SPUThread& spu, spu_opcode_t op);
+	void A(SPUThread& spu, spu_opcode_t op);
+	void AND(SPUThread& spu, spu_opcode_t op);
+	void CG(SPUThread& spu, spu_opcode_t op);
+	void AH(SPUThread& spu, spu_opcode_t op);
+	void NAND(SPUThread& spu, spu_opcode_t op);
+	void AVGB(SPUThread& spu, spu_opcode_t op);
+	void MTSPR(SPUThread& spu, spu_opcode_t op);
+	void WRCH(SPUThread& spu, spu_opcode_t op);
+	void BIZ(SPUThread& spu, spu_opcode_t op);
+	void BINZ(SPUThread& spu, spu_opcode_t op);
+	void BIHZ(SPUThread& spu, spu_opcode_t op);
+	void BIHNZ(SPUThread& spu, spu_opcode_t op);
+	void STOPD(SPUThread& spu, spu_opcode_t op);
+	void STQX(SPUThread& spu, spu_opcode_t op);
+	void BI(SPUThread& spu, spu_opcode_t op);
+	void BISL(SPUThread& spu, spu_opcode_t op);
+	void IRET(SPUThread& spu, spu_opcode_t op);
+	void BISLED(SPUThread& spu, spu_opcode_t op);
+	void HBR(SPUThread& spu, spu_opcode_t op);
+	void GB(SPUThread& spu, spu_opcode_t op);
+	void GBH(SPUThread& spu, spu_opcode_t op);
+	void GBB(SPUThread& spu, spu_opcode_t op);
+	void FSM(SPUThread& spu, spu_opcode_t op);
+	void FSMH(SPUThread& spu, spu_opcode_t op);
+	void FSMB(SPUThread& spu, spu_opcode_t op);
+	void LQX(SPUThread& spu, spu_opcode_t op);
+	void ROTQBYBI(SPUThread& spu, spu_opcode_t op);
+	void ROTQMBYBI(SPUThread& spu, spu_opcode_t op);
+	void SHLQBYBI(SPUThread& spu, spu_opcode_t op);
+	void CBX(SPUThread& spu, spu_opcode_t op);
+	void CHX(SPUThread& spu, spu_opcode_t op);
+	void CWX(SPUThread& spu, spu_opcode_t op);
+	void CDX(SPUThread& spu, spu_opcode_t op);
+	void ROTQBI(SPUThread& spu, spu_opcode_t op);
+	void ROTQMBI(SPUThread& spu, spu_opcode_t op);
+	void SHLQBI(SPUThread& spu, spu_opcode_t op);
+	void ROTQBY(SPUThread& spu, spu_opcode_t op);
+	void ROTQMBY(SPUThread& spu, spu_opcode_t op);
+	void SHLQBY(SPUThread& spu, spu_opcode_t op);
+	void ORX(SPUThread& spu, spu_opcode_t op);
+	void CBD(SPUThread& spu, spu_opcode_t op);
+	void CHD(SPUThread& spu, spu_opcode_t op);
+	void CWD(SPUThread& spu, spu_opcode_t op);
+	void CDD(SPUThread& spu, spu_opcode_t op);
+	void ROTQBII(SPUThread& spu, spu_opcode_t op);
+	void ROTQMBII(SPUThread& spu, spu_opcode_t op);
+	void SHLQBII(SPUThread& spu, spu_opcode_t op);
+	void ROTQBYI(SPUThread& spu, spu_opcode_t op);
+	void ROTQMBYI(SPUThread& spu, spu_opcode_t op);
+	void SHLQBYI(SPUThread& spu, spu_opcode_t op);
+	void NOP(SPUThread& spu, spu_opcode_t op);
+	void CGT(SPUThread& spu, spu_opcode_t op);
+	void XOR(SPUThread& spu, spu_opcode_t op);
+	void CGTH(SPUThread& spu, spu_opcode_t op);
+	void EQV(SPUThread& spu, spu_opcode_t op);
+	void CGTB(SPUThread& spu, spu_opcode_t op);
+	void SUMB(SPUThread& spu, spu_opcode_t op);
+	void HGT(SPUThread& spu, spu_opcode_t op);
+	void CLZ(SPUThread& spu, spu_opcode_t op);
+	void XSWD(SPUThread& spu, spu_opcode_t op);
+	void XSHW(SPUThread& spu, spu_opcode_t op);
+	void CNTB(SPUThread& spu, spu_opcode_t op);
+	void XSBH(SPUThread& spu, spu_opcode_t op);
+	void CLGT(SPUThread& spu, spu_opcode_t op);
+	void ANDC(SPUThread& spu, spu_opcode_t op);
+	void CLGTH(SPUThread& spu, spu_opcode_t op);
+	void ORC(SPUThread& spu, spu_opcode_t op);
+	void CLGTB(SPUThread& spu, spu_opcode_t op);
+	void HLGT(SPUThread& spu, spu_opcode_t op);
+	void CEQ(SPUThread& spu, spu_opcode_t op);
+	void MPYHHU(SPUThread& spu, spu_opcode_t op);
+	void ADDX(SPUThread& spu, spu_opcode_t op);
+	void SFX(SPUThread& spu, spu_opcode_t op);
+	void CGX(SPUThread& spu, spu_opcode_t op);
+	void BGX(SPUThread& spu, spu_opcode_t op);
+	void MPYHHA(SPUThread& spu, spu_opcode_t op);
+	void MPYHHAU(SPUThread& spu, spu_opcode_t op);
+	void MPY(SPUThread& spu, spu_opcode_t op);
+	void MPYH(SPUThread& spu, spu_opcode_t op);
+	void MPYHH(SPUThread& spu, spu_opcode_t op);
+	void MPYS(SPUThread& spu, spu_opcode_t op);
+	void CEQH(SPUThread& spu, spu_opcode_t op);
+	void MPYU(SPUThread& spu, spu_opcode_t op);
+	void CEQB(SPUThread& spu, spu_opcode_t op);
+	void HEQ(SPUThread& spu, spu_opcode_t op);
+	void BRZ(SPUThread& spu, spu_opcode_t op);
+	void STQA(SPUThread& spu, spu_opcode_t op);
+	void BRNZ(SPUThread& spu, spu_opcode_t op);
+	void BRHZ(SPUThread& spu, spu_opcode_t op);
+	void BRHNZ(SPUThread& spu, spu_opcode_t op);
+	void STQR(SPUThread& spu, spu_opcode_t op);
+	void BRA(SPUThread& spu, spu_opcode_t op);
+	void LQA(SPUThread& spu, spu_opcode_t op);
+	void BRASL(SPUThread& spu, spu_opcode_t op);
+	void BR(SPUThread& spu, spu_opcode_t op);
+	void FSMBI(SPUThread& spu, spu_opcode_t op);
+	void BRSL(SPUThread& spu, spu_opcode_t op);
+	void LQR(SPUThread& spu, spu_opcode_t op);
+	void IL(SPUThread& spu, spu_opcode_t op);
+	void ILHU(SPUThread& spu, spu_opcode_t op);
+	void ILH(SPUThread& spu, spu_opcode_t op);
+	void IOHL(SPUThread& spu, spu_opcode_t op);
+	void ORI(SPUThread& spu, spu_opcode_t op);
+	void ORHI(SPUThread& spu, spu_opcode_t op);
+	void ORBI(SPUThread& spu, spu_opcode_t op);
+	void SFI(SPUThread& spu, spu_opcode_t op);
+	void SFHI(SPUThread& spu, spu_opcode_t op);
+	void ANDI(SPUThread& spu, spu_opcode_t op);
+	void ANDHI(SPUThread& spu, spu_opcode_t op);
+	void ANDBI(SPUThread& spu, spu_opcode_t op);
+	void AI(SPUThread& spu, spu_opcode_t op);
+	void AHI(SPUThread& spu, spu_opcode_t op);
+	void STQD(SPUThread& spu, spu_opcode_t op);
+	void LQD(SPUThread& spu, spu_opcode_t op);
+	void XORI(SPUThread& spu, spu_opcode_t op);
+	void XORHI(SPUThread& spu, spu_opcode_t op);
+	void XORBI(SPUThread& spu, spu_opcode_t op);
+	void CGTI(SPUThread& spu, spu_opcode_t op);
+	void CGTHI(SPUThread& spu, spu_opcode_t op);
+	void CGTBI(SPUThread& spu, spu_opcode_t op);
+	void HGTI(SPUThread& spu, spu_opcode_t op);
+	void CLGTI(SPUThread& spu, spu_opcode_t op);
+	void CLGTHI(SPUThread& spu, spu_opcode_t op);
+	void CLGTBI(SPUThread& spu, spu_opcode_t op);
+	void HLGTI(SPUThread& spu, spu_opcode_t op);
+	void MPYI(SPUThread& spu, spu_opcode_t op);
+	void MPYUI(SPUThread& spu, spu_opcode_t op);
+	void CEQI(SPUThread& spu, spu_opcode_t op);
+	void CEQHI(SPUThread& spu, spu_opcode_t op);
+	void CEQBI(SPUThread& spu, spu_opcode_t op);
+	void HEQI(SPUThread& spu, spu_opcode_t op);
+	void HBRA(SPUThread& spu, spu_opcode_t op);
+	void HBRR(SPUThread& spu, spu_opcode_t op);
+	void ILA(SPUThread& spu, spu_opcode_t op);
+	void SELB(SPUThread& spu, spu_opcode_t op);
+	void SHUFB(SPUThread& spu, spu_opcode_t op);
+	void MPYA(SPUThread& spu, spu_opcode_t op);
+	void DFCGT(SPUThread& spu, spu_opcode_t op);
+	void DFCMGT(SPUThread& spu, spu_opcode_t op);
+	void DFTSV(SPUThread& spu, spu_opcode_t op);
+	void DFCEQ(SPUThread& spu, spu_opcode_t op);
+	void DFCMEQ(SPUThread& spu, spu_opcode_t op);
+
+	namespace fast
+	{
+		void FREST(SPUThread& spu, spu_opcode_t op);
+		void FRSQEST(SPUThread& spu, spu_opcode_t op);
+		void FCGT(SPUThread& spu, spu_opcode_t op);
+		void FA(SPUThread& spu, spu_opcode_t op);
+		void FS(SPUThread& spu, spu_opcode_t op);
+		void FM(SPUThread& spu, spu_opcode_t op);
+		void FCMGT(SPUThread& spu, spu_opcode_t op);
+		void DFA(SPUThread& spu, spu_opcode_t op);
+		void DFS(SPUThread& spu, spu_opcode_t op);
+		void DFM(SPUThread& spu, spu_opcode_t op);
+		void DFMA(SPUThread& spu, spu_opcode_t op);
+		void DFMS(SPUThread& spu, spu_opcode_t op);
+		void DFNMS(SPUThread& spu, spu_opcode_t op);
+		void DFNMA(SPUThread& spu, spu_opcode_t op);
+		void FSCRRD(SPUThread& spu, spu_opcode_t op);
+		void FESD(SPUThread& spu, spu_opcode_t op);
+		void FRDS(SPUThread& spu, spu_opcode_t op);
+		void FSCRWR(SPUThread& spu, spu_opcode_t op);
+		void FCEQ(SPUThread& spu, spu_opcode_t op);
+		void FCMEQ(SPUThread& spu, spu_opcode_t op);
+		void FI(SPUThread& spu, spu_opcode_t op);
+		void CFLTS(SPUThread& spu, spu_opcode_t op);
+		void CFLTU(SPUThread& spu, spu_opcode_t op);
+		void CSFLT(SPUThread& spu, spu_opcode_t op);
+		void CUFLT(SPUThread& spu, spu_opcode_t op);
+		void FNMS(SPUThread& spu, spu_opcode_t op);
+		void FMA(SPUThread& spu, spu_opcode_t op);
+		void FMS(SPUThread& spu, spu_opcode_t op);
+	}
+
+	namespace precise
+	{
+		void FREST(SPUThread& spu, spu_opcode_t op);
+		void FRSQEST(SPUThread& spu, spu_opcode_t op);
+		void FCGT(SPUThread& spu, spu_opcode_t op);
+		void FA(SPUThread& spu, spu_opcode_t op);
+		void FS(SPUThread& spu, spu_opcode_t op);
+		void FM(SPUThread& spu, spu_opcode_t op);
+		void FCMGT(SPUThread& spu, spu_opcode_t op);
+		void DFA(SPUThread& spu, spu_opcode_t op);
+		void DFS(SPUThread& spu, spu_opcode_t op);
+		void DFM(SPUThread& spu, spu_opcode_t op);
+		void DFMA(SPUThread& spu, spu_opcode_t op);
+		void DFMS(SPUThread& spu, spu_opcode_t op);
+		void DFNMS(SPUThread& spu, spu_opcode_t op);
+		void DFNMA(SPUThread& spu, spu_opcode_t op);
+		void FSCRRD(SPUThread& spu, spu_opcode_t op);
+		void FESD(SPUThread& spu, spu_opcode_t op);
+		void FRDS(SPUThread& spu, spu_opcode_t op);
+		void FSCRWR(SPUThread& spu, spu_opcode_t op);
+		void FCEQ(SPUThread& spu, spu_opcode_t op);
+		void FCMEQ(SPUThread& spu, spu_opcode_t op);
+		void FI(SPUThread& spu, spu_opcode_t op);
+		void CFLTS(SPUThread& spu, spu_opcode_t op);
+		void CFLTU(SPUThread& spu, spu_opcode_t op);
+		void CSFLT(SPUThread& spu, spu_opcode_t op);
+		void CUFLT(SPUThread& spu, spu_opcode_t op);
+		void FNMS(SPUThread& spu, spu_opcode_t op);
+		void FMA(SPUThread& spu, spu_opcode_t op);
+		void FMS(SPUThread& spu, spu_opcode_t op);
 	}
 }
-
-#define UNIMPLEMENTED() UNK(__FUNCTION__)
-
-#define MEM_AND_REG_HASH() \
-	unsigned char mem_h[20]; sha1(vm::get_ptr<u8>(CPU.ls_offset), 256*1024, mem_h); \
-	unsigned char reg_h[20]; sha1((const unsigned char*)CPU.GPR, sizeof(CPU.GPR), reg_h); \
-	LOG_NOTICE(Log::SPU, "Mem hash: 0x%llx, reg hash: 0x%llx", *(u64*)mem_h, *(u64*)reg_h);
-
-#define LOG2_OPCODE(...) //MEM_AND_REG_HASH(); LOG_NOTICE(Log::SPU, __FUNCTION__ "(): " __VA_ARGS__)
-
-#define LOG5_OPCODE(...) ///
-
-// Floating-point utility constants and functions
-static const u32 FLOAT_MAX_NORMAL_I = 0x7F7FFFFF;
-static const float& FLOAT_MAX_NORMAL = (float&)FLOAT_MAX_NORMAL_I;
-static const u32 FLOAT_NAN_I = 0x7FC00000;
-static const float& FLOAT_NAN = (float&)FLOAT_NAN_I;
-static const u64 DOUBLE_NAN_I = 0x7FF8000000000000ULL;
-static const double& DOUBLE_NAN = (double&)DOUBLE_NAN_I;
-static inline bool issnan(double x) {return isnan(x) && ((s64&)x)<<12 > 0;}
-static inline bool issnan(float x) {return isnan(x) && ((s32&)x)<<9 > 0;}
-static inline int fexpf(float x) {return ((u32&)x >> 23) & 0xFF;}
-static inline bool isextended(float x) {return fexpf(x) == 255;}
-static inline float extended(bool sign, u32 mantissa) // returns -1^sign * 2^127 * (1.mantissa)
-{
-    u32 bits = sign<<31 | 0x7F800000 | mantissa;
-    return (float&)bits;
-}
-static inline float ldexpf_extended(float x, int exp)  // ldexpf() for extended values, assumes result is in range
-{
-    u32 bits = (u32&)x;
-    if (bits << 1 != 0) bits += exp * 0x00800000;
-    return (float&)bits;
-}
-static inline bool isdenormal(float x)
-{
-	const int fpc = _fpclass(x);
-#ifdef __GNUG__
-	return fpc == FP_SUBNORMAL;
-#else
-	return (fpc & (_FPCLASS_PD | _FPCLASS_ND)) != 0;
-#endif
-}
-static inline bool isdenormal(double x)
-{
-	const int fpc = _fpclass(x);
-#ifdef __GNUG__
-	return fpc == FP_SUBNORMAL;
-#else
-	return (fpc & (_FPCLASS_PD | _FPCLASS_ND)) != 0;
-#endif
-}
-static double SilenceNaN(double x)
-{
-	u64 bits = (u64&)x;
-	bits |= 0x0008000000000000ULL;
-	return (double&)bits;
-}
-
-
-class SPUInterpreter : public SPUOpcodes
-{
-private:
-	SPUThread& CPU;
-
-public:
-	SPUInterpreter(SPUThread& cpu) : CPU(cpu)
-	{
-	}
-
-private:
-	//0 - 10
-	void STOP(u32 code)
-	{
-		CPU.stop_and_signal(code);
-		LOG2_OPCODE();
-	}
-	void LNOP()
-	{
-	}
-	void SYNC(u32 Cbit)
-	{
-		// This instruction must be used following a store instruction that modifies the instruction stream.
-		_mm_mfence();
-	}
-	void DSYNC()
-	{
-		// This instruction forces all earlier load, store, and channel instructions to complete before proceeding.
-		_mm_mfence();
-	}
-	void MFSPR(u32 rt, u32 sa)
-	{
-		CPU.GPR[rt].clear();  // All SPRs read as zero.
-	}
-	void RDCH(u32 rt, u32 ra)
-	{
-		CPU.GPR[rt] = v128::from32r(CPU.get_ch_value(ra));
-	}
-	void RCHCNT(u32 rt, u32 ra)
-	{
-		CPU.GPR[rt] = v128::from32r(CPU.get_ch_count(ra));
-	}
-	void SF(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = CPU.GPR[rb]._u32[0] - CPU.GPR[ra]._u32[0];
-		CPU.GPR[rt]._u32[1] = CPU.GPR[rb]._u32[1] - CPU.GPR[ra]._u32[1];
-		CPU.GPR[rt]._u32[2] = CPU.GPR[rb]._u32[2] - CPU.GPR[ra]._u32[2];
-		CPU.GPR[rt]._u32[3] = CPU.GPR[rb]._u32[3] - CPU.GPR[ra]._u32[3];
-	}
-	void OR(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] | CPU.GPR[rb]._u32[0];
-		CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] | CPU.GPR[rb]._u32[1];
-		CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] | CPU.GPR[rb]._u32[2];
-		CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] | CPU.GPR[rb]._u32[3];
-	}
-	void BG(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] > CPU.GPR[rb]._u32[0] ? 0 : 1;
-		CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] > CPU.GPR[rb]._u32[1] ? 0 : 1;
-		CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] > CPU.GPR[rb]._u32[2] ? 0 : 1;
-		CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] > CPU.GPR[rb]._u32[3] ? 0 : 1;
-	}
-	void SFH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = CPU.GPR[rb]._u16[h] - CPU.GPR[ra]._u16[h];
-	}
-	void NOR(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = ~(CPU.GPR[ra]._u32[0] | CPU.GPR[rb]._u32[0]);
-		CPU.GPR[rt]._u32[1] = ~(CPU.GPR[ra]._u32[1] | CPU.GPR[rb]._u32[1]);
-		CPU.GPR[rt]._u32[2] = ~(CPU.GPR[ra]._u32[2] | CPU.GPR[rb]._u32[2]);
-		CPU.GPR[rt]._u32[3] = ~(CPU.GPR[ra]._u32[3] | CPU.GPR[rb]._u32[3]);
-	}
-	void ABSDB(u32 rt, u32 ra, u32 rb)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = CPU.GPR[rb]._u8[b] > CPU.GPR[ra]._u8[b] ? CPU.GPR[rb]._u8[b] - CPU.GPR[ra]._u8[b] : CPU.GPR[ra]._u8[b] - CPU.GPR[rb]._u8[b];
-	}
-	void ROT(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = (CPU.GPR[ra]._u32[0] << (CPU.GPR[rb]._u32[0] & 0x1f)) | (CPU.GPR[ra]._u32[0] >> (32 - (CPU.GPR[rb]._u32[0] & 0x1f)));
-		CPU.GPR[rt]._u32[1] = (CPU.GPR[ra]._u32[1] << (CPU.GPR[rb]._u32[1] & 0x1f)) | (CPU.GPR[ra]._u32[1] >> (32 - (CPU.GPR[rb]._u32[1] & 0x1f)));
-		CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << (CPU.GPR[rb]._u32[2] & 0x1f)) | (CPU.GPR[ra]._u32[2] >> (32 - (CPU.GPR[rb]._u32[2] & 0x1f)));
-		CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] << (CPU.GPR[rb]._u32[3] & 0x1f)) | (CPU.GPR[ra]._u32[3] >> (32 - (CPU.GPR[rb]._u32[3] & 0x1f)));
-	}
-	void ROTM(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) < 32 ? CPU.GPR[ra]._u32[0] >> ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) : 0;
-		CPU.GPR[rt]._u32[1] = ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) < 32 ? CPU.GPR[ra]._u32[1] >> ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) : 0;
-		CPU.GPR[rt]._u32[2] = ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) < 32 ? CPU.GPR[ra]._u32[2] >> ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) : 0;
-		CPU.GPR[rt]._u32[3] = ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) < 32 ? CPU.GPR[ra]._u32[3] >> ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) : 0;
-	}
-	void ROTMA(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._s32[0] = ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[0] >> ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) : CPU.GPR[ra]._s32[0] >> 31;
-		CPU.GPR[rt]._s32[1] = ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[1] >> ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) : CPU.GPR[ra]._s32[1] >> 31;
-		CPU.GPR[rt]._s32[2] = ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[2] >> ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) : CPU.GPR[ra]._s32[2] >> 31;
-		CPU.GPR[rt]._s32[3] = ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[3] >> ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) : CPU.GPR[ra]._s32[3] >> 31;
-	}
-	void SHL(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = (CPU.GPR[rb]._u32[0] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[0] << (CPU.GPR[rb]._u32[0] & 0x3f);
-		CPU.GPR[rt]._u32[1] = (CPU.GPR[rb]._u32[1] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[1] << (CPU.GPR[rb]._u32[1] & 0x3f);
-		CPU.GPR[rt]._u32[2] = (CPU.GPR[rb]._u32[2] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[2] << (CPU.GPR[rb]._u32[2] & 0x3f);
-		CPU.GPR[rt]._u32[3] = (CPU.GPR[rb]._u32[3] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[3] << (CPU.GPR[rb]._u32[3] & 0x3f);
-	}
-	void ROTH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++) 
-			CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._u16[h] << (CPU.GPR[rb]._u16[h] & 0xf)) | (CPU.GPR[ra]._u16[h] >> (16 - (CPU.GPR[rb]._u16[h] & 0xf)));
-	}
-	void ROTHM(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) < 16 ? CPU.GPR[ra]._u16[h] >> ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) : 0;
-	}
-	void ROTMAH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) < 16 ? CPU.GPR[ra]._s16[h] >> ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) : CPU.GPR[ra]._s16[h] >> 15;
-	}
-	void SHLH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = (CPU.GPR[rb]._u16[h] & 0x1f) > 15 ? 0 : CPU.GPR[ra]._u16[h] << (CPU.GPR[rb]._u16[h] & 0x1f);
-	}
-	void ROTI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = i7 & 0x1f;
-		CPU.GPR[rt]._u32[0] = (CPU.GPR[ra]._u32[0] << nRot) | (CPU.GPR[ra]._u32[0] >> (32 - nRot));
-		CPU.GPR[rt]._u32[1] = (CPU.GPR[ra]._u32[1] << nRot) | (CPU.GPR[ra]._u32[1] >> (32 - nRot));
-		CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << nRot) | (CPU.GPR[ra]._u32[2] >> (32 - nRot));
-		CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] << nRot) | (CPU.GPR[ra]._u32[3] >> (32 - nRot));
-	}
-	void ROTMI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = (0 - i7) & 0x3f;
-		CPU.GPR[rt]._u32[0] = nRot < 32 ? CPU.GPR[ra]._u32[0] >> nRot : 0;
-		CPU.GPR[rt]._u32[1] = nRot < 32 ? CPU.GPR[ra]._u32[1] >> nRot : 0;
-		CPU.GPR[rt]._u32[2] = nRot < 32 ? CPU.GPR[ra]._u32[2] >> nRot : 0;
-		CPU.GPR[rt]._u32[3] = nRot < 32 ? CPU.GPR[ra]._u32[3] >> nRot : 0;
-	}
-	void ROTMAI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = (0 - i7) & 0x3f;
-		CPU.GPR[rt]._s32[0] = nRot < 32 ? CPU.GPR[ra]._s32[0] >> nRot : CPU.GPR[ra]._s32[0] >> 31;
-		CPU.GPR[rt]._s32[1] = nRot < 32 ? CPU.GPR[ra]._s32[1] >> nRot : CPU.GPR[ra]._s32[1] >> 31;
-		CPU.GPR[rt]._s32[2] = nRot < 32 ? CPU.GPR[ra]._s32[2] >> nRot : CPU.GPR[ra]._s32[2] >> 31;
-		CPU.GPR[rt]._s32[3] = nRot < 32 ? CPU.GPR[ra]._s32[3] >> nRot : CPU.GPR[ra]._s32[3] >> 31;
-	}
-	void SHLI(u32 rt, u32 ra, s32 i7)
-	{
-		const u32 s = i7 & 0x3f;
-
-		for (u32 j = 0; j < 4; ++j)
-			CPU.GPR[rt]._u32[j] = (s >= 32) ? 0 : CPU.GPR[ra]._u32[j] << s;
-	}
-	void ROTHI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = i7 & 0xf;
-
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._u16[h] << nRot) | (CPU.GPR[ra]._u16[h] >> (16 - nRot));
-	}
-	void ROTHMI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = (0 - i7) & 0x1f;
-
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = nRot < 16 ? CPU.GPR[ra]._u16[h] >> nRot : 0;
-	}
-	void ROTMAHI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = (0 - i7) & 0x1f;
-
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = nRot < 16 ? CPU.GPR[ra]._s16[h] >> nRot : CPU.GPR[ra]._s16[h] >> 15;
-	}
-	void SHLHI(u32 rt, u32 ra, s32 i7)
-	{
-		const int nRot = i7 & 0x1f;
-
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = nRot > 15 ? 0 : CPU.GPR[ra]._u16[h] << nRot;
-	}
-	void A(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0];
-		CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] + CPU.GPR[rb]._u32[1];
-		CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] + CPU.GPR[rb]._u32[2];
-		CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3];
-	}
-	void AND(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] & CPU.GPR[rb]._u32[0];
-		CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] & CPU.GPR[rb]._u32[1];
-		CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] & CPU.GPR[rb]._u32[2];
-		CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] & CPU.GPR[rb]._u32[3];
-	}
-	void CG(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = ((CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0]) < CPU.GPR[ra]._u32[0]) ? 1 : 0;
-		CPU.GPR[rt]._u32[1] = ((CPU.GPR[ra]._u32[1] + CPU.GPR[rb]._u32[1]) < CPU.GPR[ra]._u32[1]) ? 1 : 0;
-		CPU.GPR[rt]._u32[2] = ((CPU.GPR[ra]._u32[2] + CPU.GPR[rb]._u32[2]) < CPU.GPR[ra]._u32[2]) ? 1 : 0;
-		CPU.GPR[rt]._u32[3] = ((CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) < CPU.GPR[ra]._u32[3]) ? 1 : 0;
-	}
-	void AH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] + CPU.GPR[rb]._u16[h];
-	}
-	void NAND(u32 rt, u32 ra, u32 rb)
-	{
-		CPU.GPR[rt]._u32[0] = ~(CPU.GPR[ra]._u32[0] & CPU.GPR[rb]._u32[0]);
-		CPU.GPR[rt]._u32[1] = ~(CPU.GPR[ra]._u32[1] & CPU.GPR[rb]._u32[1]);
-		CPU.GPR[rt]._u32[2] = ~(CPU.GPR[ra]._u32[2] & CPU.GPR[rb]._u32[2]);
-		CPU.GPR[rt]._u32[3] = ~(CPU.GPR[ra]._u32[3] & CPU.GPR[rb]._u32[3]);
-	}
-	void AVGB(u32 rt, u32 ra, u32 rb)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = (CPU.GPR[ra]._u8[b] + CPU.GPR[rb]._u8[b] + 1) >> 1;
-	}
-	void MTSPR(u32 rt, u32 sa)
-	{
-		// SPR writes are ignored.
-	}
-	void WRCH(u32 ra, u32 rt)
-	{
-		CPU.set_ch_value(ra, CPU.GPR[rt]._u32[3]);
-	}
-	void BIZ(u32 intr, u32 rt, u32 ra)
-	{
-		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
-		if (CPU.GPR[rt]._u32[3] == 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-
-			switch (intr & 0x30)
-			{
-			case 0: break;
-			case 0x10: CPU.set_interrupt_status(true);
-			case 0x20: CPU.set_interrupt_status(false);
-			default: UNIMPLEMENTED(); return;
-			}
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void BINZ(u32 intr, u32 rt, u32 ra)
-	{
-		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
-		if (CPU.GPR[rt]._u32[3] != 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-
-			switch (intr & 0x30)
-			{
-			case 0: break;
-			case 0x10: CPU.set_interrupt_status(true);
-			case 0x20: CPU.set_interrupt_status(false);
-			default: UNIMPLEMENTED(); return;
-			}
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void BIHZ(u32 intr, u32 rt, u32 ra)
-	{
-		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
-		if (CPU.GPR[rt]._u16[6] == 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-
-			switch (intr & 0x30)
-			{
-			case 0: break;
-			case 0x10: CPU.set_interrupt_status(true);
-			case 0x20: CPU.set_interrupt_status(false);
-			default: UNIMPLEMENTED(); return;
-			}
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void BIHNZ(u32 intr, u32 rt, u32 ra)
-	{
-		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
-		if (CPU.GPR[rt]._u16[6] != 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-
-			switch (intr & 0x30)
-			{
-			case 0: break;
-			case 0x10: CPU.set_interrupt_status(true);
-			case 0x20: CPU.set_interrupt_status(false);
-			default: UNIMPLEMENTED(); return;
-			}
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void STOPD(u32 rc, u32 ra, u32 rb)
-	{
-		UNIMPLEMENTED(); // not used
-	}
-	void STQX(u32 rt, u32 ra, u32 rb)
-	{
-		u32 lsa = (CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) & 0x3fff0;
-
-		CPU.write128(lsa, CPU.GPR[rt]);
-	}
-	void BI(u32 intr, u32 ra)
-	{
-		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
-		LOG5_OPCODE("branch (0x%x)", target);
-		CPU.PC = target - 4;
-
-		switch (intr & 0x30)
-		{
-		case 0: break;
-		case 0x10: CPU.set_interrupt_status(true);
-		case 0x20: CPU.set_interrupt_status(false);
-		default: UNIMPLEMENTED(); return;
-		}
-	}
-	void BISL(u32 intr, u32 rt, u32 ra)
-	{
-		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
-		CPU.GPR[rt] = v128::from32r(CPU.PC + 4);
-		LOG5_OPCODE("branch (0x%x)", target);
-		CPU.PC = target - 4;
-
-		switch (intr & 0x30)
-		{
-		case 0: break;
-		case 0x10: CPU.set_interrupt_status(true);
-		case 0x20: CPU.set_interrupt_status(false);
-		default: UNIMPLEMENTED(); return;
-		}
-	}
-	void IRET(u32 ra)
-	{
-		UNIMPLEMENTED(); // not used
-	}
-	void BISLED(u32 intr, u32 rt, u32 ra)
-	{
-		UNIMPLEMENTED(); // not used
-	}
-	void HBR(u32 p, u32 ro, u32 ra)
-	{
-	}
-	void GB(u32 rt, u32 ra)
-	{
-		CPU.GPR[rt]._u32[3] =	(CPU.GPR[ra]._u32[0] & 1) |
-										((CPU.GPR[ra]._u32[1] & 1) << 1) |
-										((CPU.GPR[ra]._u32[2] & 1) << 2) |
-										((CPU.GPR[ra]._u32[3] & 1) << 3);
-		CPU.GPR[rt]._u32[2] = 0;
-		CPU.GPR[rt]._u64[0] = 0;
-	}
-	void GBH(u32 rt, u32 ra)
-	{
-		u32 temp = 0;
-		for (int h = 0; h < 8; h++)
-			temp |= (CPU.GPR[ra]._u16[h] & 1) << h;
-		CPU.GPR[rt]._u32[3] = temp;
-		CPU.GPR[rt]._u32[2] = 0;
-		CPU.GPR[rt]._u64[0] = 0;
-	}
-	void GBB(u32 rt, u32 ra)
-	{
-		u32 temp = 0;
-		for (int b = 0; b < 16; b++)
-			temp |= (CPU.GPR[ra]._u8[b] & 1) << b;
-		CPU.GPR[rt]._u32[3] = temp;
-		CPU.GPR[rt]._u32[2] = 0;
-		CPU.GPR[rt]._u64[0] = 0;
-	}
-	void FSM(u32 rt, u32 ra)
-	{
-		const u32 pref = CPU.GPR[ra]._u32[3];
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = (pref & (1 << w)) ? ~0 : 0;
-	}
-	void FSMH(u32 rt, u32 ra)
-	{
-		const u32 pref = CPU.GPR[ra]._u32[3];
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = (pref & (1 << h)) ? ~0 : 0;
-	}
-	void FSMB(u32 rt, u32 ra)
-	{
-		const u32 pref = CPU.GPR[ra]._u32[3];
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = (pref & (1 << b)) ? ~0 : 0;
-	}
-	void FREST(u32 rt, u32 ra)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		for (int i = 0; i < 4; i++)
-		{
-			const float a = CPU.GPR[ra]._f[i];
-			float result;
-			if (fexpf(a) == 0)
-			{
-				CPU.FPSCR.setDivideByZeroFlag(i);
-				result = extended(std::signbit(a), 0x7FFFFF);
-			}
-			else if (isextended(a))
-				result = 0.0f;
-			else
-				result = 1 / a;
-			CPU.GPR[rt]._f[i] = result;
-		}
-	}
-	void FRSQEST(u32 rt, u32 ra)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		for (int i = 0; i < 4; i++)
-		{
-			const float a = CPU.GPR[ra]._f[i];
-			float result;
-			if (fexpf(a) == 0)
-			{
-				CPU.FPSCR.setDivideByZeroFlag(i);
-				result = extended(0, 0x7FFFFF);
-			}
-			else if (isextended(a))
-				result = 0.5f / sqrtf(fabsf(ldexpf_extended(a, -2)));
-			else
-				result = 1 / sqrtf(fabsf(a));
-			CPU.GPR[rt]._f[i] = result;
-		}
-	}
-	void LQX(u32 rt, u32 ra, u32 rb)
-	{
-		u32 lsa = (CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) & 0x3fff0;
-
-		CPU.GPR[rt] = CPU.read128(lsa);
-	}
-	void ROTQBYBI(u32 rt, u32 ra, u32 rb)
-	{
-		const int s = (CPU.GPR[rb]._u32[3] >> 3) & 0xf;
-		const v128 temp = CPU.GPR[ra];
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
-	}
-	void ROTQMBYBI(u32 rt, u32 ra, u32 rb)
-	{
-		const int s = (0 - (CPU.GPR[rb]._u32[3] >> 3)) & 0x1f;
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = 0; b < 16 - s; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[b + s];
-	}
-	void SHLQBYBI(u32 rt, u32 ra, u32 rb)
-	{
-		const int s = (CPU.GPR[rb]._u32[3] >> 3) & 0x1f;
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = s; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[b - s];
-	}
-	void CBX(u32 rt, u32 ra, u32 rb)
-	{
-		const u32 t = (CPU.GPR[rb]._u32[3] + CPU.GPR[ra]._u32[3]) & 0xF;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u8[15 - t] = 0x03;
-	}
-	void CHX(u32 rt, u32 ra, u32 rb)
-	{
-		const u32 t = (CPU.GPR[rb]._u32[3] + CPU.GPR[ra]._u32[3]) & 0xE;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u16[7 - (t >> 1)] = 0x0203;
-	}
-	void CWX(u32 rt, u32 ra, u32 rb)
-	{
-		const u32 t = (CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) & 0xC;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-		
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u32[3 - (t >> 2)] = 0x00010203;
-	}
-	void CDX(u32 rt, u32 ra, u32 rb)
-	{
-		const u32 t = (CPU.GPR[rb]._u32[3] + CPU.GPR[ra]._u32[3]) & 0x8;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u64[1 - (t >> 3)] = (u64)0x0001020304050607;
-	}
-	void ROTQBI(u32 rt, u32 ra, u32 rb)
-	{
-		const int t = CPU.GPR[rb]._u32[3] & 0x7;
-		if (t) // not an optimization, it fixes shifts
-		{
-			const v128 temp = CPU.GPR[ra];
-			CPU.GPR[rt]._u32[0] = (temp._u32[0] << t) | (temp._u32[3] >> (32 - t));
-			CPU.GPR[rt]._u32[1] = (temp._u32[1] << t) | (temp._u32[0] >> (32 - t));
-			CPU.GPR[rt]._u32[2] = (temp._u32[2] << t) | (temp._u32[1] >> (32 - t));
-			CPU.GPR[rt]._u32[3] = (temp._u32[3] << t) | (temp._u32[2] >> (32 - t));
-		}
-		else
-		{
-			CPU.GPR[rt] = CPU.GPR[ra];
-		}
-	}
-	void ROTQMBI(u32 rt, u32 ra, u32 rb)
-	{
-		const int t = (0 - CPU.GPR[rb]._u32[3]) & 0x7;
-		if (t) // not an optimization, it fixes shifts
-		{
-			const v128 temp = CPU.GPR[ra];
-			CPU.GPR[rt]._u32[0] = (temp._u32[0] >> t) | (temp._u32[1] << (32 - t));
-			CPU.GPR[rt]._u32[1] = (temp._u32[1] >> t) | (temp._u32[2] << (32 - t));
-			CPU.GPR[rt]._u32[2] = (temp._u32[2] >> t) | (temp._u32[3] << (32 - t));
-			CPU.GPR[rt]._u32[3] = (temp._u32[3] >> t);
-		}
-		else
-		{
-			CPU.GPR[rt] = CPU.GPR[ra];
-		}
-	}
-	void SHLQBI(u32 rt, u32 ra, u32 rb)
-	{
-		const int t = CPU.GPR[rb]._u32[3] & 0x7;
-		if (t) // not an optimization, it fixes shifts
-		{
-			const v128 temp = CPU.GPR[ra];
-			CPU.GPR[rt]._u32[0] = (temp._u32[0] << t);
-			CPU.GPR[rt]._u32[1] = (temp._u32[1] << t) | (temp._u32[0] >> (32 - t));
-			CPU.GPR[rt]._u32[2] = (temp._u32[2] << t) | (temp._u32[1] >> (32 - t));
-			CPU.GPR[rt]._u32[3] = (temp._u32[3] << t) | (temp._u32[2] >> (32 - t));
-		}
-		else
-		{
-			CPU.GPR[rt] = CPU.GPR[ra];
-		}
-	}
-	void ROTQBY(u32 rt, u32 ra, u32 rb)
-	{
-		const int s = CPU.GPR[rb]._u32[3] & 0xf;
-		const v128 temp = CPU.GPR[ra];
-		for (int b = 0; b < 16; ++b)
-			CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
-	}
-	void ROTQMBY(u32 rt, u32 ra, u32 rb)
-	{
-		const int s = (0 - CPU.GPR[rb]._u32[3]) & 0x1f;
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = 0; b < 16 - s; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[b + s];
-	}
-	void SHLQBY(u32 rt, u32 ra, u32 rb)
-	{
-		const int s = CPU.GPR[rb]._u32[3] & 0x1f;
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = s; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[b - s];
-	}
-	void ORX(u32 rt, u32 ra)
-	{
-		CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[0] | CPU.GPR[ra]._u32[1] | CPU.GPR[ra]._u32[2] | CPU.GPR[ra]._u32[3];
-		CPU.GPR[rt]._u32[2] = 0;
-		CPU.GPR[rt]._u64[0] = 0;
-	}
-	void CBD(u32 rt, u32 ra, s32 i7)
-	{
-		const int t = (CPU.GPR[ra]._u32[3] + i7) & 0xF;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u8[15 - t] = 0x03;
-	}
-	void CHD(u32 rt, u32 ra, s32 i7)
-	{
-		const int t = (CPU.GPR[ra]._u32[3] + i7) & 0xE;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u16[7 - (t >> 1)] = 0x0203;
-	}
-	void CWD(u32 rt, u32 ra, s32 i7)
-	{
-		const int t = (CPU.GPR[ra]._u32[3] + i7) & 0xC;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u32[3 - (t >> 2)] = 0x00010203;
-	}
-	void CDD(u32 rt, u32 ra, s32 i7)
-	{
-		const int t = (CPU.GPR[ra]._u32[3] + i7) & 0x8;
-
-		if (ra == 1 && (CPU.GPR[ra]._u32[3] & 0xF))
-		{
-			LOG_ERROR(SPU, "%s(): SP = 0x%x", __FUNCTION__, CPU.GPR[ra]._u32[3]);
-			Emu.Pause();
-		}
-
-		CPU.GPR[rt]._u64[0] = (u64)0x18191A1B1C1D1E1F;
-		CPU.GPR[rt]._u64[1] = (u64)0x1011121314151617;
-		CPU.GPR[rt]._u64[1 - (t >> 3)] = (u64)0x0001020304050607;
-	}
-	void ROTQBII(u32 rt, u32 ra, s32 i7)
-	{
-		const int s = i7 & 0x7;
-		if (s) // not an optimization, it fixes shifts
-		{
-			const v128 temp = CPU.GPR[ra];
-			CPU.GPR[rt]._u32[0] = (temp._u32[0] << s) | (temp._u32[3] >> (32 - s));
-			CPU.GPR[rt]._u32[1] = (temp._u32[1] << s) | (temp._u32[0] >> (32 - s));
-			CPU.GPR[rt]._u32[2] = (temp._u32[2] << s) | (temp._u32[1] >> (32 - s));
-			CPU.GPR[rt]._u32[3] = (temp._u32[3] << s) | (temp._u32[2] >> (32 - s));
-		}
-		else
-		{
-			CPU.GPR[rt] = CPU.GPR[ra];
-		}
-	}
-	void ROTQMBII(u32 rt, u32 ra, s32 i7)
-	{
-		const int s = (0 - i7) & 0x7;
-		if (s) // not an optimization, it fixes shifts
-		{
-			const v128 temp = CPU.GPR[ra];
-			CPU.GPR[rt]._u32[0] = (temp._u32[0] >> s) | (temp._u32[1] << (32 - s));
-			CPU.GPR[rt]._u32[1] = (temp._u32[1] >> s) | (temp._u32[2] << (32 - s));
-			CPU.GPR[rt]._u32[2] = (temp._u32[2] >> s) | (temp._u32[3] << (32 - s));
-			CPU.GPR[rt]._u32[3] = (temp._u32[3] >> s);
-		}
-		else
-		{
-			CPU.GPR[rt] = CPU.GPR[ra];
-		}
-	}
-	void SHLQBII(u32 rt, u32 ra, s32 i7)
-	{
-		const int s = i7 & 0x7;
-		if (s) // not an optimization, it fixes shifts
-		{
-			const v128 temp = CPU.GPR[ra];
-			CPU.GPR[rt]._u32[0] = (temp._u32[0] << s);
-			CPU.GPR[rt]._u32[1] = (temp._u32[1] << s) | (temp._u32[0] >> (32 - s));
-			CPU.GPR[rt]._u32[2] = (temp._u32[2] << s) | (temp._u32[1] >> (32 - s));
-			CPU.GPR[rt]._u32[3] = (temp._u32[3] << s) | (temp._u32[2] >> (32 - s));
-		}
-		else
-		{
-			CPU.GPR[rt] = CPU.GPR[ra];
-		}
-	}
-	void ROTQBYI(u32 rt, u32 ra, s32 i7)
-	{
-		const int s = i7 & 0xf;
-		const v128 temp = CPU.GPR[ra];
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
-	}
-	void ROTQMBYI(u32 rt, u32 ra, s32 i7)
-	{
-		const int s = (0 - i7) & 0x1f;
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = 0; b < 16 - s; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[b + s];
-	}
-	void SHLQBYI(u32 rt, u32 ra, s32 i7)
-	{
-		const int s = i7 & 0x1f;
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = s; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = temp._u8[b - s];
-	}
-	void NOP(u32 rt)
-	{
-	}
-	void CGT(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] > CPU.GPR[rb]._s32[w] ? 0xffffffff : 0;
-	}
-	void XOR(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] ^ CPU.GPR[rb]._u32[w];
-	}
-	void CGTH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._s16[h] > CPU.GPR[rb]._s16[h] ? 0xffff : 0;
-	}
-	void EQV(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] ^ (~CPU.GPR[rb]._u32[w]);
-	}
-	void CGTB(u32 rt, u32 ra, u32 rb)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._s8[b] > CPU.GPR[rb]._s8[b] ? 0xff : 0;
-	}
-	void SUMB(u32 rt, u32 ra, u32 rb)
-	{
-		const v128 _a = CPU.GPR[ra];
-		const v128 _b = CPU.GPR[rb];
-		for (int w = 0; w < 4; w++)
-		{
-			CPU.GPR[rt]._u16[w*2] = _a._u8[w*4] + _a._u8[w*4 + 1] + _a._u8[w*4 + 2] + _a._u8[w*4 + 3];
-			CPU.GPR[rt]._u16[w*2 + 1] = _b._u8[w*4] + _b._u8[w*4 + 1] + _b._u8[w*4 + 2] + _b._u8[w*4 + 3];
-		}
-	}
-	//HGT uses signed values.  HLGT uses unsigned values
-	void HGT(u32 rt, s32 ra, s32 rb)
-	{
-		if (CPU.GPR[ra]._s32[3] > CPU.GPR[rb]._s32[3])
-		{
-			CPU.halt();
-		}
-	}
-	void CLZ(u32 rt, u32 ra)
-	{
-		for (int w = 0; w < 4; w++)
-		{
-			int nPos;
-
-			for (nPos = 0; nPos < 32; nPos++)
-				if (CPU.GPR[ra]._u32[w] & (1 << (31 - nPos)))
-					break;
-
-			CPU.GPR[rt]._u32[w] = nPos;
-		}
-	}
-	void XSWD(u32 rt, u32 ra)
-	{
-		CPU.GPR[rt]._s64[0] = (s64)CPU.GPR[ra]._s32[0];
-		CPU.GPR[rt]._s64[1] = (s64)CPU.GPR[ra]._s32[2];
-	}
-	void XSHW(u32 rt, u32 ra)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = (s32)CPU.GPR[ra]._s16[w*2];
-	}
-	void CNTB(u32 rt, u32 ra)
-	{
-		const v128 temp = CPU.GPR[ra];
-		CPU.GPR[rt].clear();
-		for (int b = 0; b < 16; b++)
-			for (int i = 0; i < 8; i++)
-				CPU.GPR[rt]._u8[b] += (temp._u8[b] & (1 << i)) ? 1 : 0;
-	}
-	void XSBH(u32 rt, u32 ra)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = (s16)CPU.GPR[ra]._s8[h*2];
-	}
-	void CLGT(u32 rt, u32 ra, u32 rb)
-	{
-		for(u32 i = 0; i < 4; ++i)
-		{
-			CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._u32[i] > CPU.GPR[rb]._u32[i]) ? 0xffffffff : 0x00000000;
-		}
-	}
-	void ANDC(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] & (~CPU.GPR[rb]._u32[w]);
-	}
-	void FCGT(u32 rt, u32 ra, u32 rb)
-	{
-		for (int i = 0; i < 4; i++)
-		{
-			const u32 a = CPU.GPR[ra]._u32[i];
-			const u32 b = CPU.GPR[rb]._u32[i];
-			const u32 abs_a = a & 0x7FFFFFFF;
-			const u32 abs_b = b & 0x7FFFFFFF;
-			const bool a_zero = (abs_a < 0x00800000);
-			const bool b_zero = (abs_b < 0x00800000);
-			bool pass;
-			if (a_zero)
-				pass = b >= 0x80800000;
-			else if (b_zero)
-				pass = (s32)a >= 0x00800000;
-			else if (a >= 0x80000000)
-				pass = (b >= 0x80000000 && a < b);
-			else
-				pass = (b >= 0x80000000 || a > b);
-			CPU.GPR[rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
-		}
-	}
-	void DFCGT(u32 rt, u32 ra, u32 rb)
-	{
-		UNIMPLEMENTED(); // cannot be used
-	}
-	void FA_FS(u32 rt, u32 ra, u32 rb, bool sub)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		for (int w = 0; w < 4; w++)
-		{
-			const float a = CPU.GPR[ra]._f[w];
-			const float b = sub ? -CPU.GPR[rb]._f[w] : CPU.GPR[rb]._f[w];
-			float result;
-			if (isdenormal(a))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				if (b == 0.0f || isdenormal(b))
-					result = +0.0f;
-				else
-					result = b;
-			}
-			else if (isdenormal(b))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				if (a == 0.0f)
-					result = +0.0f;
-				else
-					result = a;
-			}
-			else if (isextended(a) || isextended(b))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				if (isextended(a) && fexpf(b) < 255-32)
-				{
-					if (std::signbit(a) != std::signbit(b))
-					{
-						const u32 bits = (u32&)a - 1;
-						result = (float&)bits;
-					}
-					else
-
-						result = a;
-				}
-				else if (isextended(b) && fexpf(a) < 255-32)
-				{
-					if (std::signbit(a) != std::signbit(b))
-					{
-						const u32 bits = (u32&)b - 1;
-						result = (float&)bits;
-					}
-					else
-						result = b;
-				}
-				else
-				{
-					feclearexcept(FE_ALL_EXCEPT);
-					result = ldexpf_extended(a, -1) + ldexpf_extended(b, -1);
-					result = ldexpf_extended(result, 1);
-					if (fetestexcept(FE_OVERFLOW))
-					{
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-						result = extended(std::signbit(result), 0x7FFFFF);
-					}
-				}
-			}
-			else
-			{
-				result = a + b;
-				if (result == copysignf(FLOAT_MAX_NORMAL, result))
-				{
-					result = ldexpf_extended(ldexpf(a,-1) + ldexpf(b,-1), 1);
-					if (isextended(result))
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				}
-				else if (isdenormal(result))
-				{
-					CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
-					result = +0.0f;
-				}
-				else if (result == 0.0f)
-				{
-					if (fabsf(a) != fabsf(b))
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
-					result = +0.0f;
-				}
-			}
-			CPU.GPR[rt]._f[w] = result;
-		}
-	}
-	void FA(u32 rt, u32 ra, u32 rb) {FA_FS(rt, ra, rb, false);}
-	void FS(u32 rt, u32 ra, u32 rb) {FA_FS(rt, ra, rb, true);}
-	void FM(u32 rt, u32 ra, u32 rb)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		for (int w = 0; w < 4; w++)
-		{
-			const float a = CPU.GPR[ra]._f[w];
-			const float b = CPU.GPR[rb]._f[w];
-			float result;
-			if (isdenormal(a) || isdenormal(b))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				result = +0.0f;
-			}
-			else if (isextended(a) || isextended(b))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				const bool sign = std::signbit(a) ^ std::signbit(b);
-				if (a == 0.0f || b == 0.0f)
-				{
-					result = +0.0f;
-				}
-				else if ((fexpf(a)-127) + (fexpf(b)-127) >= 129)
-				{
-					CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-					result = extended(sign, 0x7FFFFF);
-				}
-				else
-				{
-					if (isextended(a))
-						result = ldexpf_extended(a, -1) * b;
-					else
-						result = a * ldexpf_extended(b, -1);
-					if (result == copysignf(FLOAT_MAX_NORMAL, result))
-					{
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-						result = extended(sign, 0x7FFFFF);
-					}
-					else
-						result = ldexpf_extended(result, 1);
-				}
-			}
-			else
-			{
-				result = a * b;
-				if (result == copysignf(FLOAT_MAX_NORMAL, result))
-				{
-					feclearexcept(FE_ALL_EXCEPT);
-					if (fexpf(a) > fexpf(b))
-						result = ldexpf(a, -1) * b;
-					else
-						result = a * ldexpf(b, -1);
-					result = ldexpf_extended(result, 1);
-					if (isextended(result))
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-					if (fetestexcept(FE_OVERFLOW))
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-				}
-				else if (isdenormal(result))
-				{
-					CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
-					result = +0.0f;
-				}
-				else if (result == 0.0f)
-				{
-					if (a != 0.0f && b != 0.0f)
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
-					result = +0.0f;
-				}
-			}
-			CPU.GPR[rt]._f[w] = result;
-		}
-	}
-	void CLGTH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] > CPU.GPR[rb]._u16[h] ? 0xffff : 0;
-	}
-	void ORC(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] | (~CPU.GPR[rb]._u32[w]);
-	}
-	void FCMGT(u32 rt, u32 ra, u32 rb)
-	{
-		for (int i = 0; i < 4; i++)
-		{
-			const u32 a = CPU.GPR[ra]._u32[i];
-			const u32 b = CPU.GPR[rb]._u32[i];
-			const u32 abs_a = a & 0x7FFFFFFF;
-			const u32 abs_b = b & 0x7FFFFFFF;
-			const bool a_zero = (abs_a < 0x00800000);
-			const bool b_zero = (abs_b < 0x00800000);
-			bool pass;
-			if (a_zero)
-				pass = false;
-			else if (b_zero)
-				pass = !a_zero;
-			else
-				pass = abs_a > abs_b;
-			CPU.GPR[rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
-		}
-	}
-	void DFCMGT(u32 rt, u32 ra, u32 rb)
-	{
-		UNIMPLEMENTED(); // cannot be used
-	}
-	enum DoubleOp {DFASM_A, DFASM_S, DFASM_M};
-	void DFASM(u32 rt, u32 ra, u32 rb, DoubleOp op)
-	{
-		for (int i = 0; i < 2; i++)
-		{
-			double a = CPU.GPR[ra]._d[i];
-			double b = CPU.GPR[rb]._d[i];
-			if (isdenormal(a))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
-				a = copysign(0.0, a);
-			}
-			if (isdenormal(b))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
-				b = copysign(0.0, b);
-			}
-			double result;
-			if (isnan(a) || isnan(b))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
-				if (issnan(a) || issnan(b))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
-				result = DOUBLE_NAN;
-			}
-			else
-			{
-				SetHostRoundingMode(CPU.FPSCR.checkSliceRounding(i));
-				feclearexcept(FE_ALL_EXCEPT);
-				switch (op)
-				{
-				case DFASM_A: result = a + b; break;
-				case DFASM_S: result = a - b; break;
-				case DFASM_M: result = a * b; break;
-				}
-				if (fetestexcept(FE_INVALID))
-				{
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
-					result = DOUBLE_NAN;
-				}
-				else
-				{
-					if (fetestexcept(FE_OVERFLOW))
-						CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DOVF);
-					if (fetestexcept(FE_UNDERFLOW))
-						CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DUNF);
-					if (fetestexcept(FE_INEXACT))
-						CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINX);
-				}
-			}
-			CPU.GPR[rt]._d[i] = result;
-		}
-	}
-	void DFA(u32 rt, u32 ra, u32 rb) {DFASM(rt, ra, rb, DFASM_A);}
-	void DFS(u32 rt, u32 ra, u32 rb) {DFASM(rt, ra, rb, DFASM_S);}
-	void DFM(u32 rt, u32 ra, u32 rb) {DFASM(rt, ra, rb, DFASM_M);}
-	void CLGTB(u32 rt, u32 ra, u32 rb)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] > CPU.GPR[rb]._u8[b] ? 0xff : 0;
-	}
-	void HLGT(u32 rt, u32 ra, u32 rb)
-	{
-		if (CPU.GPR[ra]._u32[3] > CPU.GPR[rb]._u32[3])
-		{
-			CPU.halt();
-		}
-	}
-	void DFMA(u32 rt, u32 ra, u32 rb, bool neg, bool sub)
-	{
-		for (int i = 0; i < 2; i++)
-		{
-			double a = CPU.GPR[ra]._d[i];
-			double b = CPU.GPR[rb]._d[i];
-			double c = CPU.GPR[rt]._d[i];
-			if (isdenormal(a))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
-				a = copysign(0.0, a);
-			}
-			if (isdenormal(b))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
-				b = copysign(0.0, b);
-			}
-			if (isdenormal(c))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
-				c = copysign(0.0, c);
-			}
-			double result;
-			if (isnan(a) || isnan(b) || isnan(c))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
-				if (issnan(a) || issnan(b) || issnan(c) || (isinf(a) && b == 0.0f) || (a == 0.0f && isinf(b)))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
-				result = DOUBLE_NAN;
-			}
-			else
-			{
-				SetHostRoundingMode(CPU.FPSCR.checkSliceRounding(i));
-				feclearexcept(FE_ALL_EXCEPT);
-				result = fma(a, b, sub ? -c : c);
-				if (fetestexcept(FE_INVALID))
-				{
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
-					result = DOUBLE_NAN;
-				}
-				else
-				{
-					if (fetestexcept(FE_OVERFLOW))
-						CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DOVF);
-					if (fetestexcept(FE_UNDERFLOW))
-						CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DUNF);
-					if (fetestexcept(FE_INEXACT))
-						CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINX);
-					if (neg) result = -result;
-				}
-			}
-			CPU.GPR[rt]._d[i] = result;
-		}
-	}
-	void DFMA(u32 rt, u32 ra, u32 rb) {DFMA(rt, ra, rb, false, false);}
-	void DFMS(u32 rt, u32 ra, u32 rb) {DFMA(rt, ra, rb, false, true);}
-	void DFNMS(u32 rt, u32 ra, u32 rb) {DFMA(rt, ra, rb, true, true);}
-	void DFNMA(u32 rt, u32 ra, u32 rb) {DFMA(rt, ra, rb, true, false);}
-	void CEQ(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] == CPU.GPR[rb]._s32[w] ? 0xffffffff : 0;
-	}
-	void MPYHHU(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2+1] * CPU.GPR[rb]._u16[w*2+1];
-	}
-	void ADDX(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] + CPU.GPR[rb]._u32[w] + (CPU.GPR[rt]._u32[w] & 1);
-	}
-	void SFX(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[rb]._u32[w] - CPU.GPR[ra]._u32[w] - (1 - (CPU.GPR[rt]._u32[w] & 1));
-	}
-	void CGX(u32 rt, u32 ra, u32 rb)
-	{
-		// rarely used
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = ((u64)CPU.GPR[ra]._u32[w] + (u64)CPU.GPR[rb]._u32[w] + (u64)(CPU.GPR[rt]._u32[w] & 1)) >> 32;
-	}
-	void BGX(u32 rt, u32 ra, u32 rb)
-	{
-		// rarely used
-		s64 nResult;
-		
-		for (int w = 0; w < 4; w++)
-		{
-			nResult = (u64)CPU.GPR[rb]._u32[w] - (u64)CPU.GPR[ra]._u32[w] - (u64)(1 - (CPU.GPR[rt]._u32[w] & 1));
-			CPU.GPR[rt]._u32[w] = nResult < 0 ? 0 : 1;
-		}
-	}
-	void MPYHHA(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] += CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2+1];
-	}
-	void MPYHHAU(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] += CPU.GPR[ra]._u16[w*2+1] * CPU.GPR[rb]._u16[w*2+1];
-	}
-	//Forced bits to 0, hence the shift:
-	
-	void FSCRRD(u32 rt)
-	{
-		CPU.FPSCR.Read(CPU.GPR[rt]);
-	}
-	void FESD(u32 rt, u32 ra)
-	{
-		for (int i = 0; i < 2; i++)
-		{
-			const float a = CPU.GPR[ra]._f[i*2+1];
-			if (isnan(a))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
-				if (issnan(a))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
-				CPU.GPR[rt]._d[i] = DOUBLE_NAN;
-			}
-			else if (isdenormal(a))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DDENORM);
-				CPU.GPR[rt]._d[i] = 0.0;
-			}
-			else
-			{
-				CPU.GPR[rt]._d[i] = (double)a;
-			}
-		}
-	}
-	void FRDS(u32 rt, u32 ra)
-	{
-		for (int i = 0; i < 2; i++)
-		{
-			SetHostRoundingMode(CPU.FPSCR.checkSliceRounding(i));
-			const double a = CPU.GPR[ra]._d[i];
-			if (isnan(a))
-			{
-				CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DNAN);
-				if (issnan(a))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINV);
-				CPU.GPR[rt]._f[i*2+1] = FLOAT_NAN;
-			}
-			else
-			{
-				feclearexcept(FE_ALL_EXCEPT);
-				CPU.GPR[rt]._f[i*2+1] = (float)a;
-				if (fetestexcept(FE_OVERFLOW))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DOVF);
-				if (fetestexcept(FE_UNDERFLOW))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DUNF);
-				if (fetestexcept(FE_INEXACT))
-					CPU.FPSCR.setDoublePrecisionExceptionFlags(i, FPSCR_DINX);
-			}
-			CPU.GPR[rt]._u32[i*2] = 0;
-		}
-	}
-	void FSCRWR(u32 rt, u32 ra)
-	{
-		CPU.FPSCR.Write(CPU.GPR[ra]);
-	}
-	void DFTSV(u32 rt, u32 ra, s32 i7)
-	{
-		UNIMPLEMENTED(); // cannot be used
-	}
-	void FCEQ(u32 rt, u32 ra, u32 rb)
-	{
-		for (int i = 0; i < 4; i++)
-		{
-			const u32 a = CPU.GPR[ra]._u32[i];
-			const u32 b = CPU.GPR[rb]._u32[i];
-			const u32 abs_a = a & 0x7FFFFFFF;
-			const u32 abs_b = b & 0x7FFFFFFF;
-			const bool a_zero = (abs_a < 0x00800000);
-			const bool b_zero = (abs_b < 0x00800000);
-			const bool pass = a == b || (a_zero && b_zero);
-			CPU.GPR[rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
-		}
-	}
-	void DFCEQ(u32 rt, u32 ra, u32 rb)
-	{
-		UNIMPLEMENTED(); // cannot be used
-	}
-	void MPY(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2];
-	}
-	void MPYH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = (CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2]) << 16;
-	}
-	void MPYHH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2+1];
-	}
-	void MPYS(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = (CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2]) >> 16;
-	}
-	void CEQH(u32 rt, u32 ra, u32 rb)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] == CPU.GPR[rb]._u16[h] ? 0xffff : 0;
-	}
-	void FCMEQ(u32 rt, u32 ra, u32 rb)
-	{
-		for (int i = 0; i < 4; i++)
-		{
-			const u32 a = CPU.GPR[ra]._u32[i];
-			const u32 b = CPU.GPR[rb]._u32[i];
-			const u32 abs_a = a & 0x7FFFFFFF;
-			const u32 abs_b = b & 0x7FFFFFFF;
-			const bool a_zero = (abs_a < 0x00800000);
-			const bool b_zero = (abs_b < 0x00800000);
-			const bool pass = abs_a == abs_b || (a_zero && b_zero);
-			CPU.GPR[rt]._u32[i] = pass ? 0xFFFFFFFF : 0;
-		}
-	}
-	void DFCMEQ(u32 rt, u32 ra, u32 rb)
-	{
-		UNIMPLEMENTED(); // cannot be used
-	}
-	void MPYU(u32 rt, u32 ra, u32 rb)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2] * CPU.GPR[rb]._u16[w*2];
-	}
-	void CEQB(u32 rt, u32 ra, u32 rb)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] == CPU.GPR[rb]._u8[b] ? 0xff : 0;
-	}
-	void FI(u32 rt, u32 ra, u32 rb)
-	{
-		// TODO: Floating Interpolation: ra will be ignored.
-		// It should work correctly if result of preceding FREST or FRSQEST is sufficiently exact
-		CPU.GPR[rt] = CPU.GPR[rb];
-	}
-	void HEQ(u32 rt, u32 ra, u32 rb)
-	{
-		if (CPU.GPR[ra]._s32[3] == CPU.GPR[rb]._s32[3])
-		{
-			CPU.halt();
-		}
-	}
-
-	//0 - 9
-	void CFLTS(u32 rt, u32 ra, s32 i8)
-	{
-		const int scale = 173 - (i8 & 0xff); //unsigned immediate
-		for (int i = 0; i < 4; i++)
-		{
-			const float a = CPU.GPR[ra]._f[i];
-			float scaled;
-			if ((fexpf(a)-127) + scale >= 32)
-				scaled = copysignf(4294967296.0f, a);
-			else
-				scaled = ldexpf(a, scale);
-			s32 result;
-			if (scaled >= 2147483648.0f)
-				result = 0x7FFFFFFF;
-			else if (scaled < -2147483648.0f)
-				result = 0x80000000;
-			else
-				result = (s32)scaled;
-			CPU.GPR[rt]._s32[i] = result;
-		}
-	}
-	void CFLTU(u32 rt, u32 ra, s32 i8)
-	{
-		const int scale = 173 - (i8 & 0xff); //unsigned immediate
-		for (int i = 0; i < 4; i++)
-		{
-			const float a = CPU.GPR[ra]._f[i];
-			float scaled;
-			if ((fexpf(a)-127) + scale >= 32)
-				scaled = copysignf(4294967296.0f, a);
-			else
-				scaled = ldexpf(a, scale);
-			u32 result;
-			if (scaled >= 4294967296.0f)
-				result = 0xFFFFFFFF;
-			else if (scaled < 0.0f)
-				result = 0;
-			else
-				result = (u32)scaled;
-			CPU.GPR[rt]._u32[i] = result;
-		}
-	}
-	void CSFLT(u32 rt, u32 ra, s32 i8)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		const int scale = 155 - (i8 & 0xff); //unsigned immediate
-		for (int i = 0; i < 4; i++)
-		{
-			const s32 a = CPU.GPR[ra]._s32[i];
-			CPU.GPR[rt]._f[i] = (float)a;
-
-			u32 exp = ((CPU.GPR[rt]._u32[i] >> 23) & 0xff) - scale;
-
-			if (exp > 255) //< 0
-				exp = 0;
-
-			CPU.GPR[rt]._u32[i] = (CPU.GPR[rt]._u32[i] & 0x807fffff) | (exp << 23);
-			if (isdenormal(CPU.GPR[rt]._f[i]) || (CPU.GPR[rt]._f[i] == 0.0f && a != 0))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(i, FPSCR_SUNF | FPSCR_SDIFF);
-				CPU.GPR[rt]._f[i] = 0.0f;
-			}
-		}
-	}
-	void CUFLT(u32 rt, u32 ra, s32 i8)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		const int scale = 155 - (i8 & 0xff); //unsigned immediate
-		for (int i = 0; i < 4; i++)
-		{
-			const u32 a = CPU.GPR[ra]._u32[i];
-			CPU.GPR[rt]._f[i] = (float)a;
-
-			u32 exp = ((CPU.GPR[rt]._u32[i] >> 23) & 0xff) - scale;
-
-			if (exp > 255) //< 0
-				exp = 0;
-
-			CPU.GPR[rt]._u32[i] = (CPU.GPR[rt]._u32[i] & 0x807fffff) | (exp << 23);
-			if (isdenormal(CPU.GPR[rt]._f[i]) || (CPU.GPR[rt]._f[i] == 0.0f && a != 0))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(i, FPSCR_SUNF | FPSCR_SDIFF);
-				CPU.GPR[rt]._f[i] = 0.0f;
-			}
-		}
-	}
-
-	//0 - 8
-	void BRZ(u32 rt, s32 i16)
-	{
-		u32 target = branchTarget(CPU.PC, i16);
-		if (CPU.GPR[rt]._u32[3] == 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void STQA(u32 rt, s32 i16)
-	{
-		u32 lsa = (i16 << 2) & 0x3fff0;
-
-		CPU.write128(lsa, CPU.GPR[rt]);
-	}
-	void BRNZ(u32 rt, s32 i16)
-	{
-		u32 target = branchTarget(CPU.PC, i16);
-		if (CPU.GPR[rt]._u32[3] != 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void BRHZ(u32 rt, s32 i16)
-	{
-		u32 target = branchTarget(CPU.PC, i16);
-		if (CPU.GPR[rt]._u16[6] == 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void BRHNZ(u32 rt, s32 i16)
-	{
-		u32 target = branchTarget(CPU.PC, i16);
-		if (CPU.GPR[rt]._u16[6] != 0)
-		{
-			LOG5_OPCODE("taken (0x%x)", target);
-			CPU.PC = target - 4;
-		}
-		else
-		{
-			LOG5_OPCODE("not taken (0x%x)", target);
-		}
-	}
-	void STQR(u32 rt, s32 i16)
-	{
-		u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0; 
-
-		CPU.write128(lsa, CPU.GPR[rt]);
-	}
-	void BRA(s32 i16)
-	{
-		u32 target = branchTarget(0, i16);
-		LOG5_OPCODE("branch (0x%x)", target);
-		CPU.PC = target - 4;
-	}
-	void LQA(u32 rt, s32 i16)
-	{
-		u32 lsa = (i16 << 2) & 0x3fff0;
-
-		CPU.GPR[rt] = CPU.read128(lsa);
-	}
-	void BRASL(u32 rt, s32 i16)
-	{
-		u32 target = branchTarget(0, i16);
-		CPU.GPR[rt] = v128::from32r(CPU.PC + 4);
-		LOG5_OPCODE("branch (0x%x)", target);
-		CPU.PC = target - 4;
-	}
-	void BR(s32 i16)
-	{
-		u32 target = branchTarget(CPU.PC, i16);
-		LOG5_OPCODE("branch (0x%x)", target);
-		CPU.PC = target - 4;
-	}
-	void FSMBI(u32 rt, s32 i16)
-	{
-		const u32 s = i16;
-
-		for(u32 j = 0; j < 16; ++j)
-		{
-			if((s >> j) & 0x1)
-			{
-				CPU.GPR[rt]._u8[j] = 0xFF;
-			}
-			else
-			{
-				CPU.GPR[rt]._u8[j] = 0x00;
-			}
-		}
-	}
-	void BRSL(u32 rt, s32 i16)
-	{
-		u32 target = branchTarget(CPU.PC, i16);
-		CPU.GPR[rt] = v128::from32r(CPU.PC + 4);
-		LOG5_OPCODE("branch (0x%x)", target);
-		CPU.PC = target - 4;
-	}
-	void LQR(u32 rt, s32 i16)
-	{
-		u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
-
-		CPU.GPR[rt] = CPU.read128(lsa);
-	}
-	void IL(u32 rt, s32 i16)
-	{
-		CPU.GPR[rt]._s32[0] =
-			CPU.GPR[rt]._s32[1] =
-			CPU.GPR[rt]._s32[2] =
-			CPU.GPR[rt]._s32[3] = i16;
-	}
-	void ILHU(u32 rt, s32 i16)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = i16 << 16;
-	}
-	void ILH(u32 rt, s32 i16)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = i16;
-	}
-	void IOHL(u32 rt, s32 i16)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] |= (i16 & 0xFFFF);
-	}
-	
-
-	//0 - 7
-	void ORI(u32 rt, u32 ra, s32 i10)
-	{
-		for(u32 i = 0; i < 4; ++i)
-			CPU.GPR[rt]._s32[i] = CPU.GPR[ra]._s32[i] | i10;
-	}
-	void ORHI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] | i10;
-	}
-	void ORBI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] | i10;
-	}
-	void SFI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = i10 - CPU.GPR[ra]._s32[w];
-	}
-	void SFHI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = i10 - CPU.GPR[ra]._s16[h];
-	}
-	void ANDI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s32[w] & i10;
-	}
-	void ANDHI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] & i10;
-	}
-	void ANDBI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] & i10;
-	}
-	void AI(u32 rt, u32 ra, s32 i10)
-	{
-		CPU.GPR[rt]._s32[0] = CPU.GPR[ra]._s32[0] + i10;
-		CPU.GPR[rt]._s32[1] = CPU.GPR[ra]._s32[1] + i10;
-		CPU.GPR[rt]._s32[2] = CPU.GPR[ra]._s32[2] + i10;
-		CPU.GPR[rt]._s32[3] = CPU.GPR[ra]._s32[3] + i10;
-	}
-	void AHI(u32 rt, u32 ra, s32 i10)
-	{
-		for(u32 h = 0; h < 8; ++h)
-			CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] + i10;
-	}
-	void STQD(u32 rt, s32 i10, u32 ra) //i10 is shifted left by 4 while decoding
-	{
-		const u32 lsa = (CPU.GPR[ra]._s32[3] + i10) & 0x3fff0;
-
-		CPU.write128(lsa, CPU.GPR[rt]);
-	}
-	void LQD(u32 rt, s32 i10, u32 ra) //i10 is shifted left by 4 while decoding
-	{
-		const u32 lsa = (CPU.GPR[ra]._s32[3] + i10) & 0x3fff0;
-
-		CPU.GPR[rt] = CPU.read128(lsa);
-	}
-	void XORI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s32[w] ^ i10;
-	}
-	void XORHI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] ^ i10;
-	}
-	void XORBI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] ^ i10;
-	}
-	void CGTI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] > i10 ? 0xffffffff : 0;
-	}
-	void CGTHI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._s16[h] > i10 ? 0xffff : 0;
-	}
-	void CGTBI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._s8[b] > (s8)(i10 & 0xff) ? 0xff : 0;
-	}
-	void HGTI(u32 rt, u32 ra, s32 i10)
-	{
-		if (CPU.GPR[ra]._s32[3] > i10)
-		{
-			CPU.halt();
-		}
-	}
-	void CLGTI(u32 rt, u32 ra, s32 i10)
-	{
-		for(u32 i = 0; i < 4; ++i)
-		{
-			CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._u32[i] > (u32)i10) ? 0xffffffff : 0x00000000;
-		}
-	}
-	void CLGTHI(u32 rt, u32 ra, s32 i10)
-	{
-		for(u32 i = 0; i < 8; ++i)
-		{
-			CPU.GPR[rt]._u16[i] = (CPU.GPR[ra]._u16[i] > (u16)i10) ? 0xffff : 0x0000;
-		}
-	}
-	void CLGTBI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] > (u8)(i10 & 0xff) ? 0xff : 0;
-	}
-	void HLGTI(u32 rt, u32 ra, s32 i10)
-	{
-		if (CPU.GPR[ra]._u32[3] > (u32)i10)
-		{
-			CPU.halt();
-		}
-	}
-	void MPYI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * i10;
-	}
-	void MPYUI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2] * (u16)(i10 & 0xffff);
-	}
-	void CEQI(u32 rt, u32 ra, s32 i10)
-	{
-		for(u32 i = 0; i < 4; ++i)
-			CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._s32[i] == i10) ? 0xffffffff : 0x00000000;
-	}
-	void CEQHI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int h = 0; h < 8; h++)
-			CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._s16[h] == (s16)i10) ? 0xffff : 0;
-	}
-	void CEQBI(u32 rt, u32 ra, s32 i10)
-	{
-		for (int b = 0; b < 16; b++)
-			CPU.GPR[rt]._s8[b] = (CPU.GPR[ra]._s8[b] == (s8)(i10 & 0xff)) ? 0xff : 0;
-	}
-	void HEQI(u32 rt, u32 ra, s32 i10)
-	{
-		if (CPU.GPR[ra]._s32[3] == i10)
-		{
-			CPU.halt();
-		}
-	}
-
-
-	//0 - 6
-	void HBRA(s32 ro, s32 i16)
-	{ //i16 is shifted left by 2 while decoding
-	}
-	void HBRR(s32 ro, s32 i16)
-	{
-	}
-	void ILA(u32 rt, u32 i18)
-	{
-		CPU.GPR[rt]._u32[0] = 
-			CPU.GPR[rt]._u32[1] = 
-			CPU.GPR[rt]._u32[2] = 
-			CPU.GPR[rt]._u32[3] = i18 & 0x3FFFF;
-	}
-
-	//0 - 3
-	void SELB(u32 rt, u32 ra, u32 rb, u32 rc)
-	{
-		for(u64 i = 0; i < 2; ++i)
-		{
-			CPU.GPR[rt]._u64[i] =
-				( CPU.GPR[rc]._u64[i] & CPU.GPR[rb]._u64[i]) |
-				(~CPU.GPR[rc]._u64[i] & CPU.GPR[ra]._u64[i]);
-		}
-	}
-	void SHUFB(u32 rt, u32 ra, u32 rb, u32 rc)
-	{
-		const v128 _a = CPU.GPR[ra];
-		const v128 _b = CPU.GPR[rb];
-		for (int i = 0; i < 16; i++)
-		{
-			u8 b = CPU.GPR[rc]._u8[i];
-			if(b & 0x80)
-			{
-				if(b & 0x40)
-				{
-					if(b & 0x20)
-						CPU.GPR[rt]._u8[i] = 0x80;
-					else
-						CPU.GPR[rt]._u8[i] = 0xFF;
-				}
-				else
-					CPU.GPR[rt]._u8[i] = 0x00;
-			}
-			else
-			{
-				if(b & 0x10)
-					CPU.GPR[rt]._u8[i] = _b._u8[15 - (b & 0x0F)];
-				else
-					CPU.GPR[rt]._u8[i] = _a._u8[15 - (b & 0x0F)];
-			}
-		}
-	}
-	void MPYA(u32 rt, u32 ra, u32 rb, u32 rc)
-	{
-		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2] + CPU.GPR[rc]._s32[w];
-	}
-	void FNMS(u32 rt, u32 ra, u32 rb, u32 rc) {FMA(rt, ra, rb, rc, true, true);}
-	void FMA(u32 rt, u32 ra, u32 rb, u32 rc) {FMA(rt, ra, rb, rc, false, false);}
-	void FMS(u32 rt, u32 ra, u32 rb, u32 rc) {FMA(rt, ra, rb, rc, false, true);}
-	void FMA(u32 rt, u32 ra, u32 rb, u32 rc, bool neg, bool sub)
-	{
-		SetHostRoundingMode(FPSCR_RN_ZERO);
-		for (int w = 0; w < 4; w++)
-		{
-			float a = CPU.GPR[ra]._f[w];
-			float b = neg ? -CPU.GPR[rb]._f[w] : CPU.GPR[rb]._f[w];
-			float c = (neg != sub) ? -CPU.GPR[rc]._f[w] : CPU.GPR[rc]._f[w];
-			if (isdenormal(a))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				a = 0.0f;
-			}
-			if (isdenormal(b))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				b = 0.0f;
-			}
-			if (isdenormal(c))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				c = 0.0f;
-			}
-
-			const bool sign = std::signbit(a) ^ std::signbit(b);
-			float result;
-
-			if (isextended(a) || isextended(b))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				if (a == 0.0f || b == 0.0f)
-				{
-					result = c;
-				}
-				else if ((fexpf(a)-127) + (fexpf(b)-127) >= 130)
-				{
-					CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-					result = extended(sign, 0x7FFFFF);
-				}
-				else
-				{
-					float new_a, new_b;
-					if (isextended(a))
-					{
-						new_a = ldexpf_extended(a, -2);
-						new_b = b;
-					}
-					else
-					{
-						new_a = a;
-						new_b = ldexpf_extended(b, -2);
-					}
-					if (fexpf(c) < 3)
-					{
-						result = new_a * new_b;
-						if (c != 0.0f && std::signbit(c) != sign)
-						{
-							u32 bits = (u32&)result - 1;
-							result = (float&)bits;
-						}
-					}
-					else
-					{
-						result = fmaf(new_a, new_b, ldexpf_extended(c, -2));
-					}
-					if (fabsf(result) >= ldexpf(1.0f, 127))
-					{
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-						result = extended(sign, 0x7FFFFF);
-					}
-					else
-					{
-						result = ldexpf_extended(result, 2);
-					}
-				}
-			}
-			else if (isextended(c))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-				if (a == 0.0f || b == 0.0f)
-				{
-					result = c;
-				}
-				else if ((fexpf(a)-127) + (fexpf(b)-127) < 96)
-				{
-					result = c;
-					if (sign != std::signbit(c))
-					{
-					    u32 bits = (u32&)result - 1;
-					    result = (float&)bits;
-					}
-				}
-				else
-				{
-					result = fmaf(ldexpf(a,-1), ldexpf(b,-1), ldexpf_extended(c,-2));
-					if (fabsf(result) >= ldexpf(1.0f, 127))
-					{
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-						result = extended(sign, 0x7FFFFF);
-					}
-					else
-					{
-						result = ldexpf_extended(result, 2);
-					}
-				}
-			}
-			else
-			{
-				feclearexcept(FE_ALL_EXCEPT);
-				result = fmaf(a, b, c);
-				if (fetestexcept(FE_OVERFLOW))
-				{
-					CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SDIFF);
-					if (fexpf(a) > fexpf(b))
-						result = fmaf(ldexpf(a,-2), b, ldexpf(c,-2));
-					else
-						result = fmaf(a, ldexpf(b,-2), ldexpf(c,-2));
-					if (fabsf(result) >= ldexpf(1.0f, 127))
-					{
-						CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SOVF);
-						result = extended(sign, 0x7FFFFF);
-					}
-					else
-					{
-						result = ldexpf_extended(result, 2);
-					}
-				}
-				else if (fetestexcept(FE_UNDERFLOW))
-				{
-					CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
-				}
-			}
-			if (isdenormal(result))
-			{
-				CPU.FPSCR.setSinglePrecisionExceptionFlags(w, FPSCR_SUNF | FPSCR_SDIFF);
-				result = 0.0f;
-			}
-			else if (result == 0.0f)
-			{
-				result = +0.0f;
-			}
-			CPU.GPR[rt]._f[w] = result;
-		}
-	}
-
-	void UNK(u32 code, u32 opcode, u32 gcode)
-	{
-		UNK(fmt::format("Unknown/Illegal opcode! (0x%08x, 0x%x, 0x%x)", code, opcode, gcode));
-	}
-
-	void UNK(const std::string& err)
-	{
-		LOG_ERROR(Log::SPU, "%s #pc: 0x%x", err.c_str(), CPU.PC);
-		Emu.Pause();
-		for(uint i=0; i<128; ++i) LOG_NOTICE(Log::SPU, "r%d = 0x%s", i, CPU.GPR[i].to_hex().c_str());
-	}
-};
diff --git a/rpcs3/Emu/Cell/SPUInterpreter2.h b/rpcs3/Emu/Cell/SPUInterpreter2.h
deleted file mode 100644
index 6abe8516ed..0000000000
--- a/rpcs3/Emu/Cell/SPUInterpreter2.h
+++ /dev/null
@@ -1,514 +0,0 @@
-#pragma once
-
-class SPUThread;
-
-union spu_opcode_t
-{
-	u32 opcode;
-
-	struct
-	{
-		u32 rt : 7; // 25..31, it's actually RC in 4-op instructions
-		u32 ra : 7; // 18..24
-		u32 rb : 7; // 11..17
-		u32 rc : 7; // 4..10, it's actually RT in 4-op instructions
-	};
-
-	struct
-	{
-		u32    : 14; // 18..31
-		u32 i7 : 7;  // 11..17
-	};
-
-	struct
-	{
-		u32    : 14; // 18..31
-		u32 i8 : 8;  // 10..17
-	};
-
-	struct
-	{
-		u32     : 14; // 18..31
-		u32 i10 : 10; // 8..17
-	};
-
-	struct
-	{
-		u32     : 7; // 25..31
-		u32 i16 : 16; // 9..24
-	};
-
-	struct
-	{
-		u32     : 7; // 25..31
-		u32 i18 : 18; // 7..24
-	};
-
-	struct
-	{
-		s32     : 14; // 18..31
-		s32 si7 : 7;  // 11..17
-	};
-
-	struct
-	{
-		s32     : 14; // 18..31
-		s32 si8 : 8;  // 10..17
-	};
-
-	struct
-	{
-		s32      : 14; // 18..31
-		s32 si10 : 10; // 8..17
-	};
-
-	struct
-	{
-		s32      : 7; // 25..31
-		s32 si16 : 16; // 9..24
-	};
-
-	struct
-	{
-		s32      : 7; // 25..31
-		s32 si18 : 18; // 7..24
-	};
-
-	struct
-	{
-		u32   : 18; // 14..31
-		u32 e : 1; // 13, "enable interrupts" bit
-		u32 d : 1; // 12, "disable interrupts" bit
-	};
-};
-
-using spu_inter_func_t = void(*)(SPUThread& CPU, spu_opcode_t opcode);
-
-namespace spu_interpreter
-{
-	void DEFAULT(SPUThread& CPU, spu_opcode_t op);
-
-	void set_interrupt_status(SPUThread& CPU, spu_opcode_t op);
-
-	void STOP(SPUThread& CPU, spu_opcode_t op);
-	void LNOP(SPUThread& CPU, spu_opcode_t op);
-	void SYNC(SPUThread& CPU, spu_opcode_t op);
-	void DSYNC(SPUThread& CPU, spu_opcode_t op);
-	void MFSPR(SPUThread& CPU, spu_opcode_t op);
-	void RDCH(SPUThread& CPU, spu_opcode_t op);
-	void RCHCNT(SPUThread& CPU, spu_opcode_t op);
-	void SF(SPUThread& CPU, spu_opcode_t op);
-	void OR(SPUThread& CPU, spu_opcode_t op);
-	void BG(SPUThread& CPU, spu_opcode_t op);
-	void SFH(SPUThread& CPU, spu_opcode_t op);
-	void NOR(SPUThread& CPU, spu_opcode_t op);
-	void ABSDB(SPUThread& CPU, spu_opcode_t op);
-	void ROT(SPUThread& CPU, spu_opcode_t op);
-	void ROTM(SPUThread& CPU, spu_opcode_t op);
-	void ROTMA(SPUThread& CPU, spu_opcode_t op);
-	void SHL(SPUThread& CPU, spu_opcode_t op);
-	void ROTH(SPUThread& CPU, spu_opcode_t op);
-	void ROTHM(SPUThread& CPU, spu_opcode_t op);
-	void ROTMAH(SPUThread& CPU, spu_opcode_t op);
-	void SHLH(SPUThread& CPU, spu_opcode_t op);
-	void ROTI(SPUThread& CPU, spu_opcode_t op);
-	void ROTMI(SPUThread& CPU, spu_opcode_t op);
-	void ROTMAI(SPUThread& CPU, spu_opcode_t op);
-	void SHLI(SPUThread& CPU, spu_opcode_t op);
-	void ROTHI(SPUThread& CPU, spu_opcode_t op);
-	void ROTHMI(SPUThread& CPU, spu_opcode_t op);
-	void ROTMAHI(SPUThread& CPU, spu_opcode_t op);
-	void SHLHI(SPUThread& CPU, spu_opcode_t op);
-	void A(SPUThread& CPU, spu_opcode_t op);
-	void AND(SPUThread& CPU, spu_opcode_t op);
-	void CG(SPUThread& CPU, spu_opcode_t op);
-	void AH(SPUThread& CPU, spu_opcode_t op);
-	void NAND(SPUThread& CPU, spu_opcode_t op);
-	void AVGB(SPUThread& CPU, spu_opcode_t op);
-	void MTSPR(SPUThread& CPU, spu_opcode_t op);
-	void WRCH(SPUThread& CPU, spu_opcode_t op);
-	void BIZ(SPUThread& CPU, spu_opcode_t op);
-	void BINZ(SPUThread& CPU, spu_opcode_t op);
-	void BIHZ(SPUThread& CPU, spu_opcode_t op);
-	void BIHNZ(SPUThread& CPU, spu_opcode_t op);
-	void STOPD(SPUThread& CPU, spu_opcode_t op);
-	void STQX(SPUThread& CPU, spu_opcode_t op);
-	void BI(SPUThread& CPU, spu_opcode_t op);
-	void BISL(SPUThread& CPU, spu_opcode_t op);
-	void IRET(SPUThread& CPU, spu_opcode_t op);
-	void BISLED(SPUThread& CPU, spu_opcode_t op);
-	void HBR(SPUThread& CPU, spu_opcode_t op);
-	void GB(SPUThread& CPU, spu_opcode_t op);
-	void GBH(SPUThread& CPU, spu_opcode_t op);
-	void GBB(SPUThread& CPU, spu_opcode_t op);
-	void FSM(SPUThread& CPU, spu_opcode_t op);
-	void FSMH(SPUThread& CPU, spu_opcode_t op);
-	void FSMB(SPUThread& CPU, spu_opcode_t op);
-	void FREST(SPUThread& CPU, spu_opcode_t op);
-	void FRSQEST(SPUThread& CPU, spu_opcode_t op);
-	void LQX(SPUThread& CPU, spu_opcode_t op);
-	void ROTQBYBI(SPUThread& CPU, spu_opcode_t op);
-	void ROTQMBYBI(SPUThread& CPU, spu_opcode_t op);
-	void SHLQBYBI(SPUThread& CPU, spu_opcode_t op);
-	void CBX(SPUThread& CPU, spu_opcode_t op);
-	void CHX(SPUThread& CPU, spu_opcode_t op);
-	void CWX(SPUThread& CPU, spu_opcode_t op);
-	void CDX(SPUThread& CPU, spu_opcode_t op);
-	void ROTQBI(SPUThread& CPU, spu_opcode_t op);
-	void ROTQMBI(SPUThread& CPU, spu_opcode_t op);
-	void SHLQBI(SPUThread& CPU, spu_opcode_t op);
-	void ROTQBY(SPUThread& CPU, spu_opcode_t op);
-	void ROTQMBY(SPUThread& CPU, spu_opcode_t op);
-	void SHLQBY(SPUThread& CPU, spu_opcode_t op);
-	void ORX(SPUThread& CPU, spu_opcode_t op);
-	void CBD(SPUThread& CPU, spu_opcode_t op);
-	void CHD(SPUThread& CPU, spu_opcode_t op);
-	void CWD(SPUThread& CPU, spu_opcode_t op);
-	void CDD(SPUThread& CPU, spu_opcode_t op);
-	void ROTQBII(SPUThread& CPU, spu_opcode_t op);
-	void ROTQMBII(SPUThread& CPU, spu_opcode_t op);
-	void SHLQBII(SPUThread& CPU, spu_opcode_t op);
-	void ROTQBYI(SPUThread& CPU, spu_opcode_t op);
-	void ROTQMBYI(SPUThread& CPU, spu_opcode_t op);
-	void SHLQBYI(SPUThread& CPU, spu_opcode_t op);
-	void NOP(SPUThread& CPU, spu_opcode_t op);
-	void CGT(SPUThread& CPU, spu_opcode_t op);
-	void XOR(SPUThread& CPU, spu_opcode_t op);
-	void CGTH(SPUThread& CPU, spu_opcode_t op);
-	void EQV(SPUThread& CPU, spu_opcode_t op);
-	void CGTB(SPUThread& CPU, spu_opcode_t op);
-	void SUMB(SPUThread& CPU, spu_opcode_t op);
-	void HGT(SPUThread& CPU, spu_opcode_t op);
-	void CLZ(SPUThread& CPU, spu_opcode_t op);
-	void XSWD(SPUThread& CPU, spu_opcode_t op);
-	void XSHW(SPUThread& CPU, spu_opcode_t op);
-	void CNTB(SPUThread& CPU, spu_opcode_t op);
-	void XSBH(SPUThread& CPU, spu_opcode_t op);
-	void CLGT(SPUThread& CPU, spu_opcode_t op);
-	void ANDC(SPUThread& CPU, spu_opcode_t op);
-	void FCGT(SPUThread& CPU, spu_opcode_t op);
-	void DFCGT(SPUThread& CPU, spu_opcode_t op);
-	void FA(SPUThread& CPU, spu_opcode_t op);
-	void FS(SPUThread& CPU, spu_opcode_t op);
-	void FM(SPUThread& CPU, spu_opcode_t op);
-	void CLGTH(SPUThread& CPU, spu_opcode_t op);
-	void ORC(SPUThread& CPU, spu_opcode_t op);
-	void FCMGT(SPUThread& CPU, spu_opcode_t op);
-	void DFCMGT(SPUThread& CPU, spu_opcode_t op);
-	void DFA(SPUThread& CPU, spu_opcode_t op);
-	void DFS(SPUThread& CPU, spu_opcode_t op);
-	void DFM(SPUThread& CPU, spu_opcode_t op);
-	void CLGTB(SPUThread& CPU, spu_opcode_t op);
-	void HLGT(SPUThread& CPU, spu_opcode_t op);
-	void DFMA(SPUThread& CPU, spu_opcode_t op);
-	void DFMS(SPUThread& CPU, spu_opcode_t op);
-	void DFNMS(SPUThread& CPU, spu_opcode_t op);
-	void DFNMA(SPUThread& CPU, spu_opcode_t op);
-	void CEQ(SPUThread& CPU, spu_opcode_t op);
-	void MPYHHU(SPUThread& CPU, spu_opcode_t op);
-	void ADDX(SPUThread& CPU, spu_opcode_t op);
-	void SFX(SPUThread& CPU, spu_opcode_t op);
-	void CGX(SPUThread& CPU, spu_opcode_t op);
-	void BGX(SPUThread& CPU, spu_opcode_t op);
-	void MPYHHA(SPUThread& CPU, spu_opcode_t op);
-	void MPYHHAU(SPUThread& CPU, spu_opcode_t op);
-	void FSCRRD(SPUThread& CPU, spu_opcode_t op);
-	void FESD(SPUThread& CPU, spu_opcode_t op);
-	void FRDS(SPUThread& CPU, spu_opcode_t op);
-	void FSCRWR(SPUThread& CPU, spu_opcode_t op);
-	void DFTSV(SPUThread& CPU, spu_opcode_t op);
-	void FCEQ(SPUThread& CPU, spu_opcode_t op);
-	void DFCEQ(SPUThread& CPU, spu_opcode_t op);
-	void MPY(SPUThread& CPU, spu_opcode_t op);
-	void MPYH(SPUThread& CPU, spu_opcode_t op);
-	void MPYHH(SPUThread& CPU, spu_opcode_t op);
-	void MPYS(SPUThread& CPU, spu_opcode_t op);
-	void CEQH(SPUThread& CPU, spu_opcode_t op);
-	void FCMEQ(SPUThread& CPU, spu_opcode_t op);
-	void DFCMEQ(SPUThread& CPU, spu_opcode_t op);
-	void MPYU(SPUThread& CPU, spu_opcode_t op);
-	void CEQB(SPUThread& CPU, spu_opcode_t op);
-	void FI(SPUThread& CPU, spu_opcode_t op);
-	void HEQ(SPUThread& CPU, spu_opcode_t op);
-
-	void CFLTS(SPUThread& CPU, spu_opcode_t op);
-	void CFLTU(SPUThread& CPU, spu_opcode_t op);
-	void CSFLT(SPUThread& CPU, spu_opcode_t op);
-	void CUFLT(SPUThread& CPU, spu_opcode_t op);
-
-	void BRZ(SPUThread& CPU, spu_opcode_t op);
-	void STQA(SPUThread& CPU, spu_opcode_t op);
-	void BRNZ(SPUThread& CPU, spu_opcode_t op);
-	void BRHZ(SPUThread& CPU, spu_opcode_t op);
-	void BRHNZ(SPUThread& CPU, spu_opcode_t op);
-	void STQR(SPUThread& CPU, spu_opcode_t op);
-	void BRA(SPUThread& CPU, spu_opcode_t op);
-	void LQA(SPUThread& CPU, spu_opcode_t op);
-	void BRASL(SPUThread& CPU, spu_opcode_t op);
-	void BR(SPUThread& CPU, spu_opcode_t op);
-	void FSMBI(SPUThread& CPU, spu_opcode_t op);
-	void BRSL(SPUThread& CPU, spu_opcode_t op);
-	void LQR(SPUThread& CPU, spu_opcode_t op);
-	void IL(SPUThread& CPU, spu_opcode_t op);
-	void ILHU(SPUThread& CPU, spu_opcode_t op);
-	void ILH(SPUThread& CPU, spu_opcode_t op);
-	void IOHL(SPUThread& CPU, spu_opcode_t op);
-
-	void ORI(SPUThread& CPU, spu_opcode_t op);
-	void ORHI(SPUThread& CPU, spu_opcode_t op);
-	void ORBI(SPUThread& CPU, spu_opcode_t op);
-	void SFI(SPUThread& CPU, spu_opcode_t op);
-	void SFHI(SPUThread& CPU, spu_opcode_t op);
-	void ANDI(SPUThread& CPU, spu_opcode_t op);
-	void ANDHI(SPUThread& CPU, spu_opcode_t op);
-	void ANDBI(SPUThread& CPU, spu_opcode_t op);
-	void AI(SPUThread& CPU, spu_opcode_t op);
-	void AHI(SPUThread& CPU, spu_opcode_t op);
-	void STQD(SPUThread& CPU, spu_opcode_t op);
-	void LQD(SPUThread& CPU, spu_opcode_t op);
-	void XORI(SPUThread& CPU, spu_opcode_t op);
-	void XORHI(SPUThread& CPU, spu_opcode_t op);
-	void XORBI(SPUThread& CPU, spu_opcode_t op);
-	void CGTI(SPUThread& CPU, spu_opcode_t op);
-	void CGTHI(SPUThread& CPU, spu_opcode_t op);
-	void CGTBI(SPUThread& CPU, spu_opcode_t op);
-	void HGTI(SPUThread& CPU, spu_opcode_t op);
-	void CLGTI(SPUThread& CPU, spu_opcode_t op);
-	void CLGTHI(SPUThread& CPU, spu_opcode_t op);
-	void CLGTBI(SPUThread& CPU, spu_opcode_t op);
-	void HLGTI(SPUThread& CPU, spu_opcode_t op);
-	void MPYI(SPUThread& CPU, spu_opcode_t op);
-	void MPYUI(SPUThread& CPU, spu_opcode_t op);
-	void CEQI(SPUThread& CPU, spu_opcode_t op);
-	void CEQHI(SPUThread& CPU, spu_opcode_t op);
-	void CEQBI(SPUThread& CPU, spu_opcode_t op);
-	void HEQI(SPUThread& CPU, spu_opcode_t op);
-
-	void HBRA(SPUThread& CPU, spu_opcode_t op);
-	void HBRR(SPUThread& CPU, spu_opcode_t op);
-	void ILA(SPUThread& CPU, spu_opcode_t op);
-
-	void SELB(SPUThread& CPU, spu_opcode_t op);
-	void SHUFB(SPUThread& CPU, spu_opcode_t op);
-	void MPYA(SPUThread& CPU, spu_opcode_t op);
-	void FNMS(SPUThread& CPU, spu_opcode_t op);
-	void FMA(SPUThread& CPU, spu_opcode_t op);
-	void FMS(SPUThread& CPU, spu_opcode_t op);
-
-	void UNK(SPUThread& CPU, spu_opcode_t op);
-}
-
-class SPUInterpreter2 : public SPUOpcodes
-{
-public:
-	virtual ~SPUInterpreter2() {}
-
-	spu_inter_func_t func;
-
-	virtual void STOP(u32 code) { func = spu_interpreter::STOP; }
-	virtual void LNOP() { func = spu_interpreter::LNOP; }
-	virtual void SYNC(u32 Cbit) { func = spu_interpreter::SYNC; }
-	virtual void DSYNC() { func = spu_interpreter::DSYNC; }
-	virtual void MFSPR(u32 rt, u32 sa) { func = spu_interpreter::MFSPR; }
-	virtual void RDCH(u32 rt, u32 ra) { func = spu_interpreter::RDCH; }
-	virtual void RCHCNT(u32 rt, u32 ra) { func = spu_interpreter::RCHCNT; }
-	virtual void SF(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SF; }
-	virtual void OR(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::OR; }
-	virtual void BG(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::BG; }
-	virtual void SFH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SFH; }
-	virtual void NOR(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::NOR; }
-	virtual void ABSDB(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ABSDB; }
-	virtual void ROT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROT; }
-	virtual void ROTM(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTM; }
-	virtual void ROTMA(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTMA; }
-	virtual void SHL(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SHL; }
-	virtual void ROTH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTH; }
-	virtual void ROTHM(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTHM; }
-	virtual void ROTMAH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTMAH; }
-	virtual void SHLH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SHLH; }
-	virtual void ROTI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTI; }
-	virtual void ROTMI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTMI; }
-	virtual void ROTMAI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTMAI; }
-	virtual void SHLI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::SHLI; }
-	virtual void ROTHI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTHI; }
-	virtual void ROTHMI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTHMI; }
-	virtual void ROTMAHI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTMAHI; }
-	virtual void SHLHI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::SHLHI; }
-	virtual void A(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::A; }
-	virtual void AND(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::AND; }
-	virtual void CG(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CG; }
-	virtual void AH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::AH; }
-	virtual void NAND(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::NAND; }
-	virtual void AVGB(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::AVGB; }
-	virtual void MTSPR(u32 rt, u32 sa) { func = spu_interpreter::MTSPR; }
-	virtual void WRCH(u32 ra, u32 rt) { func = spu_interpreter::WRCH; }
-	virtual void BIZ(u32 intr, u32 rt, u32 ra) { func = spu_interpreter::BIZ; }
-	virtual void BINZ(u32 intr, u32 rt, u32 ra) { func = spu_interpreter::BINZ; }
-	virtual void BIHZ(u32 intr, u32 rt, u32 ra) { func = spu_interpreter::BIHZ; }
-	virtual void BIHNZ(u32 intr, u32 rt, u32 ra) { func = spu_interpreter::BIHNZ; }
-	virtual void STOPD(u32 rc, u32 ra, u32 rb) { func = spu_interpreter::STOPD; }
-	virtual void STQX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::STQX; }
-	virtual void BI(u32 intr, u32 ra) { func = spu_interpreter::BI; }
-	virtual void BISL(u32 intr, u32 rt, u32 ra) { func = spu_interpreter::BISL; }
-	virtual void IRET(u32 ra) { func = spu_interpreter::IRET; }
-	virtual void BISLED(u32 intr, u32 rt, u32 ra) { func = spu_interpreter::BISLED; }
-	virtual void HBR(u32 p, u32 ro, u32 ra) { func = spu_interpreter::HBR; }
-	virtual void GB(u32 rt, u32 ra) { func = spu_interpreter::GB; }
-	virtual void GBH(u32 rt, u32 ra) { func = spu_interpreter::GBH; }
-	virtual void GBB(u32 rt, u32 ra) { func = spu_interpreter::GBB; }
-	virtual void FSM(u32 rt, u32 ra) { func = spu_interpreter::FSM; }
-	virtual void FSMH(u32 rt, u32 ra) { func = spu_interpreter::FSMH; }
-	virtual void FSMB(u32 rt, u32 ra) { func = spu_interpreter::FSMB; }
-	virtual void FREST(u32 rt, u32 ra) { func = spu_interpreter::FREST; }
-	virtual void FRSQEST(u32 rt, u32 ra) { func = spu_interpreter::FRSQEST; }
-	virtual void LQX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::LQX; }
-	virtual void ROTQBYBI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTQBYBI; }
-	virtual void ROTQMBYBI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTQMBYBI; }
-	virtual void SHLQBYBI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SHLQBYBI; }
-	virtual void CBX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CBX; }
-	virtual void CHX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CHX; }
-	virtual void CWX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CWX; }
-	virtual void CDX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CDX; }
-	virtual void ROTQBI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTQBI; }
-	virtual void ROTQMBI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTQMBI; }
-	virtual void SHLQBI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SHLQBI; }
-	virtual void ROTQBY(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTQBY; }
-	virtual void ROTQMBY(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ROTQMBY; }
-	virtual void SHLQBY(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SHLQBY; }
-	virtual void ORX(u32 rt, u32 ra) { func = spu_interpreter::ORX; }
-	virtual void CBD(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::CBD; }
-	virtual void CHD(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::CHD; }
-	virtual void CWD(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::CWD; }
-	virtual void CDD(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::CDD; }
-	virtual void ROTQBII(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTQBII; }
-	virtual void ROTQMBII(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTQMBII; }
-	virtual void SHLQBII(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::SHLQBII; }
-	virtual void ROTQBYI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTQBYI; }
-	virtual void ROTQMBYI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::ROTQMBYI; }
-	virtual void SHLQBYI(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::SHLQBYI; }
-	virtual void NOP(u32 rt) { func = spu_interpreter::NOP; }
-	virtual void CGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CGT; }
-	virtual void XOR(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::XOR; }
-	virtual void CGTH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CGTH; }
-	virtual void EQV(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::EQV; }
-	virtual void CGTB(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CGTB; }
-	virtual void SUMB(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SUMB; }
-	virtual void HGT(u32 rt, s32 ra, s32 rb) { func = spu_interpreter::HGT; }
-	virtual void CLZ(u32 rt, u32 ra) { func = spu_interpreter::CLZ; }
-	virtual void XSWD(u32 rt, u32 ra) { func = spu_interpreter::XSWD; }
-	virtual void XSHW(u32 rt, u32 ra) { func = spu_interpreter::XSHW; }
-	virtual void CNTB(u32 rt, u32 ra) { func = spu_interpreter::CNTB; }
-	virtual void XSBH(u32 rt, u32 ra) { func = spu_interpreter::XSBH; }
-	virtual void CLGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CLGT; }
-	virtual void ANDC(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ANDC; }
-	virtual void FCGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FCGT; }
-	virtual void DFCGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFCGT; }
-	virtual void FA(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FA; }
-	virtual void FS(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FS; }
-	virtual void FM(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FM; }
-	virtual void CLGTH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CLGTH; }
-	virtual void ORC(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ORC; }
-	virtual void FCMGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FCMGT; }
-	virtual void DFCMGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFCMGT; }
-	virtual void DFA(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFA; }
-	virtual void DFS(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFS; }
-	virtual void DFM(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFM; }
-	virtual void CLGTB(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CLGTB; }
-	virtual void HLGT(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::HLGT; }
-	virtual void DFMA(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFMA; }
-	virtual void DFMS(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFMS; }
-	virtual void DFNMS(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFNMS; }
-	virtual void DFNMA(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFNMA; }
-	virtual void CEQ(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CEQ; }
-	virtual void MPYHHU(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYHHU; }
-	virtual void ADDX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::ADDX; }
-	virtual void SFX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::SFX; }
-	virtual void CGX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CGX; }
-	virtual void BGX(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::BGX; }
-	virtual void MPYHHA(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYHHA; }
-	virtual void MPYHHAU(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYHHAU; }
-	virtual void FSCRRD(u32 rt) { func = spu_interpreter::FSCRRD; }
-	virtual void FESD(u32 rt, u32 ra) { func = spu_interpreter::FESD; }
-	virtual void FRDS(u32 rt, u32 ra) { func = spu_interpreter::FRDS; }
-	virtual void FSCRWR(u32 rt, u32 ra) { func = spu_interpreter::FSCRWR; }
-	virtual void DFTSV(u32 rt, u32 ra, s32 i7) { func = spu_interpreter::DFTSV; }
-	virtual void FCEQ(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FCEQ; }
-	virtual void DFCEQ(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFCEQ; }
-	virtual void MPY(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPY; }
-	virtual void MPYH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYH; }
-	virtual void MPYHH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYHH; }
-	virtual void MPYS(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYS; }
-	virtual void CEQH(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CEQH; }
-	virtual void FCMEQ(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FCMEQ; }
-	virtual void DFCMEQ(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::DFCMEQ; }
-	virtual void MPYU(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::MPYU; }
-	virtual void CEQB(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::CEQB; }
-	virtual void FI(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::FI; }
-	virtual void HEQ(u32 rt, u32 ra, u32 rb) { func = spu_interpreter::HEQ; }
-
-	virtual void CFLTS(u32 rt, u32 ra, s32 i8) { func = spu_interpreter::CFLTS; }
-	virtual void CFLTU(u32 rt, u32 ra, s32 i8) { func = spu_interpreter::CFLTU; }
-	virtual void CSFLT(u32 rt, u32 ra, s32 i8) { func = spu_interpreter::CSFLT; }
-	virtual void CUFLT(u32 rt, u32 ra, s32 i8) { func = spu_interpreter::CUFLT; }
-
-	virtual void BRZ(u32 rt, s32 i16) { func = spu_interpreter::BRZ; }
-	virtual void STQA(u32 rt, s32 i16) { func = spu_interpreter::STQA; }
-	virtual void BRNZ(u32 rt, s32 i16) { func = spu_interpreter::BRNZ; }
-	virtual void BRHZ(u32 rt, s32 i16) { func = spu_interpreter::BRHZ; }
-	virtual void BRHNZ(u32 rt, s32 i16) { func = spu_interpreter::BRHNZ; }
-	virtual void STQR(u32 rt, s32 i16) { func = spu_interpreter::STQR; }
-	virtual void BRA(s32 i16) { func = spu_interpreter::BRA; }
-	virtual void LQA(u32 rt, s32 i16) { func = spu_interpreter::LQA; }
-	virtual void BRASL(u32 rt, s32 i16) { func = spu_interpreter::BRASL; }
-	virtual void BR(s32 i16) { func = spu_interpreter::BR; }
-	virtual void FSMBI(u32 rt, s32 i16) { func = spu_interpreter::FSMBI; }
-	virtual void BRSL(u32 rt, s32 i16) { func = spu_interpreter::BRSL; }
-	virtual void LQR(u32 rt, s32 i16) { func = spu_interpreter::LQR; }
-	virtual void IL(u32 rt, s32 i16) { func = spu_interpreter::IL; }
-	virtual void ILHU(u32 rt, s32 i16) { func = spu_interpreter::ILHU; }
-	virtual void ILH(u32 rt, s32 i16) { func = spu_interpreter::ILH; }
-	virtual void IOHL(u32 rt, s32 i16) { func = spu_interpreter::IOHL; }
-
-	virtual void ORI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::ORI; }
-	virtual void ORHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::ORHI; }
-	virtual void ORBI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::ORBI; }
-	virtual void SFI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::SFI; }
-	virtual void SFHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::SFHI; }
-	virtual void ANDI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::ANDI; }
-	virtual void ANDHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::ANDHI; }
-	virtual void ANDBI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::ANDBI; }
-	virtual void AI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::AI; }
-	virtual void AHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::AHI; }
-	virtual void STQD(u32 rt, s32 i10, u32 ra) { func = spu_interpreter::STQD; }
-	virtual void LQD(u32 rt, s32 i10, u32 ra) { func = spu_interpreter::LQD; }
-	virtual void XORI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::XORI; }
-	virtual void XORHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::XORHI; }
-	virtual void XORBI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::XORBI; }
-	virtual void CGTI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CGTI; }
-	virtual void CGTHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CGTHI; }
-	virtual void CGTBI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CGTBI; }
-	virtual void HGTI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::HGTI; }
-	virtual void CLGTI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CLGTI; }
-	virtual void CLGTHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CLGTHI; }
-	virtual void CLGTBI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CLGTBI; }
-	virtual void HLGTI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::HLGTI; }
-	virtual void MPYI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::MPYI; }
-	virtual void MPYUI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::MPYUI; }
-	virtual void CEQI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CEQI; }
-	virtual void CEQHI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CEQHI; }
-	virtual void CEQBI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::CEQBI; }
-	virtual void HEQI(u32 rt, u32 ra, s32 i10) { func = spu_interpreter::HEQI; }
-
-	virtual void HBRA(s32 ro, s32 i16) { func = spu_interpreter::HBRA; }
-	virtual void HBRR(s32 ro, s32 i16) { func = spu_interpreter::HBRR; }
-	virtual void ILA(u32 rt, u32 i18) { func = spu_interpreter::ILA; }
-
-	virtual void SELB(u32 rc, u32 ra, u32 rb, u32 rt) { func = spu_interpreter::SELB; }
-	virtual void SHUFB(u32 rc, u32 ra, u32 rb, u32 rt) { func = spu_interpreter::SHUFB; }
-	virtual void MPYA(u32 rc, u32 ra, u32 rb, u32 rt) { func = spu_interpreter::MPYA; }
-	virtual void FNMS(u32 rc, u32 ra, u32 rb, u32 rt) { func = spu_interpreter::FNMS; }
-	virtual void FMA(u32 rc, u32 ra, u32 rb, u32 rt) { func = spu_interpreter::FMA; }
-	virtual void FMS(u32 rc, u32 ra, u32 rb, u32 rt) { func = spu_interpreter::FMS; }
-
-	virtual void UNK(u32 code, u32 opcode, u32 gcode) { func = spu_interpreter::UNK; }
-};
diff --git a/rpcs3/Emu/Cell/SPUOpcodes.h b/rpcs3/Emu/Cell/SPUOpcodes.h
index dd8a99b082..f2791e4971 100644
--- a/rpcs3/Emu/Cell/SPUOpcodes.h
+++ b/rpcs3/Emu/Cell/SPUOpcodes.h
@@ -1,451 +1,322 @@
 #pragma once
 
-namespace SPU_opcodes
+union spu_opcode_t
 {
-	enum SPU_0_10_Opcodes
+	u32 opcode;
+
+	struct
 	{
-		STOP      = 0x0,
-		LNOP      = 0x1,
-		SYNC      = 0x2,
-		DSYNC     = 0x3,
-		MFSPR     = 0xc,
-		RDCH      = 0xd,
-		RCHCNT    = 0xf,
-		SF        = 0x40,
-		OR        = 0x41,
-		BG        = 0x42,
-		SFH       = 0x48,
-		NOR       = 0x49,
-		ABSDB     = 0x53,
-		ROT       = 0x58,
-		ROTM      = 0x59,
-		ROTMA     = 0x5a,
-		SHL       = 0x5b,
-		ROTH      = 0x5c,
-		ROTHM     = 0x5d,
-		ROTMAH    = 0x5e,
-		SHLH      = 0x5f,
-		ROTI      = 0x78,
-		ROTMI     = 0x79,
-		ROTMAI    = 0x7a,
-		SHLI      = 0x7b,
-		ROTHI     = 0x7c,
-		ROTHMI    = 0x7d,
-		ROTMAHI   = 0x7e,
-		SHLHI     = 0x7f,
-		A         = 0xc0,
-		AND       = 0xc1,
-		CG        = 0xc2,
-		AH        = 0xc8,
-		NAND      = 0xc9,
-		AVGB      = 0xd3,
-		MTSPR     = 0x10c,
-		WRCH      = 0x10d,
-		BIZ       = 0x128,
-		BINZ      = 0x129,
-		BIHZ      = 0x12a,
-		BIHNZ     = 0x12b,
-		STOPD     = 0x140,
-		STQX      = 0x144,
-		BI        = 0x1a8,
-		BISL      = 0x1a9,
-		IRET      = 0x1aa,
-		BISLED    = 0x1ab,
-		HBR       = 0x1ac,
-		GB        = 0x1b0,
-		GBH       = 0x1b1,
-		GBB       = 0x1b2,
-		FSM       = 0x1b4,
-		FSMH      = 0x1b5,
-		FSMB      = 0x1b6,
-		FREST     = 0x1b8,
-		FRSQEST   = 0x1b9,
-		LQX       = 0x1c4,
-		ROTQBYBI  = 0x1cc,
-		ROTQMBYBI = 0x1cd,
-		SHLQBYBI  = 0x1cf,
-		CBX       = 0x1d4,
-		CHX       = 0x1d5,
-		CWX       = 0x1d6,
-		CDX       = 0x1d7,
-		ROTQBI    = 0x1d8,
-		ROTQMBI   = 0x1d9,
-		SHLQBI    = 0x1db,
-		ROTQBY    = 0x1dc,
-		ROTQMBY   = 0x1dd,
-		SHLQBY    = 0x1df,
-		ORX       = 0x1f0,
-		CBD       = 0x1f4,
-		CHD       = 0x1f5,
-		CWD       = 0x1f6,
-		CDD       = 0x1f7,
-		ROTQBII   = 0x1f8,
-		ROTQMBII  = 0x1f9,
-		SHLQBII   = 0x1fb,
-		ROTQBYI   = 0x1fc,
-		ROTQMBYI  = 0x1fd,
-		SHLQBYI   = 0x1ff,
-		NOP       = 0x201,
-		CGT       = 0x240,
-		XOR       = 0x241,
-		CGTH      = 0x248,
-		EQV       = 0x249,
-		CGTB      = 0x250,
-		SUMB      = 0x253,
-		HGT       = 0x258,
-		CLZ       = 0x2a5,
-		XSWD      = 0x2a6,
-		XSHW      = 0x2ae,
-		CNTB      = 0x2b4,
-		XSBH      = 0x2b6,
-		CLGT      = 0x2c0,
-		ANDC      = 0x2c1,
-		FCGT      = 0x2c2,
-		DFCGT     = 0x2c3,
-		FA        = 0x2c4,
-		FS        = 0x2c5,
-		FM        = 0x2c6,
-		CLGTH     = 0x2c8,
-		ORC       = 0x2c9,
-		FCMGT     = 0x2ca,
-		DFCMGT    = 0x2cb,
-		DFA       = 0x2cc,
-		DFS       = 0x2cd,
-		DFM       = 0x2ce,
-		CLGTB     = 0x2d0,
-		HLGT      = 0x2d8,
-		DFMA      = 0x35c,
-		DFMS      = 0x35d,
-		DFNMS     = 0x35e,
-		DFNMA     = 0x35f,
-		CEQ       = 0x3c0,
-		MPYHHU    = 0x3ce,
-		ADDX      = 0x340,
-		SFX       = 0x341,
-		CGX       = 0x342,
-		BGX       = 0x343,
-		MPYHHA    = 0x346,
-		MPYHHAU   = 0x34e,
-		FSCRRD    = 0x398,
-		FESD      = 0x3b8,
-		FRDS      = 0x3b9,
-		FSCRWR    = 0x3ba,
-		DFTSV     = 0x3bf,
-		FCEQ      = 0x3c2,
-		DFCEQ     = 0x3c3,
-		MPY       = 0x3c4,
-		MPYH      = 0x3c5,
-		MPYHH     = 0x3c6,
-		MPYS      = 0x3c7,
-		CEQH      = 0x3c8,
-		FCMEQ     = 0x3ca,
-		DFCMEQ    = 0x3cb,
-		MPYU      = 0x3cc,
-		CEQB      = 0x3d0,
-		FI        = 0x3d4,
-		HEQ       = 0x3d8,
+		u32 rt : 7; // 25..31, it's actually RC in 4-op instructions
+		u32 ra : 7; // 18..24
+		u32 rb : 7; // 11..17
+		u32 rc : 7; // 4..10, it's actually RT in 4-op instructions
 	};
 
-	enum SPU_0_9_Opcodes
+	struct
 	{
-		CFLTS = 0x1d8,
-		CFLTU = 0x1d9,
-		CSFLT = 0x1da,
-		CUFLT = 0x1db,
+		u32    : 14; // 18..31
+		u32 i7 : 7;  // 11..17
 	};
 
-	enum SPU_0_8_Opcodes
+	struct
 	{
-		BRZ   = 0x40,
-		STQA  = 0x41,
-		BRNZ  = 0x42,
-		BRHZ  = 0x44,
-		BRHNZ = 0x46,
-		STQR  = 0x47,
-		BRA   = 0x60,
-		LQA   = 0x61,
-		BRASL = 0x62,
-		BR    = 0x64,
-		FSMBI = 0x65,
-		BRSL  = 0x66,
-		LQR   = 0x67,
-		IL    = 0x81,
-		ILHU  = 0x82,
-		ILH   = 0x83,
-		IOHL  = 0xc1,
+		u32    : 14; // 18..31
+		u32 i8 : 8;  // 10..17
 	};
 
-	enum SPU_0_7_Opcodes
+	struct
 	{
-		ORI    = 0x4,
-		ORHI   = 0x5,
-		ORBI   = 0x6,
-		SFI    = 0xc,
-		SFHI   = 0xd,
-		ANDI   = 0x14,
-		ANDHI  = 0x15,
-		ANDBI  = 0x16,
-		AI     = 0x1c,
-		AHI    = 0x1d,
-		STQD   = 0x24,
-		LQD    = 0x34,
-		XORI   = 0x44,
-		XORHI  = 0x45,
-		XORBI  = 0x46,
-		CGTI   = 0x4c,
-		CGTHI  = 0x4d,
-		CGTBI  = 0x4e,
-		HGTI   = 0x4f,
-		CLGTI  = 0x5c,
-		CLGTHI = 0x5d,
-		CLGTBI = 0x5e,
-		HLGTI  = 0x5f,
-		MPYI   = 0x74,
-		MPYUI  = 0x75,
-		CEQI   = 0x7c,
-		CEQHI  = 0x7d,
-		CEQBI  = 0x7e,
-		HEQI   = 0x7f,
+		u32     : 7; // 25..31
+		u32 i16 : 16; // 9..24
 	};
 
-	enum SPU_0_6_Opcodes
+	struct
 	{
-		HBRA = 0x8,
-		HBRR = 0x9,
-		ILA  = 0x21,
+		u32     : 7; // 25..31
+		u32 i18 : 18; // 7..24
 	};
 
-	enum SPU_0_3_Opcodes
+	struct
 	{
-		SELB  = 0x8,
-		SHUFB = 0xb,
-		MPYA  = 0xc,
-		FNMS  = 0xd,
-		FMA   = 0xe,
-		FMS   = 0xf,
+		s32     : 14; // 18..31
+		s32 si7 : 7;  // 11..17
+	};
+
+	struct
+	{
+		s32     : 14; // 18..31
+		s32 si8 : 8;  // 10..17
+	};
+
+	struct
+	{
+		s32      : 14; // 18..31
+		s32 si10 : 10; // 8..17
+	};
+
+	struct
+	{
+		s32      : 7; // 25..31
+		s32 si16 : 16; // 9..24
+		s32 r0h  : 2; // 7..8
+	};
+
+	struct
+	{
+		s32     : 14; // 18..31
+		s32 roh : 2;  // 16..17
+	};
+
+	struct
+	{
+		u32   : 18; // 14..31
+		u32 e : 1; // 13, "enable interrupts" bit
+		u32 d : 1; // 12, "disable interrupts" bit
+		u32 c : 1; // 11, "C" bit for SYNC instruction
 	};
 };
 
-class SPUOpcodes
-{
-public:
-	virtual ~SPUOpcodes() {}
+#define DEFINE_SPU_OPCODES(ns) { \
+	{ 10, 0x0, ns STOP }, \
+	{ 10, 0x1, ns LNOP }, \
+	{ 10, 0x2, ns SYNC }, \
+	{ 10, 0x3, ns DSYNC }, \
+	{ 10, 0xc, ns MFSPR }, \
+	{ 10, 0xd, ns RDCH }, \
+	{ 10, 0xf, ns RCHCNT }, \
+	{ 10, 0x40, ns SF }, \
+	{ 10, 0x41, ns OR }, \
+	{ 10, 0x42, ns BG }, \
+	{ 10, 0x48, ns SFH }, \
+	{ 10, 0x49, ns NOR }, \
+	{ 10, 0x53, ns ABSDB }, \
+	{ 10, 0x58, ns ROT }, \
+	{ 10, 0x59, ns ROTM }, \
+	{ 10, 0x5a, ns ROTMA }, \
+	{ 10, 0x5b, ns SHL }, \
+	{ 10, 0x5c, ns ROTH }, \
+	{ 10, 0x5d, ns ROTHM }, \
+	{ 10, 0x5e, ns ROTMAH }, \
+	{ 10, 0x5f, ns SHLH }, \
+	{ 10, 0x78, ns ROTI }, \
+	{ 10, 0x79, ns ROTMI }, \
+	{ 10, 0x7a, ns ROTMAI }, \
+	{ 10, 0x7b, ns SHLI }, \
+	{ 10, 0x7c, ns ROTHI }, \
+	{ 10, 0x7d, ns ROTHMI }, \
+	{ 10, 0x7e, ns ROTMAHI }, \
+	{ 10, 0x7f, ns SHLHI }, \
+	{ 10, 0xc0, ns A }, \
+	{ 10, 0xc1, ns AND }, \
+	{ 10, 0xc2, ns CG }, \
+	{ 10, 0xc8, ns AH }, \
+	{ 10, 0xc9, ns NAND }, \
+	{ 10, 0xd3, ns AVGB }, \
+	{ 10, 0x10c, ns MTSPR }, \
+	{ 10, 0x10d, ns WRCH }, \
+	{ 10, 0x128, ns BIZ }, \
+	{ 10, 0x129, ns BINZ }, \
+	{ 10, 0x12a, ns BIHZ }, \
+	{ 10, 0x12b, ns BIHNZ }, \
+	{ 10, 0x140, ns STOPD }, \
+	{ 10, 0x144, ns STQX }, \
+	{ 10, 0x1a8, ns BI }, \
+	{ 10, 0x1a9, ns BISL }, \
+	{ 10, 0x1aa, ns IRET }, \
+	{ 10, 0x1ab, ns BISLED }, \
+	{ 10, 0x1ac, ns HBR }, \
+	{ 10, 0x1b0, ns GB }, \
+	{ 10, 0x1b1, ns GBH }, \
+	{ 10, 0x1b2, ns GBB }, \
+	{ 10, 0x1b4, ns FSM }, \
+	{ 10, 0x1b5, ns FSMH }, \
+	{ 10, 0x1b6, ns FSMB }, \
+	{ 10, 0x1b8, ns FREST }, \
+	{ 10, 0x1b9, ns FRSQEST }, \
+	{ 10, 0x1c4, ns LQX }, \
+	{ 10, 0x1cc, ns ROTQBYBI }, \
+	{ 10, 0x1cd, ns ROTQMBYBI }, \
+	{ 10, 0x1cf, ns SHLQBYBI }, \
+	{ 10, 0x1d4, ns CBX }, \
+	{ 10, 0x1d5, ns CHX }, \
+	{ 10, 0x1d6, ns CWX }, \
+	{ 10, 0x1d7, ns CDX }, \
+	{ 10, 0x1d8, ns ROTQBI }, \
+	{ 10, 0x1d9, ns ROTQMBI }, \
+	{ 10, 0x1db, ns SHLQBI }, \
+	{ 10, 0x1dc, ns ROTQBY }, \
+	{ 10, 0x1dd, ns ROTQMBY }, \
+	{ 10, 0x1df, ns SHLQBY }, \
+	{ 10, 0x1f0, ns ORX }, \
+	{ 10, 0x1f4, ns CBD }, \
+	{ 10, 0x1f5, ns CHD }, \
+	{ 10, 0x1f6, ns CWD }, \
+	{ 10, 0x1f7, ns CDD }, \
+	{ 10, 0x1f8, ns ROTQBII }, \
+	{ 10, 0x1f9, ns ROTQMBII }, \
+	{ 10, 0x1fb, ns SHLQBII }, \
+	{ 10, 0x1fc, ns ROTQBYI }, \
+	{ 10, 0x1fd, ns ROTQMBYI }, \
+	{ 10, 0x1ff, ns SHLQBYI }, \
+	{ 10, 0x201, ns NOP }, \
+	{ 10, 0x240, ns CGT }, \
+	{ 10, 0x241, ns XOR }, \
+	{ 10, 0x248, ns CGTH }, \
+	{ 10, 0x249, ns EQV }, \
+	{ 10, 0x250, ns CGTB }, \
+	{ 10, 0x253, ns SUMB }, \
+	{ 10, 0x258, ns HGT }, \
+	{ 10, 0x2a5, ns CLZ }, \
+	{ 10, 0x2a6, ns XSWD }, \
+	{ 10, 0x2ae, ns XSHW }, \
+	{ 10, 0x2b4, ns CNTB }, \
+	{ 10, 0x2b6, ns XSBH }, \
+	{ 10, 0x2c0, ns CLGT }, \
+	{ 10, 0x2c1, ns ANDC }, \
+	{ 10, 0x2c2, ns FCGT }, \
+	{ 10, 0x2c3, ns DFCGT }, \
+	{ 10, 0x2c4, ns FA }, \
+	{ 10, 0x2c5, ns FS }, \
+	{ 10, 0x2c6, ns FM }, \
+	{ 10, 0x2c8, ns CLGTH }, \
+	{ 10, 0x2c9, ns ORC }, \
+	{ 10, 0x2ca, ns FCMGT }, \
+	{ 10, 0x2cb, ns DFCMGT }, \
+	{ 10, 0x2cc, ns DFA }, \
+	{ 10, 0x2cd, ns DFS }, \
+	{ 10, 0x2ce, ns DFM }, \
+	{ 10, 0x2d0, ns CLGTB }, \
+	{ 10, 0x2d8, ns HLGT }, \
+	{ 10, 0x35c, ns DFMA }, \
+	{ 10, 0x35d, ns DFMS }, \
+	{ 10, 0x35e, ns DFNMS }, \
+	{ 10, 0x35f, ns DFNMA }, \
+	{ 10, 0x3c0, ns CEQ }, \
+	{ 10, 0x3ce, ns MPYHHU }, \
+	{ 10, 0x340, ns ADDX }, \
+	{ 10, 0x341, ns SFX }, \
+	{ 10, 0x342, ns CGX }, \
+	{ 10, 0x343, ns BGX }, \
+	{ 10, 0x346, ns MPYHHA }, \
+	{ 10, 0x34e, ns MPYHHAU }, \
+	{ 10, 0x398, ns FSCRRD }, \
+	{ 10, 0x3b8, ns FESD }, \
+	{ 10, 0x3b9, ns FRDS }, \
+	{ 10, 0x3ba, ns FSCRWR }, \
+	{ 10, 0x3bf, ns DFTSV }, \
+	{ 10, 0x3c2, ns FCEQ }, \
+	{ 10, 0x3c3, ns DFCEQ }, \
+	{ 10, 0x3c4, ns MPY }, \
+	{ 10, 0x3c5, ns MPYH }, \
+	{ 10, 0x3c6, ns MPYHH }, \
+	{ 10, 0x3c7, ns MPYS }, \
+	{ 10, 0x3c8, ns CEQH }, \
+	{ 10, 0x3ca, ns FCMEQ }, \
+	{ 10, 0x3cb, ns DFCMEQ }, \
+	{ 10, 0x3cc, ns MPYU }, \
+	{ 10, 0x3d0, ns CEQB }, \
+	{ 10, 0x3d4, ns FI }, \
+	{ 10, 0x3d8, ns HEQ }, \
+	{ 9, 0x1d8, ns CFLTS }, \
+	{ 9, 0x1d9, ns CFLTU }, \
+	{ 9, 0x1da, ns CSFLT }, \
+	{ 9, 0x1db, ns CUFLT }, \
+	{ 8, 0x40, ns BRZ }, \
+	{ 8, 0x41, ns STQA }, \
+	{ 8, 0x42, ns BRNZ }, \
+	{ 8, 0x44, ns BRHZ }, \
+	{ 8, 0x46, ns BRHNZ }, \
+	{ 8, 0x47, ns STQR }, \
+	{ 8, 0x60, ns BRA }, \
+	{ 8, 0x61, ns LQA }, \
+	{ 8, 0x62, ns BRASL }, \
+	{ 8, 0x64, ns BR }, \
+	{ 8, 0x65, ns FSMBI }, \
+	{ 8, 0x66, ns BRSL }, \
+	{ 8, 0x67, ns LQR }, \
+	{ 8, 0x81, ns IL }, \
+	{ 8, 0x82, ns ILHU }, \
+	{ 8, 0x83, ns ILH }, \
+	{ 8, 0xc1, ns IOHL }, \
+	{ 7, 0x4, ns ORI }, \
+	{ 7, 0x5, ns ORHI }, \
+	{ 7, 0x6, ns ORBI }, \
+	{ 7, 0xc, ns SFI }, \
+	{ 7, 0xd, ns SFHI }, \
+	{ 7, 0x14, ns ANDI }, \
+	{ 7, 0x15, ns ANDHI }, \
+	{ 7, 0x16, ns ANDBI }, \
+	{ 7, 0x1c, ns AI }, \
+	{ 7, 0x1d, ns AHI }, \
+	{ 7, 0x24, ns STQD }, \
+	{ 7, 0x34, ns LQD }, \
+	{ 7, 0x44, ns XORI }, \
+	{ 7, 0x45, ns XORHI }, \
+	{ 7, 0x46, ns XORBI }, \
+	{ 7, 0x4c, ns CGTI }, \
+	{ 7, 0x4d, ns CGTHI }, \
+	{ 7, 0x4e, ns CGTBI }, \
+	{ 7, 0x4f, ns HGTI }, \
+	{ 7, 0x5c, ns CLGTI }, \
+	{ 7, 0x5d, ns CLGTHI }, \
+	{ 7, 0x5e, ns CLGTBI }, \
+	{ 7, 0x5f, ns HLGTI }, \
+	{ 7, 0x74, ns MPYI }, \
+	{ 7, 0x75, ns MPYUI }, \
+	{ 7, 0x7c, ns CEQI }, \
+	{ 7, 0x7d, ns CEQHI }, \
+	{ 7, 0x7e, ns CEQBI }, \
+	{ 7, 0x7f, ns HEQI }, \
+	{ 6, 0x8, ns HBRA }, \
+	{ 6, 0x9, ns HBRR }, \
+	{ 6, 0x21, ns ILA }, \
+	{ 3, 0x8, ns SELB }, \
+	{ 3, 0xb, ns SHUFB }, \
+	{ 3, 0xc, ns MPYA }, \
+	{ 3, 0xd, ns FNMS }, \
+	{ 3, 0xe, ns FMA }, \
+	{ 3, 0xf, ns FMS }, \
+}
 
-	static u32 branchTarget(const u32 pc, const s32 imm)
+template<typename T> class spu_opcode_table_t
+{
+	std::array<T, 2048> m_data;
+
+	struct opcode_entry_t
 	{
-		return (pc + (imm << 2)) & 0x3fffc;
+		u32 group;
+		u32 value;
+		T pointer;
+	};
+
+public:
+	// opcode table initialization (TODO: optimize it a bit)
+	spu_opcode_table_t(std::initializer_list<opcode_entry_t> opcodes, T default_value = {})
+	{
+		for (u32 i = 0; i < 2048; i++)
+		{
+			m_data[i] = default_value;
+
+			for (auto& op : opcodes)
+			{
+				if (((i << 21) & (INT_MIN >> op.group)) == (op.value << (31 - op.group)))
+				{
+					m_data[i] = op.pointer;
+					break;
+				}
+			}
+		}
 	}
 
-	//0 - 10
-	virtual void STOP(u32 code) = 0;
-	virtual void LNOP() = 0;
-	virtual void SYNC(u32 Cbit) = 0;
-	virtual void DSYNC() = 0;
-	virtual void MFSPR(u32  rt, u32  sa) = 0;
-	virtual void RDCH(u32  rt, u32  ra) = 0;
-	virtual void RCHCNT(u32  rt, u32  ra) = 0;
-	virtual void SF(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void OR(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void BG(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SFH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void NOR(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ABSDB(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTM(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTMA(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SHL(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTHM(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTMAH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SHLH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTMI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTMAI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void SHLI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTHI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTHMI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTMAHI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void SHLHI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void A(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void AND(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CG(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void AH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void NAND(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void AVGB(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MTSPR(u32  rt, u32  sa) = 0;
-	virtual void WRCH(u32  ra, u32  rt) = 0;
-	virtual void BIZ(u32 intr, u32  rt, u32  ra) = 0;
-	virtual void BINZ(u32 intr, u32  rt, u32  ra) = 0;
-	virtual void BIHZ(u32 intr, u32  rt, u32  ra) = 0;
-	virtual void BIHNZ(u32 intr, u32  rt, u32  ra) = 0;
-	virtual void STOPD(u32  rc, u32  ra, u32  rb) = 0;
-	virtual void STQX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void BI(u32 intr, u32  ra) = 0;
-	virtual void BISL(u32 intr, u32  rt, u32  ra) = 0;
-	virtual void IRET(u32  ra) = 0;
-	virtual void BISLED(u32 intr, u32  rt, u32  ra) = 0;
-	virtual void HBR(u32  p, u32  ro, u32  ra) = 0;
-	virtual void GB(u32  rt, u32  ra) = 0;
-	virtual void GBH(u32  rt, u32  ra) = 0;
-	virtual void GBB(u32  rt, u32  ra) = 0;
-	virtual void FSM(u32  rt, u32  ra) = 0;
-	virtual void FSMH(u32  rt, u32  ra) = 0;
-	virtual void FSMB(u32  rt, u32  ra) = 0;
-	virtual void FREST(u32  rt, u32  ra) = 0;
-	virtual void FRSQEST(u32  rt, u32  ra) = 0;
-	virtual void LQX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTQBYBI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTQMBYBI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SHLQBYBI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CBX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CHX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CWX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CDX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTQBI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTQMBI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SHLQBI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTQBY(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ROTQMBY(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SHLQBY(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ORX(u32  rt, u32  ra) = 0;
-	virtual void CBD(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void CHD(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void CWD(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void CDD(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTQBII(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTQMBII(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void SHLQBII(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTQBYI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void ROTQMBYI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void SHLQBYI(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void NOP(u32  rt) = 0;
-	virtual void CGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void XOR(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CGTH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void EQV(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CGTB(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SUMB(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void HGT(u32  rt, s32  ra, s32  rb) = 0;
-	virtual void CLZ(u32  rt, u32  ra) = 0;
-	virtual void XSWD(u32  rt, u32  ra) = 0;
-	virtual void XSHW(u32  rt, u32  ra) = 0;
-	virtual void CNTB(u32  rt, u32  ra) = 0;
-	virtual void XSBH(u32  rt, u32  ra) = 0;
-	virtual void CLGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ANDC(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FCGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFCGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FA(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FS(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FM(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CLGTH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ORC(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FCMGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFCMGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFA(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFS(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFM(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CLGTB(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void HLGT(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFMA(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFMS(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFNMS(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFNMA(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CEQ(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYHHU(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void ADDX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void SFX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CGX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void BGX(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYHHA(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYHHAU(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FSCRRD(u32  rt) = 0;
-	virtual void FESD(u32  rt, u32  ra) = 0;
-	virtual void FRDS(u32  rt, u32  ra) = 0;
-	virtual void FSCRWR(u32  rt, u32  ra) = 0;
-	virtual void DFTSV(u32  rt, u32  ra, s32 i7) = 0;
-	virtual void FCEQ(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFCEQ(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPY(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYHH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYS(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CEQH(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FCMEQ(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void DFCMEQ(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void MPYU(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void CEQB(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void FI(u32  rt, u32  ra, u32  rb) = 0;
-	virtual void HEQ(u32  rt, u32  ra, u32  rb) = 0;
-
-	//0 - 9
-	virtual void CFLTS(u32  rt, u32  ra, s32 i8) = 0;
-	virtual void CFLTU(u32  rt, u32  ra, s32 i8) = 0;
-	virtual void CSFLT(u32  rt, u32  ra, s32 i8) = 0;
-	virtual void CUFLT(u32  rt, u32  ra, s32 i8) = 0;
-
-	//0 - 8
-	virtual void BRZ(u32  rt, s32 i16) = 0;
-	virtual void STQA(u32  rt, s32 i16) = 0;
-	virtual void BRNZ(u32  rt, s32 i16) = 0;
-	virtual void BRHZ(u32  rt, s32 i16) = 0;
-	virtual void BRHNZ(u32  rt, s32 i16) = 0;
-	virtual void STQR(u32  rt, s32 i16) = 0;
-	virtual void BRA(s32 i16) = 0;
-	virtual void LQA(u32  rt, s32 i16) = 0;
-	virtual void BRASL(u32  rt, s32 i16) = 0;
-	virtual void BR(s32 i16) = 0;
-	virtual void FSMBI(u32  rt, s32 i16) = 0;
-	virtual void BRSL(u32  rt, s32 i16) = 0;
-	virtual void LQR(u32  rt, s32 i16) = 0;
-	virtual void IL(u32  rt, s32 i16) = 0;
-	virtual void ILHU(u32  rt, s32 i16) = 0;
-	virtual void ILH(u32  rt, s32 i16) = 0;
-	virtual void IOHL(u32  rt, s32 i16) = 0;
-
-	//0 - 7
-	virtual void ORI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void ORHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void ORBI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void SFI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void SFHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void ANDI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void ANDHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void ANDBI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void AI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void AHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void STQD(u32  rt, s32 i10, u32  ra) = 0;
-	virtual void LQD(u32  rt, s32 i10, u32  ra) = 0;
-	virtual void XORI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void XORHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void XORBI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CGTI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CGTHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CGTBI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void HGTI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CLGTI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CLGTHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CLGTBI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void HLGTI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void MPYI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void MPYUI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CEQI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CEQHI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void CEQBI(u32  rt, u32  ra, s32 i10) = 0;
-	virtual void HEQI(u32  rt, u32  ra, s32 i10) = 0;
-
-	//0 - 6
-	virtual void HBRA(s32 ro, s32 i16) = 0;
-	virtual void HBRR(s32 ro, s32 i16) = 0;
-	virtual void ILA(u32  rt, u32 i18) = 0;
-
-	//0 - 3
-	virtual void SELB(u32  rc, u32  ra, u32  rb, u32  rt) = 0;
-	virtual void SHUFB(u32  rc, u32  ra, u32  rb, u32  rt) = 0;
-	virtual void MPYA(u32  rc, u32  ra, u32  rb, u32  rt) = 0;
-	virtual void FNMS(u32  rc, u32  ra, u32  rb, u32  rt) = 0;
-	virtual void FMA(u32  rc, u32  ra, u32  rb, u32  rt) = 0;
-	virtual void FMS(u32  rc, u32  ra, u32  rb, u32  rt) = 0;
-
-	virtual void UNK(u32 code, u32 opcode, u32 gcode) = 0;
+	// access opcode table
+	inline T operator [](u32 opcode_data) const
+	{
+		// the whole decoding process is shifting opcode data
+		return m_data[opcode_data >> 21];
+	}
 };
+
+inline u32 spu_branch_target(u32 pc, s32 imm)
+{
+	return (pc + (imm << 2)) & 0x3fffc;
+}
diff --git a/rpcs3/Emu/Cell/SPURecompiler.cpp b/rpcs3/Emu/Cell/SPURecompiler.cpp
new file mode 100644
index 0000000000..6e9aae3cae
--- /dev/null
+++ b/rpcs3/Emu/Cell/SPURecompiler.cpp
@@ -0,0 +1,75 @@
+#include "stdafx.h"
+#include "Utilities/Log.h"
+#include "Emu/IdManager.h"
+#include "Emu/Memory/Memory.h"
+
+#include "SPUThread.h"
+#include "SPURecompiler.h"
+#include "SPUASMJITRecompiler.h"
+
+extern u64 get_system_time();
+
+SPURecompilerDecoder::SPURecompilerDecoder(SPUThread& spu)
+	: db(fxm::get_always<SPUDatabase>())
+	, rec(fxm::get_always<spu_recompiler>())
+	, spu(spu)
+{
+}
+
+u32 SPURecompilerDecoder::DecodeMemory(const u32 address)
+{
+	if (spu.offset != address - spu.pc || spu.pc >= 0x40000 || spu.pc % 4)
+	{
+		throw EXCEPTION("Invalid address or PC (address=0x%x, PC=0x%05x)", address, spu.pc);
+	}
+
+	const auto _ls = vm::get_ptr<be_t<u32>>(spu.offset);
+
+	const u32 index = spu.pc / 4;
+
+	if (!m_entries.at(index) || true) // always validate (TODO)
+	{
+		const auto func = db->analyse(_ls, spu.pc);
+
+		if (!func->compiled) rec->compile(*func);
+
+		if (!func->compiled) throw EXCEPTION("Compilation failed");
+
+		m_entries[index] = func->compiled;
+	}
+
+	const u32 res = m_entries[index](&spu, _ls);
+
+	if (const auto exception = spu.pending_exception)
+	{
+		spu.pending_exception = nullptr;
+		std::rethrow_exception(exception);
+	}
+
+	if (res & 0x1000000)
+	{
+		spu.halt();
+	}
+
+	if (res & 0x2000000)
+	{
+	}
+
+	if (res & 0x4000000)
+	{
+		if (res & 0x8000000)
+		{
+			throw EXCEPTION("Undefined behaviour");
+		}
+
+		spu.set_interrupt_status(true);
+	}
+	else if (res & 0x8000000)
+	{
+		spu.set_interrupt_status(false);
+	}
+
+	spu.pc = res & 0x3fffc;
+
+	return 0;
+}
diff --git a/rpcs3/Emu/Cell/SPURecompiler.h b/rpcs3/Emu/Cell/SPURecompiler.h
index 66b1d22372..197acc545e 100644
--- a/rpcs3/Emu/Cell/SPURecompiler.h
+++ b/rpcs3/Emu/Cell/SPURecompiler.h
@@ -1,325 +1,38 @@
 #pragma once
+
 #include "Emu/CPU/CPUDecoder.h"
-#include "Emu/Cell/SPUOpcodes.h"
+#include "SPUAnalyser.h"
 
-namespace asmjit
+class SPUThread;
+
+// SPU Recompiler instance base (must be global or PS3 process-local)
+class SPURecompilerBase
 {
-	struct JitRuntime;
-	struct X86Compiler;
-	struct X86GpVar;
-	struct X86XmmVar;
-	struct X86Mem;
-}
+protected:
+	std::mutex m_mutex; // must be locked in compile()
 
-class SPURecompiler;
-class SPUInterpreter;
+	const spu_function_t* m_func; // current function
 
-class SPURecompilerCore : public CPUDecoder
-{
-	std::unique_ptr<SPURecompiler> m_enc;
-	std::unique_ptr<SPUInterpreter> m_int;
-	std::unique_ptr<asmjit::JitRuntime> m_jit;
-	SPUThread& CPU;
+	u32 m_pos; // current position
 
 public:
-	bool first = true;
-	bool need_check = false;
-
-	struct SPURecEntry
-	{
-		u32 count; // count of instructions compiled from current point (and to be checked)
-		be_t<u32> _valid; // copy of valid opcode for validation
-		void* pointer; // pointer to executable memory object
-	};
-
-	std::array<SPURecEntry, 0x10000> entry = {};
-
-	std::vector<v128> imm_table;
-
-	SPURecompilerCore(SPUThread& cpu);
-
-	void Compile(u16 pos);
-
-	virtual void Decode(const u32 code);
-
-	virtual u32 DecodeMemory(const u32 address);
+	virtual void compile(spu_function_t& f) = 0; // compile specified function
+	virtual ~SPURecompilerBase() {};
 };
 
-class SPURecompiler : public SPUOpcodes
+// SPU Decoder instance (created per SPU thread)
+class SPURecompilerDecoder final : public CPUDecoder
 {
-private:
-	SPUThread& CPU;
-	SPURecompilerCore& rec;
+	std::array<spu_jit_func_t, 0x10000> m_entries = {}; // currently useless
 
 public:
-	asmjit::X86Compiler* compiler;
-	bool do_finalize;
-	// input:
-	asmjit::X86GpVar* cpu_var;
-	asmjit::X86GpVar* ls_var;
-	asmjit::X86GpVar* imm_var;
-	asmjit::X86GpVar* g_imm_var;
-	// output:
-	asmjit::X86GpVar* pos_var;
-	// temporary:
-	asmjit::X86GpVar* addr;
-	asmjit::X86GpVar* qw0;
-	asmjit::X86GpVar* qw1;
-	asmjit::X86GpVar* qw2;
+	const std::shared_ptr<SPUDatabase> db; // associated SPU Analyser instance
 
-	struct XmmLink
-	{
-		asmjit::X86XmmVar* data = nullptr;
-		s8 reg = -1;
-		bool taken = false;
-		mutable bool got = false;
-		mutable u32 access = 0;
+	const std::shared_ptr<SPURecompilerBase> rec; // assiciated SPU Recompiler instance
 
-		const asmjit::X86XmmVar& get() const
-		{
-			assert(data);
-			if (!taken) throw EXCEPTION("Register not taken");
-			got = true;
-			return *data;
-		}
+	SPUThread& spu; // associated SPU Thread
 
-		const asmjit::X86XmmVar& read() const
-		{
-			assert(data);
-			return *data;
-		}
-	}
-	xmm_var[16];
+	SPURecompilerDecoder(SPUThread& spu);
 
-	SPURecompiler(SPUThread& cpu, SPURecompilerCore& rec)
-		: CPU(cpu)
-		, rec(rec)
-		, compiler(nullptr)
-	{
-	}
-
-	const XmmLink& XmmAlloc(s8 pref = -1);
-	const XmmLink* XmmRead(const s8 reg) const;
-	const XmmLink& XmmGet(s8 reg, s8 target = -1);
-	const XmmLink& XmmCopy(const XmmLink& from, s8 pref = -1);
-	void XmmInvalidate(const s8 reg);
-	void XmmFinalize(const XmmLink& var, s8 reg = -1);
-	void XmmRelease();
-	asmjit::X86Mem XmmConst(v128 data);
-
-private:
-
-	//0 - 10
-	virtual void STOP(u32 code) override;
-	virtual void LNOP() override;
-	virtual void SYNC(u32 Cbit) override;
-	virtual void DSYNC() override;
-	virtual void MFSPR(u32  rt, u32  sa) override;
-	virtual void RDCH(u32  rt, u32  ra) override;
-	virtual void RCHCNT(u32  rt, u32  ra) override;
-	virtual void SF(u32  rt, u32  ra, u32  rb) override;
-	virtual void OR(u32  rt, u32  ra, u32  rb) override;
-	virtual void BG(u32  rt, u32  ra, u32  rb) override;
-	virtual void SFH(u32  rt, u32  ra, u32  rb) override;
-	virtual void NOR(u32  rt, u32  ra, u32  rb) override;
-	virtual void ABSDB(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROT(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTM(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTMA(u32  rt, u32  ra, u32  rb) override;
-	virtual void SHL(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTH(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTHM(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTMAH(u32  rt, u32  ra, u32  rb) override;
-	virtual void SHLH(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTI(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTMI(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTMAI(u32  rt, u32  ra, s32 i7) override;
-	virtual void SHLI(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTHI(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTHMI(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTMAHI(u32  rt, u32  ra, s32 i7) override;
-	virtual void SHLHI(u32  rt, u32  ra, s32 i7) override;
-	virtual void A(u32  rt, u32  ra, u32  rb) override;
-	virtual void AND(u32  rt, u32  ra, u32  rb) override;
-	virtual void CG(u32  rt, u32  ra, u32  rb) override;
-	virtual void AH(u32  rt, u32  ra, u32  rb) override;
-	virtual void NAND(u32  rt, u32  ra, u32  rb) override;
-	virtual void AVGB(u32  rt, u32  ra, u32  rb) override;
-	virtual void MTSPR(u32  rt, u32  sa) override;
-	virtual void WRCH(u32  ra, u32  rt) override;
-	virtual void BIZ(u32 intr, u32  rt, u32  ra) override;
-	virtual void BINZ(u32 intr, u32  rt, u32  ra) override;
-	virtual void BIHZ(u32 intr, u32  rt, u32  ra) override;
-	virtual void BIHNZ(u32 intr, u32  rt, u32  ra) override;
-	virtual void STOPD(u32  rc, u32  ra, u32  rb) override;
-	virtual void STQX(u32  rt, u32  ra, u32  rb) override;
-	virtual void BI(u32 intr, u32  ra) override;
-	virtual void BISL(u32 intr, u32  rt, u32  ra) override;
-	virtual void IRET(u32  ra) override;
-	virtual void BISLED(u32 intr, u32  rt, u32  ra) override;
-	virtual void HBR(u32  p, u32  ro, u32  ra) override;
-	virtual void GB(u32  rt, u32  ra) override;
-	virtual void GBH(u32  rt, u32  ra) override;
-	virtual void GBB(u32  rt, u32  ra) override;
-	virtual void FSM(u32  rt, u32  ra) override;
-	virtual void FSMH(u32  rt, u32  ra) override;
-	virtual void FSMB(u32  rt, u32  ra) override;
-	virtual void FREST(u32  rt, u32  ra) override;
-	virtual void FRSQEST(u32  rt, u32  ra) override;
-	virtual void LQX(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTQBYBI(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTQMBYBI(u32  rt, u32  ra, u32  rb) override;
-	virtual void SHLQBYBI(u32  rt, u32  ra, u32  rb) override;
-	virtual void CBX(u32  rt, u32  ra, u32  rb) override;
-	virtual void CHX(u32  rt, u32  ra, u32  rb) override;
-	virtual void CWX(u32  rt, u32  ra, u32  rb) override;
-	virtual void CDX(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTQBI(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTQMBI(u32  rt, u32  ra, u32  rb) override;
-	virtual void SHLQBI(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTQBY(u32  rt, u32  ra, u32  rb) override;
-	virtual void ROTQMBY(u32  rt, u32  ra, u32  rb) override;
-	virtual void SHLQBY(u32  rt, u32  ra, u32  rb) override;
-	virtual void ORX(u32  rt, u32  ra) override;
-	virtual void CBD(u32  rt, u32  ra, s32 i7) override;
-	virtual void CHD(u32  rt, u32  ra, s32 i7) override;
-	virtual void CWD(u32  rt, u32  ra, s32 i7) override;
-	virtual void CDD(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTQBII(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTQMBII(u32  rt, u32  ra, s32 i7) override;
-	virtual void SHLQBII(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTQBYI(u32  rt, u32  ra, s32 i7) override;
-	virtual void ROTQMBYI(u32  rt, u32  ra, s32 i7) override;
-	virtual void SHLQBYI(u32  rt, u32  ra, s32 i7) override;
-	virtual void NOP(u32  rt) override;
-	virtual void CGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void XOR(u32  rt, u32  ra, u32  rb) override;
-	virtual void CGTH(u32  rt, u32  ra, u32  rb) override;
-	virtual void EQV(u32  rt, u32  ra, u32  rb) override;
-	virtual void CGTB(u32  rt, u32  ra, u32  rb) override;
-	virtual void SUMB(u32  rt, u32  ra, u32  rb) override;
-	virtual void HGT(u32  rt, s32  ra, s32  rb) override;
-	virtual void CLZ(u32  rt, u32  ra) override;
-	virtual void XSWD(u32  rt, u32  ra) override;
-	virtual void XSHW(u32  rt, u32  ra) override;
-	virtual void CNTB(u32  rt, u32  ra) override;
-	virtual void XSBH(u32  rt, u32  ra) override;
-	virtual void CLGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void ANDC(u32  rt, u32  ra, u32  rb) override;
-	virtual void FCGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFCGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void FA(u32  rt, u32  ra, u32  rb) override;
-	virtual void FS(u32  rt, u32  ra, u32  rb) override;
-	virtual void FM(u32  rt, u32  ra, u32  rb) override;
-	virtual void CLGTH(u32  rt, u32  ra, u32  rb) override;
-	virtual void ORC(u32  rt, u32  ra, u32  rb) override;
-	virtual void FCMGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFCMGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFA(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFS(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFM(u32  rt, u32  ra, u32  rb) override;
-	virtual void CLGTB(u32  rt, u32  ra, u32  rb) override;
-	virtual void HLGT(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFMA(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFMS(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFNMS(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFNMA(u32  rt, u32  ra, u32  rb) override;
-	virtual void CEQ(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYHHU(u32  rt, u32  ra, u32  rb) override;
-	virtual void ADDX(u32  rt, u32  ra, u32  rb) override;
-	virtual void SFX(u32  rt, u32  ra, u32  rb) override;
-	virtual void CGX(u32  rt, u32  ra, u32  rb) override;
-	virtual void BGX(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYHHA(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYHHAU(u32  rt, u32  ra, u32  rb) override;
-	virtual void FSCRRD(u32  rt) override;
-	virtual void FESD(u32  rt, u32  ra) override;
-	virtual void FRDS(u32  rt, u32  ra) override;
-	virtual void FSCRWR(u32  rt, u32  ra) override;
-	virtual void DFTSV(u32  rt, u32  ra, s32 i7) override;
-	virtual void FCEQ(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFCEQ(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPY(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYH(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYHH(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYS(u32  rt, u32  ra, u32  rb) override;
-	virtual void CEQH(u32  rt, u32  ra, u32  rb) override;
-	virtual void FCMEQ(u32  rt, u32  ra, u32  rb) override;
-	virtual void DFCMEQ(u32  rt, u32  ra, u32  rb) override;
-	virtual void MPYU(u32  rt, u32  ra, u32  rb) override;
-	virtual void CEQB(u32  rt, u32  ra, u32  rb) override;
-	virtual void FI(u32  rt, u32  ra, u32  rb) override;
-	virtual void HEQ(u32  rt, u32  ra, u32  rb) override;
-
-	//0 - 9
-	virtual void CFLTS(u32  rt, u32  ra, s32 i8) override;
-	virtual void CFLTU(u32  rt, u32  ra, s32 i8) override;
-	virtual void CSFLT(u32  rt, u32  ra, s32 i8) override;
-	virtual void CUFLT(u32  rt, u32  ra, s32 i8) override;
-
-	//0 - 8
-	virtual void BRZ(u32  rt, s32 i16) override;
-	virtual void STQA(u32  rt, s32 i16) override;
-	virtual void BRNZ(u32  rt, s32 i16) override;
-	virtual void BRHZ(u32  rt, s32 i16) override;
-	virtual void BRHNZ(u32  rt, s32 i16) override;
-	virtual void STQR(u32  rt, s32 i16) override;
-	virtual void BRA(s32 i16) override;
-	virtual void LQA(u32  rt, s32 i16) override;
-	virtual void BRASL(u32  rt, s32 i16) override;
-	virtual void BR(s32 i16) override;
-	virtual void FSMBI(u32  rt, s32 i16) override;
-	virtual void BRSL(u32  rt, s32 i16) override;
-	virtual void LQR(u32  rt, s32 i16) override;
-	virtual void IL(u32  rt, s32 i16) override;
-	virtual void ILHU(u32  rt, s32 i16) override;
-	virtual void ILH(u32  rt, s32 i16) override;
-	virtual void IOHL(u32  rt, s32 i16) override;
-
-	//0 - 7
-	virtual void ORI(u32  rt, u32  ra, s32 i10) override;
-	virtual void ORHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void ORBI(u32  rt, u32  ra, s32 i10) override;
-	virtual void SFI(u32  rt, u32  ra, s32 i10) override;
-	virtual void SFHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void ANDI(u32  rt, u32  ra, s32 i10) override;
-	virtual void ANDHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void ANDBI(u32  rt, u32  ra, s32 i10) override;
-	virtual void AI(u32  rt, u32  ra, s32 i10) override;
-	virtual void AHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void STQD(u32  rt, s32 i10, u32  ra) override;
-	virtual void LQD(u32  rt, s32 i10, u32  ra) override;
-	virtual void XORI(u32  rt, u32  ra, s32 i10) override;
-	virtual void XORHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void XORBI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CGTI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CGTHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CGTBI(u32  rt, u32  ra, s32 i10) override;
-	virtual void HGTI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CLGTI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CLGTHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CLGTBI(u32  rt, u32  ra, s32 i10) override;
-	virtual void HLGTI(u32  rt, u32  ra, s32 i10) override;
-	virtual void MPYI(u32  rt, u32  ra, s32 i10) override;
-	virtual void MPYUI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CEQI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CEQHI(u32  rt, u32  ra, s32 i10) override;
-	virtual void CEQBI(u32  rt, u32  ra, s32 i10) override;
-	virtual void HEQI(u32  rt, u32  ra, s32 i10) override;
-
-	//0 - 6
-	virtual void HBRA(s32 ro, s32 i16) override;
-	virtual void HBRR(s32 ro, s32 i16) override;
-	virtual void ILA(u32  rt, u32 i18) override;
-
-	//0 - 3
-	virtual void SELB(u32  rc, u32  ra, u32  rb, u32  rt) override;
-	virtual void SHUFB(u32  rc, u32  ra, u32  rb, u32  rt) override;
-	virtual void MPYA(u32  rc, u32  ra, u32  rb, u32  rt) override;
-	virtual void FNMS(u32  rc, u32  ra, u32  rb, u32  rt) override;
-	virtual void FMA(u32  rc, u32  ra, u32  rb, u32  rt) override;
-	virtual void FMS(u32  rc, u32  ra, u32  rb, u32  rt) override;
-
-	virtual void UNK(u32 code, u32 opcode, u32 gcode) override;
-	virtual void UNK(const std::string& error);
+	u32 DecodeMemory(const u32 address) override; // non-virtual override (to avoid virtual call whenever possible)
 };
diff --git a/rpcs3/Emu/Cell/SPURecompilerCore.cpp b/rpcs3/Emu/Cell/SPURecompilerCore.cpp
deleted file mode 100644
index 4e15619da7..0000000000
--- a/rpcs3/Emu/Cell/SPURecompilerCore.cpp
+++ /dev/null
@@ -1,3427 +0,0 @@
-#include "stdafx.h"
-#include "Utilities/Log.h"
-#include "Emu/Memory/Memory.h"
-#include "Emu/System.h"
-#include "Utilities/File.h"
-
-#include "SPUInstrTable.h"
-#include "SPUDisAsm.h"
-
-#include "SPUThread.h"
-#include "SPUInterpreter.h"
-#include "SPURecompiler.h"
-
-#define ASMJIT_STATIC
-
-#include "asmjit.h"
-
-using namespace asmjit;
-using namespace asmjit::host;
-
-extern u64 get_system_time();
-
-SPURecompilerCore::SPURecompilerCore(SPUThread& cpu)
-	: m_enc(new SPURecompiler(cpu, *this))
-	, m_int(new SPUInterpreter(cpu))
-	, m_jit(new JitRuntime)
-	, CPU(cpu)
-{
-	X86CpuInfo inf;
-	X86CpuUtil::detect(&inf);
-}
-
-void SPURecompilerCore::Decode(const u32 code) // decode instruction and run with interpreter
-{
-	(*SPU_instr::rrr_list)(m_int.get(), code);
-}
-
-void SPURecompilerCore::Compile(u16 pos)
-{
-	//const u64 stamp0 = get_system_time();
-	//u64 time0 = 0;
-
-	//SPUDisAsm dis_asm(CPUDisAsm_InterpreterMode);
-	//dis_asm.offset = vm::get_ptr<u8>(CPU.offset);
-
-	//StringLogger stringLogger;
-	//stringLogger.setOption(kLoggerOptionBinaryForm, true);
-
-	X86Compiler compiler(m_jit.get());
-	m_enc->compiler = &compiler;
-	//compiler.setLogger(&stringLogger);
-
-	compiler.addFunc(kFuncConvHost, FuncBuilder4<u32, void*, void*, void*, u32>());
-	const u16 start = pos;
-	//u32 excess = 0;
-	entry[start].count = 0;
-
-	X86GpVar cpu_var(compiler, kVarTypeIntPtr, "cpu");
-	compiler.setArg(0, cpu_var);
-	compiler.alloc(cpu_var);
-	m_enc->cpu_var = &cpu_var;
-
-	X86GpVar ls_var(compiler, kVarTypeIntPtr, "ls");
-	compiler.setArg(1, ls_var);
-	compiler.alloc(ls_var);
-	m_enc->ls_var = &ls_var;
-
-	X86GpVar imm_var(compiler, kVarTypeIntPtr, "imm");
-	compiler.setArg(2, imm_var);
-	compiler.alloc(imm_var);
-	m_enc->imm_var = &imm_var;
-
-	X86GpVar g_imm_var(compiler, kVarTypeIntPtr, "g_imm");
-	compiler.setArg(3, g_imm_var);
-	compiler.alloc(g_imm_var);
-	m_enc->g_imm_var = &g_imm_var;
-
-	X86GpVar pos_var(compiler, kVarTypeUInt32, "pos");
-	m_enc->pos_var = &pos_var;
-	X86GpVar addr_var(compiler, kVarTypeUInt32, "addr");
-	m_enc->addr = &addr_var;
-	X86GpVar qw0_var(compiler, kVarTypeUInt64, "qw0");
-	m_enc->qw0 = &qw0_var;
-	X86GpVar qw1_var(compiler, kVarTypeUInt64, "qw1");
-	m_enc->qw1 = &qw1_var;
-	X86GpVar qw2_var(compiler, kVarTypeUInt64, "qw2");
-	m_enc->qw2 = &qw2_var;
-
-	for (u32 i = 0; i < 16; i++)
-	{
-		m_enc->xmm_var[i].data = new X86XmmVar(compiler, kX86VarTypeXmm, fmt::format("reg_%d", i).c_str());
-	}
-
-	compiler.xor_(pos_var, pos_var);
-
-	while (true)
-	{
-		const be_t<u32> opcode = vm::ps3::read32(CPU.offset + pos * 4);
-		m_enc->do_finalize = false;
-		if (opcode.data())
-		{
-			//const u64 stamp1 = get_system_time();
-			// disasm for logging:
-			//dis_asm.dump_pc = pos * 4;
-			//(*SPU_instr::rrr_list)(&dis_asm, opcode);
-			//compiler.addComment(fmt::format("SPU data: PC=0x%05x %s", pos * 4, dis_asm.last_opcode.c_str()).c_str());
-			// compile single opcode:
-			(*SPU_instr::rrr_list)(m_enc.get(), opcode);
-			// force finalization between every slice using absolute alignment
-			/*if ((pos % 128 == 127) && !m_enc->do_finalize)
-			{
-				compiler.mov(pos_var, pos + 1);
-				m_enc->do_finalize = true;
-			}*/
-			entry[start].count++;
-			//time0 += get_system_time() - stamp1;
-		}
-		else
-		{
-			m_enc->do_finalize = true;
-		}
-		bool fin = m_enc->do_finalize;
-		//if (entry[pos]._valid == opcode)
-		//{
-		//	excess++;
-		//}
-		entry[pos]._valid = opcode;
-
-		if (fin) break;
-		CPU.PC += 4;
-		pos++;
-	}
-
-	m_enc->XmmRelease();
-
-	for (u32 i = 0; i < 16; i++)
-	{
-		assert(!m_enc->xmm_var[i].taken);
-		delete m_enc->xmm_var[i].data;
-		m_enc->xmm_var[i].data = nullptr;
-	}
-
-	//const u64 stamp1 = get_system_time();
-	compiler.ret(pos_var);
-	compiler.endFunc();
-	entry[start].pointer = compiler.make();
-	compiler.setLogger(nullptr); // crashes without it
-
-	//std::string log = fmt::format("========== START POSITION 0x%x ==========\n\n", start * 4);
-	//log += stringLogger.getString();
-	//if (!entry[start].pointer)
-	//{
-	//	LOG_ERROR(Log::SPU, "SPURecompilerCore::Compile(pos=0x%x) failed", start * sizeof(u32));
-	//	log += "========== FAILED ============\n\n";
-	//	Emu.Pause();
-	//}
-	//else
-	//{
-	//	log += fmt::format("========== COMPILED %d (excess %d), time: [start=%lld (decoding=%lld), finalize=%lld]\n\n",
-	//		entry[start].count, excess, stamp1 - stamp0, time0, get_system_time() - stamp1);
-	//}
-
-	//fs::file(fmt::format("SPUjit_%d.log", this->CPU.GetId()), fom::write | fom::create | (first ? fom::trunc : fom::append)).write(log.c_str(), log.size());
-
-	m_enc->compiler = nullptr;
-	first = false;
-}
-
-u32 SPURecompilerCore::DecodeMemory(const u32 address)
-{
-	const u32 pos = CPU.PC >> 2; // 0x0..0xffff
-	const auto _ls = vm::get_ptr<be_t<u32>>(CPU.offset);
-
-	assert(CPU.offset == address - CPU.PC && pos < 0x10000);
-
-	if (entry[pos].pointer)
-	{
-		bool is_valid = true;
-
-		// check data if necessary (hard way)
-		if (need_check)
-		{
-			for (u32 i = 0; i < 0x10000; i++)
-			{
-				if (entry[i]._valid.data() && entry[i]._valid != _ls[i])
-				{
-					is_valid = false;
-					break;
-				}
-			}
-
-			need_check = false;
-		}
-
-		// invalidate if necessary
-		if (!is_valid)
-		{
-			for (u32 i = 0; i < 0x10000; i++)
-			{
-				if (!entry[i].pointer) continue;
-
-				if (!entry[i]._valid.data() || entry[i]._valid != _ls[i] || (i + entry[i].count > pos && i < pos + entry[pos].count))
-				{
-					m_jit->release(entry[i].pointer);
-					entry[i].pointer = nullptr;
-
-					for (u32 j = i; j < i + entry[i].count; j++)
-					{
-						entry[j]._valid = 0;
-					}
-
-					//need_check = true;
-				}
-			}
-		}
-	}
-
-	if (!entry[pos].pointer)
-	{
-		Compile(pos);
-	}
-
-	if (!entry[pos].pointer)
-	{
-		return 0;
-	}
-
-	const auto func = asmjit_cast<u32(*)(SPUThread* _cpu, be_t<u32>* _ls, const void* _imm, const void* _g_imm)>(entry[pos].pointer);
-
-	u32 res = func(&CPU, _ls, imm_table.data(), &g_spu_imm);
-
-	if (res & 0x1000000)
-	{
-		CPU.halt();
-		res &= ~0x1000000;
-	}
-
-	if (res & 0x2000000)
-	{
-		need_check = true;
-		res &= ~0x2000000;
-	}
-
-	if ((res - 1) == (CPU.PC >> 2))
-	{
-		return 4;
-	}
-	else
-	{
-		CPU.PC = (res << 2) - 4;
-		return 0;
-	}
-}
-
-#define c (*compiler)
-
-#define cpu_offset(x) static_cast<s32>(reinterpret_cast<uintptr_t>(&(((SPUThread*)0)->x)))
-#define cpu_xmm(x) oword_ptr(*cpu_var, cpu_offset(x))
-#define cpu_qword(x) qword_ptr(*cpu_var, cpu_offset(x))
-#define cpu_dword(x) dword_ptr(*cpu_var, cpu_offset(x))
-#define cpu_word(x) word_ptr(*cpu_var, cpu_offset(x))
-#define cpu_byte(x) byte_ptr(*cpu_var, cpu_offset(x))
-
-#define g_imm_offset(x) static_cast<s32>(reinterpret_cast<uintptr_t>(&(((g_spu_imm_table_t*)0)->x)))
-#define g_imm_xmm(x) oword_ptr(*g_imm_var, g_imm_offset(x))
-#define g_imm2_xmm(x, y) oword_ptr(*g_imm_var, y, 0, g_imm_offset(x))
-
-
-#define LOG_OPCODE(...) //ConLog.Write("Compiled "__FUNCTION__"(): "__VA_ARGS__)
-
-#define LOG3_OPCODE(...) //ConLog.Write("Linked "__FUNCTION__"(): "__VA_ARGS__)
-
-#define LOG4_OPCODE(...) //c.addComment(fmt::format("SPU info: "__FUNCTION__"(): "__VA_ARGS__).c_str())
-
-#define WRAPPER_BEGIN(a0, a1, a2) struct opwr_##a0 \
-{ \
-	static void opcode(SPUThread* CPU, u32 a0, u32 a1, u32 a2) \
-{
-
-#define WRAPPER_END(a0, a1, a2) /*LOG2_OPCODE();*/ } \
-}; \
-	/*XmmRelease();*/ \
-	if (#a0[0] == 'r') XmmInvalidate(a0); \
-	if (#a1[0] == 'r') XmmInvalidate(a1); \
-	if (#a2[0] == 'r') XmmInvalidate(a2); \
-	X86CallNode* call##a0 = c.call(imm_ptr(reinterpret_cast<void*>(&opwr_##a0::opcode)), kFuncConvHost, FuncBuilder4<void, SPUThread*, u32, u32, u32>()); \
-	call##a0->setArg(0, *cpu_var); \
-	call##a0->setArg(1, imm_u(a0)); \
-	call##a0->setArg(2, imm_u(a1)); \
-	call##a0->setArg(3, imm_u(a2)); \
-	LOG3_OPCODE(/*#a0"=%d, "#a1"=%d, "#a2"=%d, "#a3"=%d", a0, a1, a2, a3*/);
-
-const SPURecompiler::XmmLink& SPURecompiler::XmmAlloc(s8 pref) // get empty xmm register
-{
-	if (pref >= 0) for (u32 i = 0; i < 16; i++)
-	{
-		if ((xmm_var[i].reg == pref) && !xmm_var[i].taken)
-		{
-			xmm_var[i].taken = true;
-			xmm_var[i].got = false;
-			xmm_var[i].access = 0;
-			LOG4_OPCODE("pref(%d) reg taken (i=%d)", pref, i);
-			return xmm_var[i];
-		}
-	}
-
-	for (u32 i = 0; i < 16; i++)
-	{
-		if ((xmm_var[i].reg == -1) && !xmm_var[i].taken)
-		{
-			xmm_var[i].taken = true;
-			xmm_var[i].got = false;
-			xmm_var[i].access = 0;
-			LOG4_OPCODE("free reg taken (i=%d)", i);
-			return xmm_var[i];
-		}
-	}
-
-	int last = -1, max = -1;
-	for (u32 i = 0; i < 16; i++)
-	{
-		if (!xmm_var[i].taken)
-		{
-			if ((int)xmm_var[i].access > max)
-			{
-				last = i;
-				max = xmm_var[i].access;
-			}
-		}
-	}
-
-	if (last >= 0)
-	{
-		// (saving cached data?)
-		//c.movdqa(cpu_xmm(GPR[xmm_var[last].reg]), *xmm_var[last].data);
-		xmm_var[last].taken = true;
-		xmm_var[last].got = false;
-		LOG4_OPCODE("cached reg taken (i=%d): GPR[%d] lost", last, xmm_var[last].reg);
-		xmm_var[last].reg = -1; // ???
-		xmm_var[last].access = 0;
-		return xmm_var[last];
-	}
-
-	throw EXCEPTION("Failure");
-}
-
-const SPURecompiler::XmmLink* SPURecompiler::XmmRead(const s8 reg) const // get xmm register with specific SPU reg or nullptr
-{
-	assert(reg >= 0);
-	for (u32 i = 0; i < 16; i++)
-	{
-		if (xmm_var[i].reg == reg)
-		{
-			//assert(!xmm_var[i].got);
-			//if (xmm_var[i].got) throw EXCEPTION("Wrong reuse");
-			LOG4_OPCODE("GPR[%d] has been read (i=%d)", reg, i);
-			xmm_var[i].access++;
-			return &xmm_var[i];
-		}
-	}
-	LOG4_OPCODE("GPR[%d] not found", reg);
-	return nullptr;
-}
-
-const SPURecompiler::XmmLink& SPURecompiler::XmmGet(s8 reg, s8 target) // get xmm register with specific SPU reg
-{
-	assert(reg >= 0);
-	const XmmLink* res = nullptr;
-	if (reg == target)
-	{
-		for (u32 i = 0; i < 16; i++)
-		{
-			if (xmm_var[i].reg == reg)
-			{
-				res = &xmm_var[i];
-				if (xmm_var[i].taken) throw EXCEPTION("xmm_var is taken");
-				xmm_var[i].taken = true;
-				xmm_var[i].got = false;
-				//xmm_var[i].reg = -1;
-				for (u32 j = i + 1; j < 16; j++)
-				{
-					if (xmm_var[j].reg == reg) throw EXCEPTION("xmm_var duplicate");
-				}
-				LOG4_OPCODE("cached GPR[%d] used (i=%d)", reg, i);
-				break;
-			}
-		}
-	}
-	if (!res)
-	{
-		res = &XmmAlloc(target);
-		/*if (target != res->reg)
-		{
-		c.movdqa(*res->data, cpu_xmm(GPR[reg]));
-		}
-		else*/
-		{
-			if (const XmmLink* source = XmmRead(reg))
-			{
-				c.movdqa(*res->data, source->read());
-			}
-			else
-			{
-				c.movdqa(*res->data, cpu_xmm(GPR[reg]));
-			}
-		}
-		const_cast<XmmLink*>(res)->reg = -1; // ???
-		LOG4_OPCODE("* cached GPR[%d] not found", reg);
-	}
-	return *res;
-}
-
-const SPURecompiler::XmmLink& SPURecompiler::XmmCopy(const XmmLink& from, s8 pref) // XmmAlloc + mov
-{
-	const XmmLink* res = &XmmAlloc(pref);
-	c.movdqa(*res->data, *from.data);
-	const_cast<XmmLink*>(res)->reg = -1; // ???
-	LOG4_OPCODE("*");
-	return *res;
-}
-
-void SPURecompiler::XmmInvalidate(const s8 reg) // invalidate cached register
-{
-	assert(reg >= 0);
-	for (u32 i = 0; i < 16; i++)
-	{
-		if (xmm_var[i].reg == reg)
-		{
-			if (xmm_var[i].taken) throw EXCEPTION("xmm_var is taken");
-			LOG4_OPCODE("GPR[%d] invalidated (i=%d)", reg, i);
-			xmm_var[i].reg = -1;
-			xmm_var[i].access = 0;
-		}
-	}
-}
-
-void SPURecompiler::XmmFinalize(const XmmLink& var, s8 reg)
-{
-	// invalidation
-	if (reg >= 0) for (u32 i = 0; i < 16; i++)
-	{
-		if (xmm_var[i].reg == reg)
-		{
-			LOG4_OPCODE("GPR[%d] invalidated (i=%d)", reg, i);
-			xmm_var[i].reg = -1;
-			xmm_var[i].access = 0;
-		}
-	}
-	for (u32 i = 0; i < 16; i++)
-	{
-		if (xmm_var[i].data == var.data)
-		{
-			assert(xmm_var[i].taken);
-			// save immediately:
-			if (reg >= 0)
-			{
-				c.movdqa(cpu_xmm(GPR[reg]), *xmm_var[i].data);
-			}
-			else
-			{
-			}
-			LOG4_OPCODE("GPR[%d] finalized (i=%d), GPR[%d] replaced", reg, i, xmm_var[i].reg);
-			// (to disable caching:)
-			//reg = -1;
-			xmm_var[i].reg = reg;
-			xmm_var[i].taken = false;
-			xmm_var[i].got = false;
-			xmm_var[i].access = 0;
-			return;
-		}
-	}
-	assert(false);
-}
-
-void SPURecompiler::XmmRelease()
-{
-	for (u32 i = 0; i < 16; i++)
-	{
-		if (xmm_var[i].reg >= 0)
-		{
-			//c.movdqa(cpu_xmm(GPR[xmm_var[i].reg]), *xmm_var[i].data);
-			LOG4_OPCODE("GPR[%d] released (i=%d)", xmm_var[i].reg, i);
-			xmm_var[i].reg = -1;
-			xmm_var[i].access = 0;
-		}
-	}
-}
-
-X86Mem SPURecompiler::XmmConst(v128 data)
-{
-	s32 shift = 0;
-
-	for (; shift < rec.imm_table.size(); shift++)
-	{
-		if (rec.imm_table[shift] == data)
-		{
-			return oword_ptr(*imm_var, shift * sizeof(v128));
-		}
-	}
-
-	rec.imm_table.push_back(data);
-	return oword_ptr(*imm_var, shift * sizeof(v128));
-}
-
-
-void SPURecompiler::STOP(u32 code)
-{
-	struct STOP_wrapper
-	{
-		static void STOP(SPUThread* CPU, u32 code)
-		{
-			CPU->stop_and_signal(code);
-			LOG2_OPCODE();
-		}
-	};
-	c.mov(cpu_dword(PC), CPU.PC);
-	X86CallNode* call = c.call(imm_ptr(reinterpret_cast<void*>(&STOP_wrapper::STOP)), kFuncConvHost, FuncBuilder2<void, SPUThread*, u32>());
-	call->setArg(0, *cpu_var);
-	call->setArg(1, imm_u(code));
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::LNOP()
-{
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SYNC(u32 Cbit)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	// This instruction must be used following a store instruction that modifies the instruction stream.
-	c.mfence();
-	c.mov(*pos_var, (CPU.PC >> 2) + 1 + 0x2000000);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DSYNC()
-{
-	// This instruction forces all earlier load, store, and channel instructions to complete before proceeding.
-	c.mfence();
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MFSPR(u32 rt, u32 sa)
-{
-	return UNK("MFSPR");
-}
-
-void SPURecompiler::RDCH(u32 rt, u32 ra)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	WRAPPER_BEGIN(rt, ra, zz);
-	CPU->GPR[rt] = v128::from32r(CPU->get_ch_value(ra));
-	WRAPPER_END(rt, ra, 0);
-	// TODO
-}
-
-void SPURecompiler::RCHCNT(u32 rt, u32 ra)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	WRAPPER_BEGIN(rt, ra, zz);
-	CPU->GPR[rt] = v128::from32r(CPU->get_ch_count(ra));
-	WRAPPER_END(rt, ra, 0);
-	// TODO
-}
-
-void SPURecompiler::SF(u32 rt, u32 ra, u32 rb)
-{
-	// sub from
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.psubd(vb.get(), va->read());
-	}
-	else
-	{
-		c.psubd(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::OR(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.por(vb.get(), va->read());
-	}
-	else
-	{
-		c.por(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BG(u32 rt, u32 ra, u32 rb)
-{
-	// compare if-greater-than
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from32p(0x80000000)));
-	c.pxor(va.get(), vi.get());
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pxor(vi.get(), vb->read());
-	}
-	else
-	{
-		c.pxor(vi.get(), cpu_xmm(GPR[rb]));
-	}
-	c.pcmpgtd(va.get(), vi.get());
-	c.paddd(va.get(), XmmConst(v128::from32p(1)));
-	XmmFinalize(va, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SFH(u32 rt, u32 ra, u32 rb)
-{
-	// sub from (halfword)
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.psubw(vb.get(), va->read());
-	}
-	else
-	{
-		c.psubw(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::NOR(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (ra != rb)
-	{
-		if (const XmmLink* vb = XmmRead(rb))
-		{
-			c.por(va.get(), vb->read());
-		}
-		else
-		{
-			c.por(va.get(), cpu_xmm(GPR[rb]));
-		}
-	}
-	c.pxor(va.get(), XmmConst(v128::from32p(0xffffffff)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ABSDB(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = XmmGet(rb);
-	const XmmLink& vm = XmmCopy(va);
-	c.pmaxub(va.get(), vb.get());
-	c.pminub(vb.get(), vm.get());
-	c.psubb(va.get(), vb.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(vm);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROT(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 4; i++)
-	{
-		c.mov(qw0->r32(), cpu_dword(GPR[ra]._u32[i]));
-		c.mov(*addr, cpu_dword(GPR[rb]._u32[i]));
-		c.rol(qw0->r32(), *addr);
-		c.mov(cpu_dword(GPR[rt]._u32[i]), qw0->r32());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTM(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 4; i++)
-	{
-		c.mov(qw0->r32(), cpu_dword(GPR[ra]._u32[i]));
-		c.mov(*addr, cpu_dword(GPR[rb]._u32[i]));
-		c.neg(*addr);
-		c.shr(*qw0, *addr);
-		c.mov(cpu_dword(GPR[rt]._u32[i]), qw0->r32());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTMA(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 4; i++)
-	{
-		c.movsxd(*qw0, cpu_dword(GPR[ra]._u32[i]));
-		c.mov(*addr, cpu_dword(GPR[rb]._u32[i]));
-		c.neg(*addr);
-		c.sar(*qw0, *addr);
-		c.mov(cpu_dword(GPR[rt]._u32[i]), qw0->r32());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHL(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 4; i++)
-	{
-		c.mov(qw0->r32(), cpu_dword(GPR[ra]._u32[i]));
-		c.mov(*addr, cpu_dword(GPR[rb]._u32[i]));
-		c.shl(*qw0, *addr);
-		c.mov(cpu_dword(GPR[rt]._u32[i]), qw0->r32());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTH(u32 rt, u32 ra, u32 rb) //nf
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 8; i++)
-	{
-		c.movzx(qw0->r32(), cpu_word(GPR[ra]._u16[i]));
-		c.movzx(*addr, cpu_word(GPR[rb]._u16[i]));
-		c.rol(qw0->r16(), *addr);
-		c.mov(cpu_word(GPR[rt]._u16[i]), qw0->r16());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTHM(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 8; i++)
-	{
-		c.movzx(qw0->r32(), cpu_word(GPR[ra]._u16[i]));
-		c.movzx(*addr, cpu_word(GPR[rb]._u16[i]));
-		c.neg(*addr);
-		c.shr(qw0->r32(), *addr);
-		c.mov(cpu_word(GPR[rt]._u16[i]), qw0->r16());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTMAH(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 8; i++)
-	{
-		c.movsx(qw0->r32(), cpu_word(GPR[ra]._u16[i]));
-		c.movzx(*addr, cpu_word(GPR[rb]._u16[i]));
-		c.neg(*addr);
-		c.sar(qw0->r32(), *addr);
-		c.mov(cpu_word(GPR[rt]._u16[i]), qw0->r16());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLH(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	for (u32 i = 0; i < 8; i++)
-	{
-		c.movzx(qw0->r32(), cpu_word(GPR[ra]._u16[i]));
-		c.movzx(*addr, cpu_word(GPR[rb]._u16[i]));
-		c.shl(qw0->r32(), *addr);
-		c.mov(cpu_word(GPR[rt]._u16[i]), qw0->r16());
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTI(u32 rt, u32 ra, s32 i7)
-{
-	// rotate left
-	const int s = i7 & 0x1f;
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& v1 = XmmCopy(va);
-	c.pslld(va.get(), s);
-	c.psrld(v1.get(), 32 - s);
-	c.por(va.get(), v1.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(v1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTMI(u32 rt, u32 ra, s32 i7)
-{
-	// shift right logical
-	const int s = (0 - i7) & 0x3f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psrld(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTMAI(u32 rt, u32 ra, s32 i7)
-{
-	// shift right arithmetical
-	const int s = (0 - i7) & 0x3f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psrad(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLI(u32 rt, u32 ra, s32 i7)
-{
-	// shift left
-	const int s = i7 & 0x3f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pslld(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTHI(u32 rt, u32 ra, s32 i7)
-{
-	// rotate left (halfword)
-	const int s = i7 & 0xf;
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& v1 = XmmCopy(va);
-	c.psllw(va.get(), s);
-	c.psrlw(v1.get(), 16 - s);
-	c.por(va.get(), v1.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(v1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTHMI(u32 rt, u32 ra, s32 i7)
-{
-	// shift right logical
-	const int s = (0 - i7) & 0x1f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psrlw(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTMAHI(u32 rt, u32 ra, s32 i7)
-{
-	// shift right arithmetical (halfword)
-	const int s = (0 - i7) & 0x1f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psraw(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLHI(u32 rt, u32 ra, s32 i7)
-{
-	// shift left (halfword)
-	const int s = i7 & 0x1f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psllw(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::A(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.paddd(vb.get(), va->read());
-	}
-	else
-	{
-		c.paddd(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::AND(u32 rt, u32 ra, u32 rb)
-{
-	// and
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.pand(vb.get(), va->read());
-	}
-	else
-	{
-		c.pand(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CG(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = XmmGet(rb);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from32p(0x80000000)));
-	c.paddd(vb.get(), va.get());
-	c.pxor(va.get(), vi.get());
-	c.pxor(vb.get(), vi.get());
-	c.pcmpgtd(va.get(), vb.get());
-	c.psrld(va.get(), 31);
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::AH(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.paddw(va.get(), vb->read());
-	}
-	else
-	{
-		c.paddw(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::NAND(u32 rt, u32 ra, u32 rb)
-{
-	// nand
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pand(va.get(), vb->read());
-	}
-	else
-	{
-		c.pand(va.get(), cpu_xmm(GPR[rb]));
-	}
-	c.pxor(va.get(), XmmConst(v128::from32p(0xffffffff)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::AVGB(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.pavgb(vb.get(), va->read());
-	}
-	else
-	{
-		c.pavgb(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-}
-
-void SPURecompiler::MTSPR(u32 rt, u32 sa)
-{
-}
-
-void SPURecompiler::WRCH(u32 ra, u32 rt)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	WRAPPER_BEGIN(ra, rt, yy);
-	CPU->set_ch_value(ra, CPU->GPR[rt]._u32[3]);
-	WRAPPER_END(ra, rt, 0);
-	// TODO
-
-	/*XmmInvalidate(rt);
-
-	X86GpVar v(c, kVarTypeUInt32);
-	c.mov(v, cpu_dword(GPR[rt]._u32[3]));
-	switch (ra)
-	{
-	case MFC_LSA:
-	c.mov(cpu_dword(MFC1.LSA.m_value[0]), v);
-	break;
-
-	case MFC_EAH:
-	c.mov(cpu_dword(MFC1.EAH.m_value[0]), v);
-	break;
-
-	case MFC_EAL:
-	c.mov(cpu_dword(MFC1.EAL.m_value[0]), v);
-	break;
-
-	case MFC_Size:
-	c.mov(cpu_word(MFC1.Size_Tag.m_val16[1]), v);
-	break;
-
-	case MFC_TagID:
-	c.mov(cpu_word(MFC1.Size_Tag.m_val16[0]), v);
-	break;
-
-	default:
-	{
-	X86X64CallNode* call = c.call(imm_ptr(reinterpret_cast<void*>(&WRCH_wrapper::WRCH)), kFuncConvHost, FuncBuilder2<FnVoid, u32, u32>());
-	call->setArg(0, imm_u(ra));
-	call->setArg(1, v);
-	}
-	}*/
-}
-
-void SPURecompiler::BIZ(u32 intr, u32 rt, u32 ra)
-{
-	switch (intr & 0x30)
-	{
-	case 0: break;
-	default: return UNK("BIZ");
-	}
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, CPU.PC + 4);
-	c.mov(*pos_var, cpu_dword(GPR[ra]._u32[3]));
-	if (ra) c.or_(*pos_var, 0x2000000 << 2); // rude (check if not LR)
-	c.cmp(cpu_dword(GPR[rt]._u32[3]), 0);
-	c.cmovne(*pos_var, *addr);
-	c.shr(*pos_var, 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BINZ(u32 intr, u32 rt, u32 ra)
-{
-	switch (intr & 0x30)
-	{
-	case 0: break;
-	default: return UNK("BINZ");
-	}
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, CPU.PC + 4);
-	c.mov(*pos_var, cpu_dword(GPR[ra]._u32[3]));
-	if (ra) c.or_(*pos_var, 0x2000000 << 2); // rude (check if not LR)
-	c.cmp(cpu_dword(GPR[rt]._u32[3]), 0);
-	c.cmove(*pos_var, *addr);
-	c.shr(*pos_var, 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BIHZ(u32 intr, u32 rt, u32 ra)
-{
-	switch (intr & 0x30)
-	{
-	case 0: break;
-	default: return UNK("BIHZ");
-	}
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, CPU.PC + 4);
-	c.mov(*pos_var, cpu_dword(GPR[ra]._u32[3]));
-	if (ra) c.or_(*pos_var, 0x2000000 << 2); // rude (check if not LR)
-	c.cmp(cpu_word(GPR[rt]._u16[6]), 0);
-	c.cmovne(*pos_var, *addr);
-	c.shr(*pos_var, 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BIHNZ(u32 intr, u32 rt, u32 ra)
-{
-	switch (intr & 0x30)
-	{
-	case 0: break;
-	default: return UNK("BIHNZ");
-	}
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, CPU.PC + 4);
-	c.mov(*pos_var, cpu_dword(GPR[ra]._u32[3]));
-	if (ra) c.or_(*pos_var, 0x2000000 << 2); // rude (check if not LR)
-	c.cmp(cpu_word(GPR[rt]._u16[6]), 0);
-	c.cmove(*pos_var, *addr);
-	c.shr(*pos_var, 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::STOPD(u32 rc, u32 ra, u32 rb)
-{
-	return UNK("STOPD");
-}
-
-void SPURecompiler::STQX(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	if (ra == rb)
-	{
-		c.add(*addr, *addr);
-	}
-	else
-	{
-		c.add(*addr, cpu_dword(GPR[rb]._u32[3]));
-	}
-	c.and_(*addr, 0x3fff0);
-
-	/*const XmmLink& vt = XmmGet(rt);
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	c.movdqa(oword_ptr(*ls_var, *addr), vt.get());
-	XmmFinalize(vt);*/
-
-	c.mov(*qw0, cpu_qword(GPR[rt]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[rt]._u64[1]));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(qword_ptr(*ls_var, *addr, 0, 0), *qw1);
-	c.mov(qword_ptr(*ls_var, *addr, 0, 8), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BI(u32 intr, u32 ra)
-{
-	switch (intr & 0x30)
-	{
-	case 0: break;
-	default: return UNK("BI");
-	}
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*pos_var, cpu_dword(GPR[ra]._u32[3]));
-	if (ra) c.or_(*pos_var, 0x2000000 << 2); // rude (check if not LR)
-	c.shr(*pos_var, 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BISL(u32 intr, u32 rt, u32 ra)
-{
-	switch (intr & 0x30)
-	{
-	case 0: break;
-	default: return UNK("BISL");
-	}
-
-	XmmInvalidate(rt);
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.xor_(*pos_var, *pos_var);
-	c.mov(cpu_dword(GPR[rt]._u32[0]), *pos_var);
-	c.mov(cpu_dword(GPR[rt]._u32[1]), *pos_var);
-	c.mov(cpu_dword(GPR[rt]._u32[2]), *pos_var);
-	c.mov(*pos_var, cpu_dword(GPR[ra]._u32[3]));
-	c.mov(cpu_dword(GPR[rt]._u32[3]), CPU.PC + 4);
-	c.shr(*pos_var, 2);
-	c.or_(*pos_var, 0x2000000);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::IRET(u32 ra)
-{
-	return UNK("IRET");
-}
-
-void SPURecompiler::BISLED(u32 intr, u32 rt, u32 ra)
-{
-	return UNK("BISLED");
-}
-
-void SPURecompiler::HBR(u32 p, u32 ro, u32 ra)
-{
-	LOG_OPCODE();
-}
-
-void SPURecompiler::GB(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pshufb(va.get(), XmmConst(v128::fromV(_mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 12, 8, 4, 0))));
-	c.psllq(va.get(), 7);
-	c.pmovmskb(*addr, va.get());
-	c.pxor(va.get(), va.get());
-	c.pinsrw(va.get(), *addr, 6);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::GBH(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pshufb(va.get(), XmmConst(v128::fromV(_mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 14, 12, 10, 8, 6, 4, 2, 0))));
-	c.psllq(va.get(), 7);
-	c.pmovmskb(*addr, va.get());
-	c.pxor(va.get(), va.get());
-	c.pinsrw(va.get(), *addr, 6);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::GBB(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psllq(va.get(), 7);
-	c.pmovmskb(*addr, va.get());
-	c.pxor(va.get(), va.get());
-	c.pinsrw(va.get(), *addr, 6);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FSM(u32 rt, u32 ra)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.and_(*addr, 0xf);
-	c.shl(*addr, 4);
-	c.movdqa(vr.get(), g_imm2_xmm(fsm[0], *addr));
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FSMH(u32 rt, u32 ra)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.and_(*addr, 0xff);
-	c.shl(*addr, 4);
-	c.movdqa(vr.get(), g_imm2_xmm(fsmh[0], *addr));
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FSMB(u32 rt, u32 ra)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.and_(*addr, 0xffff);
-	c.shl(*addr, 4);
-	c.movdqa(vr.get(), g_imm2_xmm(fsmb[0], *addr));
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FREST(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.rcpps(va.get(), va.get());
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FRSQEST(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.andps(va.get(), XmmConst(v128::from32p(0x7fffffff))); // abs
-	c.rsqrtps(va.get(), va.get());
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::LQX(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	if (ra == rb)
-	{
-		c.add(*addr, *addr);
-	}
-	else
-	{
-		c.add(*addr, cpu_dword(GPR[rb]._u32[3]));
-	}
-	c.and_(*addr, 0x3fff0);
-
-	/*const XmmLink& vt = XmmAlloc(rt);
-	c.movdqa(vt.get(), oword_ptr(*ls_var, *addr));
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	XmmFinalize(vt, rt);*/
-
-	c.mov(*qw0, qword_ptr(*ls_var, *addr, 0, 0));
-	c.mov(*qw1, qword_ptr(*ls_var, *addr, 0, 8));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQBYBI(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.and_(*addr, 0xf << 3);
-	c.shl(*addr, 1);
-	c.pshufb(va.get(), g_imm2_xmm(rldq_pshufb[0], *addr));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQMBYBI(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.shr(*addr, 3);
-	c.neg(*addr);
-	c.and_(*addr, 0x1f);
-	c.shl(*addr, 4);
-	c.pshufb(va.get(), g_imm2_xmm(srdq_pshufb[0], *addr));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLQBYBI(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.and_(*addr, 0x1f << 3);
-	c.shl(*addr, 1);
-	c.pshufb(va.get(), g_imm2_xmm(sldq_pshufb[0], *addr));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CBX(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-	}
-	else if (ra == rb)
-	{
-		c.add(*addr, *addr);
-	}
-	else
-	{
-		c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
-	}
-	c.not_(*addr);
-	c.and_(*addr, 0xf);
-	const XmmLink& vr = XmmAlloc(rt);
-	c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))));
-	XmmFinalize(vr, rt);
-	XmmInvalidate(rt);
-	c.mov(byte_ptr(*cpu_var, *addr, 0, cpu_offset(GPR[rt])), 0x03);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CHX(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-	}
-	else if (ra == rb)
-	{
-		c.add(*addr, *addr);
-	}
-	else
-	{
-		c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
-	}
-	c.not_(*addr);
-	c.and_(*addr, 0xe);
-	const XmmLink& vr = XmmAlloc(rt);
-	c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))));
-	XmmFinalize(vr, rt);
-	XmmInvalidate(rt);
-	c.mov(word_ptr(*cpu_var, *addr, 0, cpu_offset(GPR[rt])), 0x0203);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CWX(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-	}
-	else if (ra == rb)
-	{
-		c.add(*addr, *addr);
-	}
-	else
-	{
-		c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
-	}
-	c.not_(*addr);
-	c.and_(*addr, 0xc);
-	const XmmLink& vr = XmmAlloc(rt);
-	c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))));
-	XmmFinalize(vr, rt);
-	XmmInvalidate(rt);
-	c.mov(dword_ptr(*cpu_var, *addr, 0, cpu_offset(GPR[rt])), 0x00010203);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CDX(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-	}
-	else if (ra == rb)
-	{
-		c.add(*addr, *addr);
-	}
-	else
-	{
-		c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
-	}
-	c.test(*addr, 0x8);
-	const XmmLink& vr = XmmAlloc(rt);
-	Label p1(c), p2(c);
-	c.jnz(p1);
-	c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x00010203, 0x04050607, 0x18191a1b, 0x1c1d1e1f))));
-	c.jmp(p2);
-	c.bind(p1);
-	c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x00010203, 0x04050607))));
-	c.bind(p2);
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQBI(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, cpu_qword(GPR[ra]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[ra]._u64[1]));
-	c.mov(*qw2, *qw0);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.and_(*addr, 7);
-	c.shld(*qw0, *qw1, *addr);
-	c.shld(*qw1, *qw2, *addr);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQMBI(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, cpu_qword(GPR[ra]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[ra]._u64[1]));
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.neg(*addr);
-	c.and_(*addr, 7);
-	c.shrd(*qw0, *qw1, *addr);
-	c.shr(*qw1, *addr);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLQBI(u32 rt, u32 ra, u32 rb)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, cpu_qword(GPR[ra]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[ra]._u64[1]));
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.and_(*addr, 7);
-	c.shld(*qw1, *qw0, *addr);
-	c.shl(*qw0, *addr);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQBY(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.and_(*addr, 0xf);
-	c.shl(*addr, 4);
-	c.pshufb(va.get(), g_imm2_xmm(rldq_pshufb[0], *addr));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQMBY(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.neg(*addr);
-	c.and_(*addr, 0x1f);
-	c.shl(*addr, 4);
-	c.pshufb(va.get(), g_imm2_xmm(srdq_pshufb[0], *addr));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLQBY(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.and_(*addr, 0x1f);
-	c.shl(*addr, 4);
-	c.pshufb(va.get(), g_imm2_xmm(sldq_pshufb[0], *addr));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ORX(u32 rt, u32 ra)
-{
-	XmmInvalidate(rt);
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[0]));
-	c.or_(*addr, cpu_dword(GPR[ra]._u32[1]));
-	c.or_(*addr, cpu_dword(GPR[ra]._u32[2]));
-	c.or_(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.mov(cpu_dword(GPR[rt]._u32[3]), *addr);
-	c.xor_(*addr, *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[0]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[1]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[2]), *addr);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CBD(u32 rt, u32 ra, s32 i7)
-{
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-		const XmmLink& vr = XmmAlloc(rt);
-		v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
-		value.u8r[i7 & 0xf] = 0x03;
-		c.movdqa(vr.get(), XmmConst(value));
-		XmmFinalize(vr, rt);
-	}
-	else
-	{
-		c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-		c.add(*addr, i7);
-		c.not_(*addr);
-		c.and_(*addr, 0xf);
-		const XmmLink& vr = XmmAlloc(rt);
-		c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))));
-		XmmFinalize(vr, rt);
-		XmmInvalidate(rt);
-		c.mov(byte_ptr(*cpu_var, *addr, 0, cpu_offset(GPR[rt])), 0x03);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CHD(u32 rt, u32 ra, s32 i7)
-{
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-		const XmmLink& vr = XmmAlloc(rt);
-		v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
-		value.u16r[(i7 >> 1) & 0x7] = 0x0203;
-		c.movdqa(vr.get(), XmmConst(value));
-		XmmFinalize(vr, rt);
-	}
-	else
-	{
-		c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-		c.add(*addr, i7);
-		c.not_(*addr);
-		c.and_(*addr, 0xe);
-		const XmmLink& vr = XmmAlloc(rt);
-		c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))));
-		XmmFinalize(vr, rt);
-		XmmInvalidate(rt);
-		c.mov(word_ptr(*cpu_var, *addr, 0, cpu_offset(GPR[rt])), 0x0203);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CWD(u32 rt, u32 ra, s32 i7)
-{
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-		const XmmLink& vr = XmmAlloc(rt);
-		v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
-		value.u32r[(i7 >> 2) & 0x3] = 0x00010203;
-		c.movdqa(vr.get(), XmmConst(value));
-		XmmFinalize(vr, rt);
-	}
-	else
-	{
-		c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-		c.add(*addr, i7);
-		c.not_(*addr);
-		c.and_(*addr, 0xc);
-		const XmmLink& vr = XmmAlloc(rt);
-		c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))));
-		XmmFinalize(vr, rt);
-		XmmInvalidate(rt);
-		c.mov(dword_ptr(*cpu_var, *addr, 0, cpu_offset(GPR[rt])), 0x00010203);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CDD(u32 rt, u32 ra, s32 i7)
-{
-	if (ra == 1)
-	{
-		// assuming that SP % 16 is always zero
-		const XmmLink& vr = XmmAlloc(rt);
-		v128 value = v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f));
-		value.u64r[(i7 >> 3) & 0x1] = 0x0001020304050607ull;
-		c.movdqa(vr.get(), XmmConst(value));
-		XmmFinalize(vr, rt);
-	}
-	else
-	{
-		c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-		c.add(*addr, i7);
-		c.test(*addr, 0x8);
-		const XmmLink& vr = XmmAlloc(rt);
-		Label p1(c), p2(c);
-		c.jnz(p1);
-		c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x00010203, 0x04050607, 0x18191a1b, 0x1c1d1e1f))));
-		c.jmp(p2);
-		c.bind(p1);
-		c.movdqa(vr.get(), XmmConst(v128::fromV(_mm_set_epi32(0x10111213, 0x14151617, 0x00010203, 0x04050607))));
-		c.bind(p2);
-		XmmFinalize(vr, rt);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQBII(u32 rt, u32 ra, s32 i7)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, cpu_qword(GPR[ra]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[ra]._u64[1]));
-	c.mov(*qw2, *qw0);
-	c.shld(*qw0, *qw1, i7 & 0x7);
-	c.shld(*qw1, *qw2, i7 & 0x7);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQMBII(u32 rt, u32 ra, s32 i7)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, cpu_qword(GPR[ra]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[ra]._u64[1]));
-	c.shrd(*qw0, *qw1, (0 - i7) & 0x7);
-	c.shr(*qw1, (0 - i7) & 0x7);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLQBII(u32 rt, u32 ra, s32 i7)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, cpu_qword(GPR[ra]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[ra]._u64[1]));
-	c.shld(*qw1, *qw0, i7 & 0x7);
-	c.shl(*qw0, i7 & 0x7);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQBYI(u32 rt, u32 ra, s32 i7)
-{
-	const int s = i7 & 0xf;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.palignr(va.get(), va.get(), 16 - s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ROTQMBYI(u32 rt, u32 ra, s32 i7)
-{
-	const int s = (0 - i7) & 0x1f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psrldq(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHLQBYI(u32 rt, u32 ra, s32 i7)
-{
-	const int s = i7 & 0x1f;
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pslldq(va.get(), s);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::NOP(u32 rt)
-{
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGT(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pcmpgtd(va.get(), vb->read());
-	}
-	else
-	{
-		c.pcmpgtd(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XOR(u32 rt, u32 ra, u32 rb)
-{
-	// xor
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pxor(va.get(), vb->read());
-	}
-	else
-	{
-		c.pxor(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGTH(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pcmpgtw(va.get(), vb->read());
-	}
-	else
-	{
-		c.pcmpgtw(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::EQV(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb, rt);
-	c.pxor(vb.get(), XmmConst(v128::from32p(0xffffffff)));
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.pxor(vb.get(), va->read());
-	}
-	else
-	{
-		c.pxor(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGTB(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pcmpgtb(va.get(), vb->read());
-	}
-	else
-	{
-		c.pcmpgtb(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SUMB(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from8p(1)));
-	c.pmaddubsw(va.get(), vi.get());
-	c.pmaddubsw(vb.get(), vi.get());
-	c.phaddw(va.get(), vb.get());
-	c.pshufb(va.get(), XmmConst(v128::fromV(_mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0))));
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-//HGT uses signed values.  HLGT uses unsigned values
-void SPURecompiler::HGT(u32 rt, s32 ra, s32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
-	c.cmp(*addr, cpu_dword(GPR[rb]._s32[3]));
-	c.setg(addr->r8());
-	c.shl(*addr, 24);
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	c.or_(*pos_var, *addr);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLZ(u32 rt, u32 ra)
-{
-	XmmInvalidate(rt);
-	c.mov(*qw0, 32 + 31);
-	for (u32 i = 0; i < 4; i++)
-	{
-		c.bsr(*addr, cpu_dword(GPR[ra]._u32[i]));
-		c.cmovz(*addr, qw0->r32());
-		c.xor_(*addr, 31);
-		c.mov(cpu_dword(GPR[rt]._u32[i]), *addr);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XSWD(u32 rt, u32 ra)
-{
-	c.movsxd(*qw0, cpu_dword(GPR[ra]._s32[0]));
-	c.movsxd(*qw1, cpu_dword(GPR[ra]._s32[2]));
-	c.mov(cpu_qword(GPR[rt]._s64[0]), *qw0);
-	c.mov(cpu_qword(GPR[rt]._s64[1]), *qw1);
-	XmmInvalidate(rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XSHW(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pslld(va.get(), 16);
-	c.psrad(va.get(), 16);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CNTB(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& v1 = XmmCopy(va);
-	const XmmLink& vm = XmmAlloc();
-	c.psrlq(v1.get(), 4);
-	c.movdqa(vm.get(), XmmConst(v128::from8p(0xf)));
-	c.pand(va.get(), vm.get());
-	c.pand(v1.get(), vm.get());
-	c.movdqa(vm.get(), XmmConst(v128::fromV(_mm_set_epi8(4, 3, 3, 2, 3, 2, 2, 1, 3, 2, 2, 1, 2, 1, 1, 0))));
-	c.pshufb(vm.get(), va.get());
-	c.movdqa(va.get(), XmmConst(v128::fromV(_mm_set_epi8(4, 3, 3, 2, 3, 2, 2, 1, 3, 2, 2, 1, 2, 1, 1, 0))));
-	c.pshufb(va.get(), v1.get());
-	c.paddb(va.get(), vm.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(v1);
-	XmmFinalize(vm);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XSBH(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.psllw(va.get(), 8);
-	c.psraw(va.get(), 8);
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLGT(u32 rt, u32 ra, u32 rb)
-{
-	// compare if-greater-than
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from32p(0x80000000)));
-	c.pxor(va.get(), vi.get());
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pxor(vi.get(), vb->read());
-	}
-	else
-	{
-		c.pxor(vi.get(), cpu_xmm(GPR[rb]));
-	}
-	c.pcmpgtd(va.get(), vi.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ANDC(u32 rt, u32 ra, u32 rb)
-{
-	// and not
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.pandn(vb.get(), va->read());
-	}
-	else
-	{
-		c.pandn(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FCGT(u32 rt, u32 ra, u32 rb)
-{
-	// reverted less-than
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.cmpps(vb.get(), va->read(), 1);
-	}
-	else
-	{
-		c.cmpps(vb.get(), cpu_xmm(GPR[ra]), 1);
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFCGT(u32 rt, u32 ra, u32 rb)
-{
-	return UNK("DFCGT");
-}
-
-void SPURecompiler::FA(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.addps(va.get(), vb->read());
-	}
-	else
-	{
-		c.addps(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FS(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.subps(va.get(), vb->read());
-	}
-	else
-	{
-		c.subps(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FM(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.mulps(va.get(), vb->read());
-	}
-	else
-	{
-		c.mulps(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLGTH(u32 rt, u32 ra, u32 rb)
-{
-	// compare if-greater-than
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from16p(0x8000)));
-	c.pxor(va.get(), vi.get());
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pxor(vi.get(), vb->read());
-	}
-	else
-	{
-		c.pxor(vi.get(), cpu_xmm(GPR[rb]));
-	}
-	c.pcmpgtw(va.get(), vi.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ORC(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb, rt);
-	c.pxor(vb.get(), XmmConst(v128::from32p(0xffffffff)));
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.por(vb.get(), va->read());
-	}
-	else
-	{
-		c.por(vb.get(), cpu_xmm(GPR[ra]));
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FCMGT(u32 rt, u32 ra, u32 rb)
-{
-	// reverted less-than
-	const XmmLink& vb = XmmGet(rb, rt);
-	const XmmLink& vi = XmmAlloc();
-	c.movaps(vi.get(), XmmConst(v128::from32p(0x7fffffff)));
-	c.andps(vb.get(), vi.get()); // abs
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.andps(vi.get(), va->read());
-	}
-	else
-	{
-		c.andps(vi.get(), cpu_xmm(GPR[ra]));
-	}
-	c.cmpps(vb.get(), vi.get(), 1);
-	XmmFinalize(vb, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFCMGT(u32 rt, u32 ra, u32 rb)
-{
-	return UNK("DFCMGT");
-}
-
-void SPURecompiler::DFA(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.addpd(va.get(), vb->read());
-	}
-	else
-	{
-		c.addpd(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFS(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.subpd(va.get(), vb->read());
-	}
-	else
-	{
-		c.subpd(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFM(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.mulpd(va.get(), vb->read());
-	}
-	else
-	{
-		c.mulpd(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLGTB(u32 rt, u32 ra, u32 rb)
-{
-	// compare if-greater-than
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from8p(0x80)));
-	c.pxor(va.get(), vi.get());
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pxor(vi.get(), vb->read());
-	}
-	else
-	{
-		c.pxor(vi.get(), cpu_xmm(GPR[rb]));
-	}
-	c.pcmpgtb(va.get(), vi.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HLGT(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.cmp(*addr, cpu_dword(GPR[rb]._u32[3]));
-	c.seta(addr->r8());
-	c.shl(*addr, 24);
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	c.or_(*pos_var, *addr);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFMA(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vr = XmmGet(rt, rt);
-	const XmmLink& va = XmmGet(ra);
-	c.mulpd(va.get(), cpu_xmm(GPR[rb]));
-	c.addpd(vr.get(), va.get());
-	XmmFinalize(vr, rt);
-	XmmFinalize(va);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFMS(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vt = (ra == rt) ? XmmCopy(va) : XmmGet(rt);
-	c.mulpd(va.get(), cpu_xmm(GPR[rb]));
-	c.subpd(va.get(), vt.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFNMS(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vr = XmmGet(rt, rt);
-	const XmmLink& va = XmmGet(ra);
-	c.mulpd(va.get(), cpu_xmm(GPR[rb]));
-	c.subpd(vr.get(), va.get());
-	XmmFinalize(vr, rt);
-	XmmFinalize(va);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFNMA(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vt = (ra == rt) ? XmmCopy(va) : XmmGet(rt);
-	c.mulpd(va.get(), cpu_xmm(GPR[rb]));
-	c.addpd(vt.get(), va.get());
-	c.xorpd(va.get(), va.get());
-	c.subpd(va.get(), vt.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CEQ(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pcmpeqd(va.get(), vb->read());
-	}
-	else
-	{
-		c.pcmpeqd(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYHHU(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	const XmmLink& va2 = XmmCopy(va);
-	c.pmulhuw(va.get(), vb.get());
-	c.pmullw(va2.get(), vb.get());
-	c.pand(va.get(), XmmConst(v128::from32p(0xffff0000)));
-	c.psrld(va2.get(), 16);
-	c.por(va.get(), va2.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(va2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ADDX(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vt = XmmGet(rt);
-	c.pand(vt.get(), XmmConst(v128::from32p(1)));
-	c.paddd(vt.get(), cpu_xmm(GPR[ra]));
-	c.paddd(vt.get(), cpu_xmm(GPR[rb]));
-	XmmFinalize(vt, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SFX(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vt = XmmGet(rt);
-	const XmmLink& vb = XmmGet(rb, rt);
-	c.pandn(vt.get(), XmmConst(v128::from32p(1)));
-	c.psubd(vb.get(), cpu_xmm(GPR[ra]));
-	c.psubd(vb.get(), vt.get());
-	XmmFinalize(vb, rt);
-	XmmFinalize(vt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGX(u32 rt, u32 ra, u32 rb) //nf
-{
-	WRAPPER_BEGIN(rt, ra, rb);
-	for (int w = 0; w < 4; w++)
-		CPU->GPR[rt]._u32[w] = ((u64)CPU->GPR[ra]._u32[w] + (u64)CPU->GPR[rb]._u32[w] + (u64)(CPU->GPR[rt]._u32[w] & 1)) >> 32;
-	WRAPPER_END(rt, ra, rb);
-}
-
-void SPURecompiler::BGX(u32 rt, u32 ra, u32 rb) //nf
-{
-	WRAPPER_BEGIN(rt, ra, rb);
-	s64 nResult;
-
-	for (int w = 0; w < 4; w++)
-	{
-		nResult = (u64)CPU->GPR[rb]._u32[w] - (u64)CPU->GPR[ra]._u32[w] - (u64)(1 - (CPU->GPR[rt]._u32[w] & 1));
-		CPU->GPR[rt]._u32[w] = nResult < 0 ? 0 : 1;
-	}
-	WRAPPER_END(rt, ra, rb);
-}
-
-void SPURecompiler::MPYHHA(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vt = XmmGet(rt, rt);
-	const XmmLink& va = XmmGet(ra);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	c.psrld(va.get(), 16);
-	c.psrld(vb.get(), 16);
-	c.pmaddwd(va.get(), vb.get());
-	c.paddd(vt.get(), va.get());
-	XmmFinalize(vt, rt);
-	XmmFinalize(va);
-	XmmFinalize(vb);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYHHAU(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vt = XmmGet(rt, rt);
-	const XmmLink& va = XmmGet(ra);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	const XmmLink& va2 = XmmCopy(va);
-	c.pmulhuw(va.get(), vb.get());
-	c.pmullw(va2.get(), vb.get());
-	c.pand(va.get(), XmmConst(v128::from32p(0xffff0000)));
-	c.psrld(va2.get(), 16);
-	c.paddd(vt.get(), va.get());
-	c.paddd(vt.get(), va2.get());
-	XmmFinalize(vt, rt);
-	XmmFinalize(va);
-	XmmFinalize(vb);
-	XmmFinalize(va2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FSCRRD(u32 rt)
-{
-	// zero (hack)
-	const XmmLink& v0 = XmmAlloc(rt);
-	c.pxor(v0.get(), v0.get());
-	XmmFinalize(v0, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FESD(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.shufps(va.get(), va.get(), 0x8d); // _f[0] = _f[1]; _f[1] = _f[3];
-	c.cvtps2pd(va.get(), va.get());
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FRDS(u32 rt, u32 ra)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.cvtpd2ps(va.get(), va.get());
-	c.shufps(va.get(), va.get(), 0x72); // _f[1] = _f[0]; _f[3] = _f[1]; _f[0] = _f[2] = 0;
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FSCRWR(u32 rt, u32 ra)
-{
-	// nop (not implemented)
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFTSV(u32 rt, u32 ra, s32 i7)
-{
-	return UNK("DFTSV");
-}
-
-void SPURecompiler::FCEQ(u32 rt, u32 ra, u32 rb)
-{
-	// compare equal
-	const XmmLink& vb = XmmGet(rb, rt);
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.cmpps(vb.get(), va->read(), 0);
-	}
-	else
-	{
-		c.cmpps(vb.get(), cpu_xmm(GPR[ra]), 0);
-	}
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFCEQ(u32 rt, u32 ra, u32 rb)
-{
-	return UNK("DFCEQ");
-}
-
-void SPURecompiler::MPY(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from32p(0xffff)));
-	c.pand(va.get(), vi.get());
-	c.pand(vb.get(), vi.get());
-	c.pmaddwd(va.get(), vb.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYH(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	c.psrld(va.get(), 16);
-	c.pmullw(va.get(), vb.get());
-	c.pslld(va.get(), 16);
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYHH(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	c.psrld(va.get(), 16);
-	c.psrld(vb.get(), 16);
-	c.pmaddwd(va.get(), vb.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYS(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	c.pmulhw(va.get(), vb.get());
-	c.pslld(va.get(), 16);
-	c.psrad(va.get(), 16);
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CEQH(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pcmpeqw(va.get(), vb->read());
-	}
-	else
-	{
-		c.pcmpeqw(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FCMEQ(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb, rt);
-	const XmmLink& vi = XmmAlloc();
-	c.movaps(vi.get(), XmmConst(v128::from32p(0x7fffffff)));
-	c.andps(vb.get(), vi.get()); // abs
-	if (const XmmLink* va = XmmRead(ra))
-	{
-		c.andps(vi.get(), va->read());
-	}
-	else
-	{
-		c.andps(vi.get(), cpu_xmm(GPR[ra]));
-	}
-	c.cmpps(vb.get(), vi.get(), 0); // ==
-	XmmFinalize(vb, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::DFCMEQ(u32 rt, u32 ra, u32 rb)
-{
-	return UNK("DFCMEQ");
-}
-
-void SPURecompiler::MPYU(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = (ra == rb) ? XmmCopy(va) : XmmGet(rb);
-	const XmmLink& va2 = XmmCopy(va);
-	c.pmulhuw(va.get(), vb.get());
-	c.pmullw(va2.get(), vb.get());
-	c.pslld(va.get(), 16);
-	c.pand(va2.get(), XmmConst(v128::from32p(0xffff)));
-	c.por(va.get(), va2.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(va2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CEQB(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (const XmmLink* vb = XmmRead(rb))
-	{
-		c.pcmpeqb(va.get(), vb->read());
-	}
-	else
-	{
-		c.pcmpeqb(va.get(), cpu_xmm(GPR[rb]));
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FI(u32 rt, u32 ra, u32 rb)
-{
-	const XmmLink& vb = XmmGet(rb);
-	XmmFinalize(vb, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HEQ(u32 rt, u32 ra, u32 rb)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
-	c.cmp(*addr, cpu_dword(GPR[rb]._s32[3]));
-	c.sete(addr->r8());
-	c.shl(*addr, 24);
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	c.or_(*pos_var, *addr);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CFLTS(u32 rt, u32 ra, s32 i8)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (i8 != 173)
-	{
-		c.mulps(va.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(static_cast<float>(173 - (i8 & 0xff))))))); // scale
-	}
-	const XmmLink& vi = XmmAlloc();
-	c.movaps(vi.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(31)))));
-	c.cmpps(vi.get(), va.get(), 2);
-	c.cvttps2dq(va.get(), va.get()); // convert to ints with truncation
-	c.pxor(va.get(), vi.get()); // fix result saturation (0x80000000 -> 0x7fffffff)
-	XmmFinalize(va, rt);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CFLTU(u32 rt, u32 ra, s32 i8)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	if (i8 != 173)
-	{
-		c.mulps(va.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(static_cast<float>(173 - (i8 & 0xff))))))); // scale
-	}
-	c.maxps(va.get(), XmmConst({})); // saturate
-	const XmmLink& vs = XmmCopy(va); // copy scaled value
-	const XmmLink& vs2 = XmmCopy(va);
-	const XmmLink& vs3 = XmmAlloc();
-	c.movaps(vs3.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(31)))));
-	c.subps(vs2.get(), vs3.get());
-	c.cmpps(vs3.get(), vs.get(), 2);
-	c.andps(vs2.get(), vs3.get());
-	c.cvttps2dq(va.get(), va.get());
-	c.cmpps(vs.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(32)))), 5);
-	c.cvttps2dq(vs2.get(), vs2.get());
-	c.por(va.get(), vs.get());
-	c.por(va.get(), vs2.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vs);
-	XmmFinalize(vs2);
-	XmmFinalize(vs3);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CSFLT(u32 rt, u32 ra, s32 i8)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.cvtdq2ps(va.get(), va.get()); // convert to floats
-	if (i8 != 155)
-	{
-		c.mulps(va.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(static_cast<float>((i8 & 0xff) - 155)))))); // scale
-	}
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CUFLT(u32 rt, u32 ra, s32 i8)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& v1 = XmmCopy(va);
-	c.pand(va.get(), XmmConst(v128::from32p(0x7fffffff)));
-	c.cvtdq2ps(va.get(), va.get()); // convert to floats
-	c.psrad(v1.get(), 31); // generate mask from sign bit
-	c.andps(v1.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(31))))); // generate correction component
-	c.addps(va.get(), v1.get()); // add correction component
-	if (i8 != 155)
-	{
-		c.mulps(va.get(), XmmConst(v128::fromF(_mm_set1_ps(exp2f(static_cast<float>((i8 & 0xff) - 155)))))); // scale
-	}
-	XmmFinalize(va, rt);
-	XmmFinalize(v1);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRZ(u32 rt, s32 i16)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, (CPU.PC >> 2) + 1);
-	c.mov(*pos_var, branchTarget(CPU.PC, i16) >> 2);
-	c.cmp(cpu_dword(GPR[rt]._u32[3]), 0);
-	c.cmovne(*pos_var, *addr);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::STQA(u32 rt, s32 i16)
-{
-	const u32 lsa = (i16 << 2) & 0x3fff0;
-
-	/*const XmmLink& vt = XmmGet(rt);
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	c.movdqa(oword_ptr(*ls_var, lsa), vt.get());
-	XmmFinalize(vt);*/
-
-	c.mov(*qw0, cpu_qword(GPR[rt]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[rt]._u64[1]));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(qword_ptr(*ls_var, lsa), *qw1);
-	c.mov(qword_ptr(*ls_var, lsa + 8), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRNZ(u32 rt, s32 i16)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, (CPU.PC >> 2) + 1);
-	c.mov(*pos_var, branchTarget(CPU.PC, i16) >> 2);
-	c.cmp(cpu_dword(GPR[rt]._u32[3]), 0);
-	c.cmove(*pos_var, *addr);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRHZ(u32 rt, s32 i16)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, (CPU.PC >> 2) + 1);
-	c.mov(*pos_var, branchTarget(CPU.PC, i16) >> 2);
-	c.cmp(cpu_word(GPR[rt]._u16[6]), 0);
-	c.cmovnz(*pos_var, *addr);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRHNZ(u32 rt, s32 i16)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*addr, (CPU.PC >> 2) + 1);
-	c.mov(*pos_var, branchTarget(CPU.PC, i16) >> 2);
-	c.cmp(cpu_word(GPR[rt]._u16[6]), 0);
-	c.cmovz(*pos_var, *addr);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::STQR(u32 rt, s32 i16)
-{
-	const u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
-
-	/*const XmmLink& vt = XmmGet(rt);
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	c.movdqa(oword_ptr(*ls_var, lsa), vt.get());
-	XmmFinalize(vt);*/
-
-	c.mov(*qw0, cpu_qword(GPR[rt]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[rt]._u64[1]));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(qword_ptr(*ls_var, lsa), *qw1);
-	c.mov(qword_ptr(*ls_var, lsa + 8), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRA(s32 i16)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*pos_var, branchTarget(0, i16) >> 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::LQA(u32 rt, s32 i16)
-{
-	XmmInvalidate(rt);
-
-	const u32 lsa = (i16 << 2) & 0x3fff0;
-
-	/*const XmmLink& vt = XmmAlloc(rt);
-	c.movdqa(vt.get(), oword_ptr(*ls_var, lsa));
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	XmmFinalize(vt, rt);*/
-
-	c.mov(*qw0, qword_ptr(*ls_var, lsa));
-	c.mov(*qw1, qword_ptr(*ls_var, lsa + 8));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRASL(u32 rt, s32 i16)
-{
-	XmmInvalidate(rt);
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.xor_(*addr, *addr); // zero
-	c.mov(cpu_dword(GPR[rt]._u32[0]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[1]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[2]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[3]), CPU.PC + 4);
-	c.mov(*pos_var, branchTarget(0, i16) >> 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BR(s32 i16)
-{
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.mov(*pos_var, branchTarget(CPU.PC, i16) >> 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FSMBI(u32 rt, s32 i16)
-{
-	if (i16 == 0)
-	{
-		// zero
-		const XmmLink& v0 = XmmAlloc(rt);
-		c.pxor(v0.get(), v0.get());
-		XmmFinalize(v0, rt);
-	}
-	else
-	{
-		const XmmLink& vr = XmmAlloc(rt);
-		c.movdqa(vr.get(), g_imm_xmm(fsmb[i16 & 0xffff]));
-		XmmFinalize(vr, rt);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::BRSL(u32 rt, s32 i16)
-{
-	XmmInvalidate(rt);
-
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-
-	c.xor_(*addr, *addr); // zero
-	c.mov(cpu_dword(GPR[rt]._u32[0]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[1]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[2]), *addr);
-	c.mov(cpu_dword(GPR[rt]._u32[3]), CPU.PC + 4);
-	c.mov(*pos_var, branchTarget(CPU.PC, i16) >> 2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::LQR(u32 rt, s32 i16)
-{
-	XmmInvalidate(rt);
-
-	const u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
-
-	/*const XmmLink& vt = XmmAlloc(rt);
-	c.movdqa(vt.get(), oword_ptr(*ls_var, lsa));
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	XmmFinalize(vt, rt);*/
-
-	c.mov(*qw0, qword_ptr(*ls_var, lsa));
-	c.mov(*qw1, qword_ptr(*ls_var, lsa + 8));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::IL(u32 rt, s32 i16)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	if (i16 == 0)
-	{
-		c.pxor(vr.get(), vr.get());
-	}
-	else if (i16 == -1)
-	{
-		c.pcmpeqd(vr.get(), vr.get());
-	}
-	else
-	{
-		c.movdqa(vr.get(), XmmConst(v128::from32p(i16)));
-	}
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ILHU(u32 rt, s32 i16)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	c.movdqa(vr.get(), XmmConst(v128::from32p(i16 << 16)));
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ILH(u32 rt, s32 i16)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	c.movdqa(vr.get(), XmmConst(v128::from32p(i16)));
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::IOHL(u32 rt, s32 i16)
-{
-	const XmmLink& vt = XmmGet(rt, rt);
-	c.por(vt.get(), XmmConst(v128::from32p(i16 & 0xffff)));
-	XmmFinalize(vt, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ORI(u32 rt, u32 ra, s32 i10)
-{
-	if (i10 == -1)
-	{
-		// fill with 1
-		const XmmLink& v1 = XmmAlloc(rt);
-		c.pcmpeqd(v1.get(), v1.get());
-		XmmFinalize(v1, rt);
-	}
-	else if (i10 == 0)
-	{
-		if (rt != ra)
-		{
-			// mov
-			const XmmLink& va = XmmGet(ra, rt);
-			XmmFinalize(va, rt);
-		}
-		// else nop
-	}
-	else
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		c.por(va.get(), XmmConst(v128::from32p(i10)));
-		XmmFinalize(va, rt);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ORHI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.por(va.get(), XmmConst(v128::from16p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ORBI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.por(va.get(), XmmConst(v128::from8p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SFI(u32 rt, u32 ra, s32 i10)
-{
-	if (i10 == 0)
-	{
-		// zero
-		const XmmLink& v0 = XmmAlloc(rt);
-		c.pxor(v0.get(), v0.get());
-		c.psubd(v0.get(), cpu_xmm(GPR[ra]));
-		XmmFinalize(v0, rt);
-	}
-	else if (i10 == -1)
-	{
-		// fill with 1
-		const XmmLink& v1 = XmmAlloc(rt);
-		c.pcmpeqd(v1.get(), v1.get());
-		c.psubd(v1.get(), cpu_xmm(GPR[ra]));
-		XmmFinalize(v1, rt);
-	}
-	else
-	{
-		const XmmLink& vr = XmmAlloc(rt);
-		c.movdqa(vr.get(), XmmConst(v128::from32p(i10)));
-		c.psubd(vr.get(), cpu_xmm(GPR[ra]));
-		XmmFinalize(vr, rt);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SFHI(u32 rt, u32 ra, s32 i10)
-{
-	if (i10 == 0)
-	{
-		// zero
-		const XmmLink& v0 = XmmAlloc(rt);
-		c.pxor(v0.get(), v0.get());
-		c.psubw(v0.get(), cpu_xmm(GPR[ra]));
-		XmmFinalize(v0, rt);
-	}
-	else if (i10 == -1)
-	{
-		// fill with 1
-		const XmmLink& v1 = XmmAlloc(rt);
-		c.pcmpeqw(v1.get(), v1.get());
-		c.psubw(v1.get(), cpu_xmm(GPR[ra]));
-		XmmFinalize(v1, rt);
-	}
-	else
-	{
-		const XmmLink& vr = XmmAlloc(rt);
-		c.movdqa(vr.get(), XmmConst(v128::from16p(i10)));
-		c.psubw(vr.get(), cpu_xmm(GPR[ra]));
-		XmmFinalize(vr, rt);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ANDI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pand(va.get(), XmmConst(v128::from32p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ANDHI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pand(va.get(), XmmConst(v128::from16p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ANDBI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pand(va.get(), XmmConst(v128::from8p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::AI(u32 rt, u32 ra, s32 i10)
-{
-	// add
-	const XmmLink& va = XmmGet(ra, rt);
-	c.paddd(va.get(), XmmConst(v128::from32p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::AHI(u32 rt, u32 ra, s32 i10)
-{
-	// add
-	const XmmLink& va = XmmGet(ra, rt);
-	c.paddw(va.get(), XmmConst(v128::from16p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::STQD(u32 rt, s32 i10, u32 ra) // i10 is shifted left by 4 while decoding
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	if (i10) c.add(*addr, i10);
-	c.and_(*addr, 0x3fff0);
-
-	/*const XmmLink& vt = XmmGet(rt);
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	c.movdqa(oword_ptr(*ls_var, *addr), vt.get());
-	XmmFinalize(vt);*/
-
-	c.mov(*qw0, cpu_qword(GPR[rt]._u64[0]));
-	c.mov(*qw1, cpu_qword(GPR[rt]._u64[1]));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(qword_ptr(*ls_var, *addr, 0, 0), *qw1);
-	c.mov(qword_ptr(*ls_var, *addr, 0, 8), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::LQD(u32 rt, s32 i10, u32 ra) // i10 is shifted left by 4 while decoding
-{
-	XmmInvalidate(rt);
-
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	if (i10) c.add(*addr, i10);
-	c.and_(*addr, 0x3fff0);
-
-	/*const XmmLink& vt = XmmAlloc(rt);
-	c.movdqa(vt.get(), oword_ptr(*ls_var, *addr));
-	c.pshufb(vt.get(), XmmConst(_mm_set_epi32(0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f)));
-	XmmFinalize(vt, rt);*/
-
-	c.mov(*qw0, qword_ptr(*ls_var, *addr, 0, 0));
-	c.mov(*qw1, qword_ptr(*ls_var, *addr, 0, 8));
-	c.bswap(*qw0);
-	c.bswap(*qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[0]), *qw1);
-	c.mov(cpu_qword(GPR[rt]._u64[1]), *qw0);
-
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XORI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pxor(va.get(), XmmConst(v128::from32p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XORHI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pxor(va.get(), XmmConst(v128::from16p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::XORBI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pxor(va.get(), XmmConst(v128::from8p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGTI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pcmpgtd(va.get(), XmmConst(v128::from32p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGTHI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pcmpgtw(va.get(), XmmConst(v128::from16p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CGTBI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pcmpgtb(va.get(), XmmConst(v128::from8p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HGTI(u32 rt, u32 ra, s32 i10)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
-	c.cmp(*addr, i10);
-	c.setg(addr->r8());
-	c.shl(*addr, 24);
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	c.or_(*pos_var, *addr);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLGTI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pxor(va.get(), XmmConst(v128::from32p(0x80000000)));
-	c.pcmpgtd(va.get(), XmmConst(v128::from32p((u32)i10 - 0x80000000)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLGTHI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pxor(va.get(), XmmConst(v128::from16p(0x8000)));
-	c.pcmpgtw(va.get(), XmmConst(v128::from16p((u16)i10 - 0x8000)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CLGTBI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.psubb(va.get(), XmmConst(v128::from8p(0x80)));
-	c.pcmpgtb(va.get(), XmmConst(v128::from8p((s8)i10 - 0x80)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HLGTI(u32 rt, u32 ra, s32 i10)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.cmp(*addr, i10);
-	c.seta(addr->r8());
-	c.shl(*addr, 24);
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	c.or_(*pos_var, *addr);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	c.pmaddwd(va.get(), XmmConst(v128::from32p(i10 & 0xffff)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYUI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vi = XmmAlloc();
-	const XmmLink& va2 = XmmCopy(va);
-	c.movdqa(vi.get(), XmmConst(v128::from32p(i10 & 0xffff)));
-	c.pmulhuw(va.get(), vi.get());
-	c.pmullw(va2.get(), vi.get());
-	c.pslld(va.get(), 16);
-	c.por(va.get(), va2.get());
-	XmmFinalize(va, rt);
-	XmmFinalize(vi);
-	XmmFinalize(va2);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CEQI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pcmpeqd(va.get(), XmmConst(v128::from32p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CEQHI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pcmpeqw(va.get(), XmmConst(v128::from16p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::CEQBI(u32 rt, u32 ra, s32 i10)
-{
-	const XmmLink& va = XmmGet(ra);
-	c.pcmpeqb(va.get(), XmmConst(v128::from8p(i10)));
-	XmmFinalize(va, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HEQI(u32 rt, u32 ra, s32 i10)
-{
-	c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
-	c.cmp(*addr, i10);
-	c.sete(addr->r8());
-	c.shl(*addr, 24);
-	c.mov(*pos_var, (CPU.PC >> 2) + 1);
-	c.or_(*pos_var, *addr);
-	do_finalize = true;
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HBRA(s32 ro, s32 i16)
-{ 
-	//i16 is shifted left by 2 while decoding
-	LOG_OPCODE();
-}
-
-void SPURecompiler::HBRR(s32 ro, s32 i16)
-{
-	LOG_OPCODE();
-}
-
-void SPURecompiler::ILA(u32 rt, u32 i18)
-{
-	const XmmLink& vr = XmmAlloc(rt);
-	if (i18 == 0)
-	{
-		c.pxor(vr.get(), vr.get());
-	}
-	else
-	{
-		c.movdqa(vr.get(), XmmConst(v128::from32p(i18 & 0x3ffff)));
-	}
-	XmmFinalize(vr, rt);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SELB(u32 rt, u32 ra, u32 rb, u32 rc)
-{
-	const XmmLink& vb = XmmGet(rb);
-	const XmmLink& vc = XmmGet(rc);
-	c.pand(vb.get(), vc.get());
-	c.pandn(vc.get(), cpu_xmm(GPR[ra]));
-	c.por(vb.get(), vc.get());
-	XmmFinalize(vb, rt);
-	XmmFinalize(vc);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::SHUFB(u32 rt, u32 ra, u32 rb, u32 rc)
-{
-	const XmmLink& v0 = XmmGet(rc); // v0 = mask
-	const XmmLink& v1 = XmmAlloc();
-	const XmmLink& v2 = XmmCopy(v0); // v2 = mask
-	const XmmLink& v3 = XmmAlloc();
-	const XmmLink& v4 = XmmAlloc();
-	const XmmLink& vFF = XmmAlloc(rt);
-	// generate specific values:
-	c.movdqa(v1.get(), XmmConst(v128::from8p(0xe0))); // v1 = 11100000
-	c.movdqa(v3.get(), XmmConst(v128::from8p(0x80))); // v3 = 10000000
-	c.pand(v2.get(), v1.get()); // filter mask      v2 = mask & 11100000
-	c.movdqa(vFF.get(), v2.get()); // and copy      vFF = mask & 11100000
-	c.movdqa(v4.get(), XmmConst(v128::from8p(0xc0))); // v4 = 11000000
-	c.pcmpeqb(vFF.get(), v4.get()); // gen 0xff     vFF = (mask & 11100000 == 11000000) ? 0xff : 0
-	c.movdqa(v4.get(), v2.get()); // copy again     v4 = mask & 11100000
-	c.pand(v4.get(), v3.get()); // filter mask      v4 = mask & 10000000
-	c.pcmpeqb(v2.get(), v1.get()); //               v2 = (mask & 11100000 == 11100000) ? 0xff : 0
-	c.pcmpeqb(v4.get(), v3.get()); //               v4 = (mask & 10000000 == 10000000) ? 0xff : 0
-	c.pand(v2.get(), v3.get()); // generate 0x80    v2 = (mask & 11100000 == 11100000) ? 0x80 : 0
-	c.por(vFF.get(), v2.get()); // merge 0xff, 0x80 vFF = (mask & 11100000 == 11000000) ? 0xff : (mask & 11100000 == 11100000) ? 0x80 : 0
-	c.pandn(v1.get(), v0.get()); // filter mask     v1 = mask & 00011111
-								 // select bytes from [rb]:
-	c.movdqa(v2.get(), XmmConst(v128::from8p(0x0f))); //   v2 = 00001111
-	c.pxor(v1.get(), XmmConst(v128::from8p(0x10))); //   v1 = (mask & 00011111) ^ 00010000
-	c.psubb(v2.get(), v1.get()); //                 v2 = 00001111 - ((mask & 00011111) ^ 00010000)
-	c.movdqa(v1.get(), cpu_xmm(GPR[rb])); //        v1 = rb
-	c.pshufb(v1.get(), v2.get()); //                v1 = select(rb, 00001111 - ((mask & 00011111) ^ 00010000))
-								  // select bytes from [ra]:
-	c.pxor(v2.get(), XmmConst(v128::from8p(0xf0))); //   v2 = (00001111 - ((mask & 00011111) ^ 00010000)) ^ 11110000
-	c.movdqa(v3.get(), cpu_xmm(GPR[ra])); //        v3 = ra
-	c.pshufb(v3.get(), v2.get()); //                v3 = select(ra, (00001111 - ((mask & 00011111) ^ 00010000)) ^ 11110000)
-	c.por(v1.get(), v3.get()); //                   v1 = select(rb, 00001111 - ((mask & 00011111) ^ 00010000)) | (v3)
-	c.pandn(v4.get(), v1.get()); // filter result   v4 = v1 & ((mask & 10000000 == 10000000) ? 0 : 0xff)
-	c.por(vFF.get(), v4.get()); // final merge      vFF = (mask & 10000000 == 10000000) ? ((mask & 11100000 == 11000000) ? 0xff : (mask & 11100000 == 11100000) ? 0x80 : 0) : (v1)
-	XmmFinalize(vFF, rt);
-	XmmFinalize(v4);
-	XmmFinalize(v3);
-	XmmFinalize(v2);
-	XmmFinalize(v1);
-	XmmFinalize(v0);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::MPYA(u32 rt, u32 ra, u32 rb, u32 rc)
-{
-	const XmmLink& va = XmmGet(ra, rt);
-	const XmmLink& vb = XmmGet(rb);
-	const XmmLink& vi = XmmAlloc();
-	c.movdqa(vi.get(), XmmConst(v128::from32p(0xffff)));
-	c.pand(va.get(), vi.get());
-	c.pand(vb.get(), vi.get());
-	c.pmaddwd(va.get(), vb.get());
-	c.paddd(va.get(), cpu_xmm(GPR[rc]));
-	XmmFinalize(va, rt);
-	XmmFinalize(vb);
-	XmmFinalize(vi);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FNMS(u32 rt, u32 ra, u32 rb, u32 rc)
-{
-	const XmmLink& va = XmmGet(ra);
-	const XmmLink& vc = (ra == rc) ? XmmCopy(va, rt) : XmmGet(rc, rt);
-
-	if (ra == rb)
-	{
-		c.mulps(va.get(), va.get());
-	}
-	else if (rb == rc)
-	{
-		c.mulps(va.get(), vc.get());
-	}
-	else
-	{
-		if (const XmmLink* vb = XmmRead(rb))
-		{
-			c.mulps(va.get(), vb->read());
-		}
-		else
-		{
-			c.mulps(va.get(), cpu_xmm(GPR[rb]));
-		}
-	}
-	c.subps(vc.get(), va.get());
-	XmmFinalize(vc, rt);
-	XmmFinalize(va);
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FMA(u32 rt, u32 ra, u32 rb, u32 rc)
-{
-	if (ra != rb && rb != rc && rc != ra)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		if (const XmmLink* vb = XmmRead(rb))
-		{
-			c.mulps(va.get(), vb->read());
-		}
-		else
-		{
-			c.mulps(va.get(), cpu_xmm(GPR[rb]));
-		}
-		if (const XmmLink* vc = XmmRead(rc))
-		{
-			c.addps(va.get(), vc->read());
-		}
-		else
-		{
-			c.addps(va.get(), cpu_xmm(GPR[rc]));
-		}
-		XmmFinalize(va, rt);
-	}
-	else if (ra == rb && rb == rc)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		const XmmLink& vc = XmmCopy(va);
-		c.mulps(va.get(), va.get());
-		c.addps(va.get(), vc.get());
-		XmmFinalize(va, rt);
-		XmmFinalize(vc);
-	}
-	else if (ra == rb)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		c.mulps(va.get(), va.get());
-		if (const XmmLink* vc = XmmRead(rc))
-		{
-			c.addps(va.get(), vc->read());
-		}
-		else
-		{
-			c.addps(va.get(), cpu_xmm(GPR[rc]));
-		}
-		XmmFinalize(va, rt);
-	}
-	else if (rb == rc)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		if (const XmmLink* vc = XmmRead(rc))
-		{
-			c.mulps(va.get(), vc->read());
-			c.addps(va.get(), vc->read());
-		}
-		else
-		{
-			const XmmLink& vb = XmmGet(rb, rb);
-			c.mulps(va.get(), vb.get());
-			c.addps(va.get(), vb.get());
-			XmmFinalize(vb, rb);
-		}
-		XmmFinalize(va, rt);
-	}
-	else if (ra == rc)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		const XmmLink& vc = XmmCopy(va);
-		if (const XmmLink* vb = XmmRead(rb))
-		{
-			c.mulps(va.get(), vb->read());
-		}
-		else
-		{
-			c.mulps(va.get(), cpu_xmm(GPR[rb]));
-		}
-		c.addps(va.get(), vc.get());
-		XmmFinalize(va, rt);
-		XmmFinalize(vc);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::FMS(u32 rt, u32 ra, u32 rb, u32 rc)
-{
-	if (ra != rb && rb != rc && rc != ra)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		if (const XmmLink* vb = XmmRead(rb))
-		{
-			c.mulps(va.get(), vb->read());
-		}
-		else
-		{
-			c.mulps(va.get(), cpu_xmm(GPR[rb]));
-		}
-		if (const XmmLink* vc = XmmRead(rc))
-		{
-			c.subps(va.get(), vc->read());
-		}
-		else
-		{
-			c.subps(va.get(), cpu_xmm(GPR[rc]));
-		}
-		XmmFinalize(va, rt);
-	}
-	else if (ra == rb && rb == rc)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		const XmmLink& vc = XmmCopy(va);
-		c.mulps(va.get(), va.get());
-		c.subps(va.get(), vc.get());
-		XmmFinalize(va, rt);
-		XmmFinalize(vc);
-	}
-	else if (ra == rb)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		c.mulps(va.get(), va.get());
-		if (const XmmLink* vc = XmmRead(rc))
-		{
-			c.subps(va.get(), vc->read());
-		}
-		else
-		{
-			c.subps(va.get(), cpu_xmm(GPR[rc]));
-		}
-		XmmFinalize(va, rt);
-	}
-	else if (rb == rc)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		if (const XmmLink* vc = XmmRead(rc))
-		{
-			c.mulps(va.get(), vc->read());
-			c.subps(va.get(), vc->read());
-		}
-		else
-		{
-			const XmmLink& vb = XmmGet(rb, rb);
-			c.mulps(va.get(), vb.get());
-			c.subps(va.get(), vb.get());
-			XmmFinalize(vb, rb);
-		}
-		XmmFinalize(va, rt);
-	}
-	else if (ra == rc)
-	{
-		const XmmLink& va = XmmGet(ra, rt);
-		const XmmLink& vc = XmmCopy(va);
-		if (const XmmLink* vb = XmmRead(rb))
-		{
-			c.mulps(va.get(), vb->read());
-		}
-		else
-		{
-			c.mulps(va.get(), cpu_xmm(GPR[rb]));
-		}
-		c.subps(va.get(), vc.get());
-		XmmFinalize(va, rt);
-		XmmFinalize(vc);
-	}
-	LOG_OPCODE();
-}
-
-void SPURecompiler::UNK(u32 code, u32 opcode, u32 gcode)
-{
-	UNK(fmt::format("Unimplemented opcode! (0x%08x, 0x%x, 0x%x)", code, opcode, gcode));
-}
-
-void SPURecompiler::UNK(const std::string& err)
-{
-	LOG_ERROR(Log::SPU, "%s #pc: 0x%x", err.c_str(), CPU.PC);
-	c.mov(cpu_dword(PC), CPU.PC);
-	do_finalize = true;
-	Emu.Pause();
-}
diff --git a/rpcs3/Emu/Cell/SPUThread.cpp b/rpcs3/Emu/Cell/SPUThread.cpp
index 71269a9af8..fb0409ef85 100644
--- a/rpcs3/Emu/Cell/SPUThread.cpp
+++ b/rpcs3/Emu/Cell/SPUThread.cpp
@@ -14,15 +14,18 @@
 
 #include "Emu/Cell/SPUDisAsm.h"
 #include "Emu/Cell/SPUThread.h"
-#include "Emu/Cell/SPUDecoder.h"
 #include "Emu/Cell/SPUInterpreter.h"
-#include "Emu/Cell/SPUInterpreter2.h"
 #include "Emu/Cell/SPURecompiler.h"
 
 #include <cfenv>
 
 extern u64 get_timebased_time();
 
+// defined here since SPUDisAsm.cpp doesn't exist
+const spu_opcode_table_t<void(SPUDisAsm::*)(spu_opcode_t)> SPUDisAsm::opcodes{ DEFINE_SPU_OPCODES(&SPUDisAsm::), &SPUDisAsm::UNK };
+
+thread_local bool spu_channel_t::notification_required;
+
 void spu_int_ctrl_t::set(u64 ints)
 {
 	// leave only enabled interrupts
@@ -47,40 +50,7 @@ void spu_int_ctrl_t::clear(u64 ints)
 	stat &= ~ints;
 }
 
-const g_spu_imm_table_t g_spu_imm;
-
-class spu_inter_func_list_t
-{
-	std::array<spu_inter_func_t, 2048> funcs = {};
-
-	std::mutex m_mutex;
-
-public:
-	void initialize()
-	{
-		std::lock_guard<std::mutex> lock(m_mutex);
-
-		if (funcs[0]) return; // check if already initialized
-
-		auto inter = new SPUInterpreter2;
-		SPUDecoder dec(*inter);
-
-		for (u32 i = 0; i < funcs.size(); i++)
-		{
-			inter->func = spu_interpreter::DEFAULT;
-			
-			dec.Decode(i << 21);
-
-			funcs[i] = inter->func;
-		}
-	}
-
-	force_inline spu_inter_func_t operator [](u32 opcode) const
-	{
-		return funcs[opcode >> 21];
-	}
-}
-g_spu_inter_func_list;
+const spu_imm_table_t g_spu_imm;
 
 SPUThread::SPUThread(CPUThreadType type, const std::string& name, std::function<std::string()> thread_name, u32 index, u32 offset)
 	: CPUThread(type, name, std::move(thread_name))
@@ -90,7 +60,7 @@ SPUThread::SPUThread(CPUThreadType type, const std::string& name, std::function<
 }
 
 SPUThread::SPUThread(const std::string& name, u32 index)
-	: CPUThread(CPU_THREAD_SPU, name, WRAP_EXPR(fmt::format("SPU[0x%x] Thread (%s)[0x%08x]", m_id, m_name.c_str(), PC)))
+	: CPUThread(CPU_THREAD_SPU, name, WRAP_EXPR(fmt::format("SPU[0x%x] Thread (%s)[0x%05x]", m_id, m_name.c_str(), pc)))
 	, index(index)
 	, offset(vm::alloc(0x40000, vm::main))
 {
@@ -138,51 +108,55 @@ void SPUThread::task()
 {
 	std::fesetround(FE_TOWARDZERO);
 
+	if (!custom_task && !m_dec)
+	{
+		// Select opcode table (TODO)
+		const auto& table = Ini.SPUDecoderMode.GetValue() == 0 ? spu_interpreter::precise::g_spu_opcode_table : spu_interpreter::fast::g_spu_opcode_table;
+
+		// LS base address
+		const auto base = vm::get_ptr<const be_t<u32>>(offset);
+
+		while (true)
+		{
+			if (!m_state.load())
+			{
+				// read opcode
+				const u32 opcode = base[pc / 4];
+
+				// call interpreter function
+				table[opcode](*this, { opcode });
+
+				// next instruction
+				pc += 4;
+
+				continue;
+			}
+
+			if (check_status())
+			{
+				return;
+			}
+		}
+	}
+
 	if (custom_task)
 	{
 		if (check_status()) return;
 
 		return custom_task(*this);
 	}
-	
-	if (m_dec)
+
+	while (!m_state.load() || !check_status())
 	{
-		while (true)
-		{
-			if (m_state.load() && check_status()) break;
-
-			// decode instruction using specified decoder
-			m_dec->DecodeMemory(PC + offset);
-
-			// next instruction
-			PC += 4;
-		}
-	}
-	else
-	{
-		while (true)
-		{
-			if (m_state.load() && check_status()) break;
-
-			// read opcode
-			const spu_opcode_t opcode = { vm::read32(PC + offset) };
-
-			// get interpreter function
-			const auto func = g_spu_inter_func_list[opcode.opcode];
-
-			// call interpreter function
-			func(*this, opcode);
-
-			// next instruction
-			PC += 4;
-		}
+		// decode instruction using specified decoder
+		pc += m_dec->DecodeMemory(pc + offset);
 	}
 }
 
 void SPUThread::init_regs()
 {
-	memset(GPR, 0, sizeof(GPR));
-	FPSCR.Reset();
+	gpr = {};
+	fpscr.Reset();
 
 	ch_mfc_args = {};
 	mfc_queue.clear();
@@ -215,7 +189,7 @@ void SPUThread::init_regs()
 
 	int_ctrl = {};
 
-	GPR[1]._u32[3] = 0x3FFF0; // initial stack frame pointer
+	gpr[1]._u32[3] = 0x3FFF0; // initial stack frame pointer
 }
 
 void SPUThread::init_stack()
@@ -230,25 +204,19 @@ void SPUThread::close_stack()
 
 void SPUThread::do_run()
 {
-	m_dec = nullptr;
+	m_dec.reset();
 
 	switch (auto mode = Ini.SPUDecoderMode.GetValue())
 	{
-	case 0: // original interpreter
+	case 0: // Interpreter 1 (Precise)
+	case 1: // Interpreter 2 (Fast)
 	{
-		m_dec.reset(new SPUDecoder(*new SPUInterpreter(*this)));
-		break;
-	}
-		
-	case 1: // alternative interpreter
-	{
-		g_spu_inter_func_list.initialize(); // initialize helper table
 		break;
 	}
 
 	case 2:
 	{
-		m_dec.reset(new SPURecompilerCore(*this));
+		m_dec.reset(new SPURecompilerDecoder(*this));
 		break;
 	}
 
@@ -267,15 +235,16 @@ void SPUThread::fast_call(u32 ls_addr)
 		throw EXCEPTION("Called from the wrong thread");
 	}
 
+	// LS:0x0: this is originally the entry point of the interrupt handler, but interrupts are not implemented
 	write32(0x0, 2);
 
-	auto old_PC = PC;
-	auto old_LR = GPR[0]._u32[3];
-	auto old_stack = GPR[1]._u32[3]; // only saved and restored (may be wrong)
+	auto old_pc = pc;
+	auto old_lr = gpr[0]._u32[3];
+	auto old_stack = gpr[1]._u32[3]; // only saved and restored (may be wrong)
 	auto old_task = std::move(custom_task);
 
-	PC = ls_addr;
-	GPR[0]._u32[3] = 0x0;
+	pc = ls_addr;
+	gpr[0]._u32[3] = 0x0;
 	custom_task = nullptr;
 
 	try
@@ -288,9 +257,9 @@ void SPUThread::fast_call(u32 ls_addr)
 
 	m_state &= ~CPU_STATE_RETURN;
 
-	PC = old_PC;
-	GPR[0]._u32[3] = old_LR;
-	GPR[1]._u32[3] = old_stack;
+	pc = old_pc;
+	gpr[0]._u32[3] = old_lr;
+	gpr[1]._u32[3] = old_stack;
 	custom_task = std::move(old_task);
 }
 
@@ -1218,14 +1187,18 @@ void SPUThread::stop_and_signal(u32 code)
 
 	case 0x003:
 	{
-		auto iter = m_addr_to_hle_function_map.find(PC);
-		assert(iter != m_addr_to_hle_function_map.end());
+		const auto found = m_addr_to_hle_function_map.find(pc);
 
-		auto return_to_caller = iter->second(*this);
-		if (return_to_caller)
+		if (found == m_addr_to_hle_function_map.end())
 		{
-			PC = (GPR[0]._u32[3] & 0x3fffc) - 4;
+			throw EXCEPTION("HLE function not registered (PC=0x%05x)", pc);
 		}
+
+		if (const auto return_to_caller = found->second(*this))
+		{
+			pc = (gpr[0]._u32[3] & 0x3fffc) - 4;
+		}
+
 		return;
 	}
 
@@ -1472,7 +1445,7 @@ spu_thread::spu_thread(u32 entry, const std::string& name, u32 stack_size, u32 p
 {
 	auto spu = idm::make_ptr<SPUThread>(name, 0x13370666);
 
-	spu->PC = entry;
+	spu->pc = entry;
 
 	thread = std::move(spu);
 }
diff --git a/rpcs3/Emu/Cell/SPUThread.h b/rpcs3/Emu/Cell/SPUThread.h
index ec1b1c981c..3f3bc97cdc 100644
--- a/rpcs3/Emu/Cell/SPUThread.h
+++ b/rpcs3/Emu/Cell/SPUThread.h
@@ -135,16 +135,15 @@ enum
 	SPU_RdSigNotify2_offs = 0x1C00C,
 };
 
-union spu_channel_t
+struct spu_channel_t
 {
+	// set to true if SPU thread must be notified after SPU channel operation
+	thread_local static bool notification_required;
+
 	struct sync_var_t
 	{
-		struct
-		{
-			u32 waiting : 1; // waiting flag (0..1)
-			u32 count : 1; // channel count (0..1)
-		};
-		
+		bool count; // value available
+		bool wait; // notification required
 		u32 value;
 	};
 
@@ -154,93 +153,75 @@ public:
 	// returns true on success
 	bool try_push(u32 value)
 	{
-		return sync_var.atomic_op([=](sync_var_t& data) -> bool
+		const auto old = sync_var.atomic_op([=](sync_var_t& data)
 		{
-			if (data.count == 0)
+			if ((data.wait = data.count) == false)
 			{
-				data.waiting = 0;
-				data.count = 1;
+				data.count = true;
 				data.value = value;
-
-				return true;
 			}
-
-			data.waiting = 1;
-			return false;
 		});
+
+		return !old.count;
 	}
 
-	// push performing bitwise OR with previous value, returns true if needs signaling
-	bool push_or(u32 value)
+	// push performing bitwise OR with previous value, may require notification
+	void push_or(u32 value)
 	{
-		return sync_var.atomic_op([=](sync_var_t& data) -> bool
+		const auto old = sync_var.atomic_op([=](sync_var_t& data)
 		{
-			data.count = 1;
+			data.count = true;
+			data.wait = false;
 			data.value |= value;
-
-			if (data.waiting)
-			{
-				data.waiting = 0;
-
-				return true;
-			}
-
-			return false;
 		});
+
+		notification_required = old.wait;
 	}
 
-	// push unconditionally (overwriting previous value), returns true if needs signaling
-	bool push(u32 value)
+	// push unconditionally (overwriting previous value), may require notification
+	void push(u32 value)
 	{
-		return sync_var.atomic_op([=](sync_var_t& data) -> bool
+		const auto old = sync_var.atomic_op([=](sync_var_t& data)
 		{
-			data.count = 1;
+			data.count = true;
+			data.wait = false;
 			data.value = value;
-
-			if (data.waiting)
-			{
-				data.waiting = 0;
-
-				return true;
-			}
-
-			return false;
 		});
+
+		notification_required = old.wait;
 	}
 
-	// returns true on success and u32 value
+	// returns true on success and loaded value
 	std::tuple<bool, u32> try_pop()
 	{
-		return sync_var.atomic_op([](sync_var_t& data)
+		const auto old = sync_var.atomic_op([](sync_var_t& data)
 		{
-			const auto result = std::make_tuple(data.count != 0, u32{ data.value });
-
-			data.waiting = data.count == 0;
-			data.count = 0;
-			data.value = 0;
-
-			return result;
+			data.wait = !data.count;
+			data.count = false;
+			data.value = 0; // ???
 		});
+
+		return std::tie(old.count, old.value);
 	}
 
-	// pop unconditionally (loading last value), returns u32 value and bool value (true if needs signaling)
-	std::tuple<u32, bool> pop()
+	// pop unconditionally (loading last value), may require notification
+	u32 pop()
 	{
-		return sync_var.atomic_op([](sync_var_t& data)
+		const auto old = sync_var.atomic_op([](sync_var_t& data)
 		{
-			const auto result = std::make_tuple(u32{ data.value }, data.waiting != 0);
-
-			data.waiting = 0;
-			data.count = 0;
+			data.wait = false;
+			data.count = false;
 			// value is not cleared and may be read again
-			
-			return result;
 		});
+
+		notification_required = old.wait;
+
+		return old.value;
 	}
 
-	void set_value(u32 value, u32 count = 1)
+	void set_value(u32 value, bool count = true)
 	{
-		sync_var.store({ { 0, count }, value });
+		sync_var.store({ count, false, value });
 	}
 
 	u32 get_value() volatile
@@ -358,7 +339,7 @@ struct spu_int_ctrl_t
 	void clear(u64 ints);
 };
 
-struct g_spu_imm_table_t
+struct spu_imm_table_t
 {
 	v128 fsmb[65536]; // table for FSMB, FSMBI instructions
 	v128 fsmh[256]; // table for FSMH instruction
@@ -388,7 +369,7 @@ struct g_spu_imm_table_t
 	}
 	const scale;
 
-	g_spu_imm_table_t()
+	spu_imm_table_t()
 	{
 		for (u32 i = 0; i < sizeof(fsm) / sizeof(fsm[0]); i++)
 		{
@@ -440,7 +421,7 @@ struct g_spu_imm_table_t
 	}
 };
 
-extern const g_spu_imm_table_t g_spu_imm;
+extern const spu_imm_table_t g_spu_imm;
 
 enum FPSCR_EX
 {
@@ -543,9 +524,11 @@ public:
 
 class SPUThread : public CPUThread
 {
+	friend class spu_recompiler;
+
 public:
-	v128 GPR[128]; // General-Purpose Registers
-	SPU_FPSCR FPSCR;
+	std::array<v128, 128> gpr; // General-Purpose Registers
+	SPU_FPSCR fpscr;
 
 	std::unordered_map<u32, std::function<bool(SPUThread& SPU)>> m_addr_to_hle_function_map;
 
@@ -586,43 +569,34 @@ public:
 	std::array<std::pair<u32, std::weak_ptr<lv2_event_queue_t>>, 32> spuq; // Event Queue Keys for SPU Thread
 	std::weak_ptr<lv2_event_queue_t> spup[64]; // SPU Ports
 
-	u32 PC = 0;
+	u32 pc = 0; // 
 	const u32 index; // SPU index
 	const u32 offset; // SPU LS offset
 
 	void push_snr(u32 number, u32 value)
 	{
-		if (number == 0)
+		// get channel
+		const auto channel =
+			number == 0 ? &ch_snr1 :
+			number == 1 ? &ch_snr2 : throw EXCEPTION("Unexpected");
+
+		// check corresponding SNR register settings
+		if ((snr_config >> number) & 1)
 		{
-			if (snr_config & 1)
-			{
-				if (!ch_snr1.push_or(value)) return;
-			}
-			else
-			{
-				if (!ch_snr1.push(value)) return;
-			}
-		}
-		else if (number == 1)
-		{
-			if (snr_config & 2)
-			{
-				if (!ch_snr2.push_or(value)) return;
-			}
-			else
-			{
-				if (!ch_snr2.push(value)) return;
-			}
+			channel->push_or(value);
 		}
 		else
 		{
-			throw EXCEPTION("Unexpected");
+			channel->push(value);
 		}
 
-		// notify if required
-		std::lock_guard<std::mutex> lock(mutex);
+		if (channel->notification_required)
+		{
+			// lock for reliable notification
+			std::lock_guard<std::mutex> lock(mutex);
 
-		cv.notify_one();
+			cv.notify_one();
+		}
 	}
 
 	void do_dma_transfer(u32 cmd, spu_mfc_arg_t args);
@@ -683,6 +657,7 @@ public:
 	}
 
 	std::function<void(SPUThread&)> custom_task;
+	std::exception_ptr pending_exception;
 
 protected:
 	SPUThread(CPUThreadType type, const std::string& name, std::function<std::string()> thread_name, u32 index, u32 offset);
@@ -694,7 +669,7 @@ public:
 	virtual bool is_paused() const override;
 
 	virtual void dump_info() const override;
-	virtual u32 get_pc() const override { return PC; }
+	virtual u32 get_pc() const override { return pc; }
 	virtual u32 get_offset() const override { return offset; }
 	virtual void do_run() override;
 	virtual void task() override;
@@ -709,7 +684,7 @@ public:
 	{
 		std::string ret = "Registers:\n=========\n";
 
-		for(uint i=0; i<128; ++i) ret += fmt::format("GPR[%d] = 0x%s\n", i, GPR[i].to_hex().c_str());
+		for(uint i=0; i<128; ++i) ret += fmt::format("GPR[%d] = 0x%s\n", i, gpr[i].to_hex().c_str());
 
 		return ret;
 	}
@@ -721,7 +696,7 @@ public:
 		{
 			long reg_index;
 			reg_index = atol(reg.substr(first_brk + 1, reg.length()-2).c_str());
-			if (reg.find("GPR")==0) return fmt::format("%016llx%016llx",  GPR[reg_index]._u64[1], GPR[reg_index]._u64[0]);
+			if (reg.find("GPR")==0) return fmt::format("%016llx%016llx",  gpr[reg_index]._u64[1], gpr[reg_index]._u64[0]);
 		}
 		return "";
 	}
@@ -747,8 +722,8 @@ public:
 				{
 					return false;
 				}
-				GPR[reg_index]._u64[0] = (u64)reg_value0;
-				GPR[reg_index]._u64[1] = (u64)reg_value1;
+				gpr[reg_index]._u64[0] = (u64)reg_value0;
+				gpr[reg_index]._u64[1] = (u64)reg_value1;
 				return true;
 			}
 		}
diff --git a/rpcs3/Emu/Memory/vm.cpp b/rpcs3/Emu/Memory/vm.cpp
index 1bdb95915e..5f0d83739c 100644
--- a/rpcs3/Emu/Memory/vm.cpp
+++ b/rpcs3/Emu/Memory/vm.cpp
@@ -1083,17 +1083,17 @@ namespace vm
 		{
 			SPUThread& context = static_cast<SPUThread&>(cpu);
 
-			old_pos = context.GPR[1]._u32[3];
-			context.GPR[1]._u32[3] -= align(size, 16);
-			context.GPR[1]._u32[3] &= ~(align_v - 1);
+			old_pos = context.gpr[1]._u32[3];
+			context.gpr[1]._u32[3] -= align(size, 16);
+			context.gpr[1]._u32[3] &= ~(align_v - 1);
 
-			if (context.GPR[1]._u32[3] >= 0x40000) // extremely rough
+			if (context.gpr[1]._u32[3] >= 0x40000) // extremely rough
 			{
 				throw EXCEPTION("Stack overflow (size=0x%x, align=0x%x, SP=LS:0x%05x)", size, align_v, old_pos);
 			}
 			else
 			{
-				return context.GPR[1]._u32[3] + context.offset;
+				return context.gpr[1]._u32[3] + context.offset;
 			}
 		}
 
@@ -1144,12 +1144,12 @@ namespace vm
 		{
 			SPUThread& context = static_cast<SPUThread&>(cpu);
 
-			if (context.GPR[1]._u32[3] + context.offset != addr)
+			if (context.gpr[1]._u32[3] + context.offset != addr)
 			{
-				throw EXCEPTION("Stack inconsistency (addr=0x%x, SP=LS:0x%05x, old_pos=LS:0x%05x)", addr, context.GPR[1]._u32[3], old_pos);
+				throw EXCEPTION("Stack inconsistency (addr=0x%x, SP=LS:0x%05x, old_pos=LS:0x%05x)", addr, context.gpr[1]._u32[3], old_pos);
 			}
 
-			context.GPR[1]._u32[3] = old_pos;
+			context.gpr[1]._u32[3] = old_pos;
 			return;
 		}
 
diff --git a/rpcs3/Emu/SysCalls/Modules/cellSpurs.cpp b/rpcs3/Emu/SysCalls/Modules/cellSpurs.cpp
index 31788d1514..6414f63437 100644
--- a/rpcs3/Emu/SysCalls/Modules/cellSpurs.cpp
+++ b/rpcs3/Emu/SysCalls/Modules/cellSpurs.cpp
@@ -600,24 +600,24 @@ s32 spursWakeUpShutdownCompletionWaiter(PPUThread& ppu, vm::ptr<CellSpurs> spurs
 		return CELL_SPURS_POLICY_MODULE_ERROR_STAT;
 	}
 
-	auto& wklF     = wid < CELL_SPURS_MAX_WORKLOAD ? spurs->wklF1[wid] : spurs->wklF2[wid & 0x0F];
-	auto& wklEvent = wid < CELL_SPURS_MAX_WORKLOAD ? spurs->wklEvent1[wid] : spurs->wklEvent2[wid & 0x0F];
+	const auto wklF     = wid < CELL_SPURS_MAX_WORKLOAD ? &spurs->wklF1[wid] : &spurs->wklF2[wid & 0x0F];
+	const auto wklEvent = wid < CELL_SPURS_MAX_WORKLOAD ? &spurs->wklEvent1[wid] : &spurs->wklEvent2[wid & 0x0F];
 
-	if (wklF.hook)
+	if (wklF->hook)
 	{
-		wklF.hook(ppu, spurs, wid, wklF.hookArg);
+		wklF->hook(ppu, spurs, wid, wklF->hookArg);
 
-		assert(wklEvent.load() & 0x01);
-		assert(wklEvent.load() & 0x02);
-		assert((wklEvent.load() & 0x20) == 0);
-		wklEvent |= 0x20;
+		assert(wklEvent->load() & 0x01);
+		assert(wklEvent->load() & 0x02);
+		assert((wklEvent->load() & 0x20) == 0);
+		*wklEvent |= 0x20;
 	}
 
 	s32 rc = CELL_OK;
-	if (!wklF.hook || wklEvent.load() & 0x10)
+	if (!wklF->hook || wklEvent->load() & 0x10)
 	{
-		assert(wklF.x28 == 2);
-		rc = sys_semaphore_post((u32)wklF.sem, 1);
+		assert(wklF->x28 == 2);
+		rc = sys_semaphore_post((u32)wklF->sem, 1);
 	}
 
 	return rc;
@@ -1724,8 +1724,8 @@ s32 cellSpursSetPriorities(vm::ptr<CellSpurs> spurs, u32 wid, vm::cptr<u8> prior
 		prio <<= 8;
 	}
 
-	auto& wklInfo = wid < CELL_SPURS_MAX_WORKLOAD ? spurs->wklInfo1[wid] : spurs->wklInfo2[wid];
-	*((be_t<u64>*)wklInfo.priority) = prio;
+	const auto wklInfo = wid < CELL_SPURS_MAX_WORKLOAD ? &spurs->wklInfo1[wid] : &spurs->wklInfo2[wid];
+	*((be_t<u64>*)wklInfo->priority) = prio;
 
 	spurs->sysSrvMsgUpdateWorkload.store(0xFF);
 	spurs->sysSrvMessage.store(0xFF);
@@ -2296,8 +2296,8 @@ s32 spursAddWorkload(
 	spurs->wklFlagReceiver.compare_and_swap(wnum, 0xff);
 
 	u32 res_wkl;
-	CellSpurs::WorkloadInfo& wkl = wnum <= 15 ? spurs->wklInfo1[wnum] : spurs->wklInfo2[wnum & 0xf];
-	spurs->wklMskB.atomic_op([spurs, &wkl, wnum, &res_wkl](be_t<u32>& v)
+	const auto wkl = wnum <= 15 ? &spurs->wklInfo1[wnum] : &spurs->wklInfo2[wnum & 0xf];
+	spurs->wklMskB.atomic_op([spurs, wkl, wnum, &res_wkl](be_t<u32>& v)
 	{
 		const u32 mask = v & ~(0x80000000u >> wnum);
 		res_wkl = 0;
@@ -2306,22 +2306,22 @@ s32 spursAddWorkload(
 		{
 			if (mask & m)
 			{
-				CellSpurs::WorkloadInfo& current = i <= 15 ? spurs->wklInfo1[i] : spurs->wklInfo2[i & 0xf];
-				if (current.addr == wkl.addr)
+				const auto current = i <= 15 ? &spurs->wklInfo1[i] : &spurs->wklInfo2[i & 0xf];
+				if (current->addr == wkl->addr)
 				{
 					// if a workload with identical policy module found
-					res_wkl = current.uniqueId.load();
+					res_wkl = current->uniqueId.load();
 					break;
 				}
 				else
 				{
-					k |= 0x80000000 >> current.uniqueId.load();
+					k |= 0x80000000 >> current->uniqueId.load();
 					res_wkl = cntlz32(~k);
 				}
 			}
 		}
 
-		wkl.uniqueId.exchange((u8)res_wkl);
+		wkl->uniqueId.exchange((u8)res_wkl);
 		v = mask | (0x80000000u >> wnum);
 	});
 	assert(res_wkl <= 31);
diff --git a/rpcs3/Emu/SysCalls/Modules/cellSpursSpu.cpp b/rpcs3/Emu/SysCalls/Modules/cellSpursSpu.cpp
index f23b39b13b..b615987270 100644
--- a/rpcs3/Emu/SysCalls/Modules/cellSpursSpu.cpp
+++ b/rpcs3/Emu/SysCalls/Modules/cellSpursSpu.cpp
@@ -90,14 +90,14 @@ void cellSpursModulePutTrace(CellSpursTracePacket * packet, u32 dmaTagId) {
 u32 cellSpursModulePollStatus(SPUThread & spu, u32 * status) {
     auto ctxt = vm::get_ptr<SpursKernelContext>(spu.offset + 0x100);
 
-    spu.GPR[3]._u32[3] = 1;
+    spu.gpr[3]._u32[3] = 1;
     if (ctxt->spurs->flags1 & SF1_32_WORKLOADS) {
         spursKernel2SelectWorkload(spu);
     } else {
         spursKernel1SelectWorkload(spu);
     }
 
-    auto result = spu.GPR[3]._u64[1];
+    auto result = spu.gpr[3]._u64[1];
     if (status) {
         *status = (u32)result;
     }
@@ -109,7 +109,7 @@ u32 cellSpursModulePollStatus(SPUThread & spu, u32 * status) {
 /// Exit current workload
 void cellSpursModuleExit(SPUThread & spu) {
     auto ctxt = vm::get_ptr<SpursKernelContext>(spu.offset + 0x100);
-    spu.PC = ctxt->exitToKernelAddr - 4;
+    spu.pc = ctxt->exitToKernelAddr - 4;
     throw SpursModuleExit();
 }
 
@@ -164,7 +164,7 @@ bool spursKernel1SelectWorkload(SPUThread & spu) {
     // The first and only argument to this function is a boolean that is set to false if the function
     // is called by the SPURS kernel and set to true if called by cellSpursModulePollStatus.
     // If the first argument is true then the shared data is not updated with the result.
-    const auto isPoll = spu.GPR[3]._u32[3];
+    const auto isPoll = spu.gpr[3]._u32[3];
 
     u32 wklSelectedId;
     u32 pollStatus;
@@ -310,7 +310,7 @@ bool spursKernel1SelectWorkload(SPUThread & spu) {
 
     u64 result          = (u64)wklSelectedId << 32;
     result             |= pollStatus;
-    spu.GPR[3]._u64[1]  = result;
+    spu.gpr[3]._u64[1]  = result;
     return true;
 }
 
@@ -321,7 +321,7 @@ bool spursKernel2SelectWorkload(SPUThread & spu) {
     // The first and only argument to this function is a boolean that is set to false if the function
     // is called by the SPURS kernel and set to true if called by cellSpursModulePollStatus.
     // If the first argument is true then the shared data is not updated with the result.
-    const auto isPoll = spu.GPR[3]._u32[3];
+    const auto isPoll = spu.gpr[3]._u32[3];
 
     u32 wklSelectedId;
     u32 pollStatus;
@@ -457,7 +457,7 @@ bool spursKernel2SelectWorkload(SPUThread & spu) {
 
     u64 result          = (u64)wklSelectedId << 32;
     result             |= pollStatus;
-    spu.GPR[3]._u64[1]  = result;
+    spu.gpr[3]._u64[1]  = result;
     return true;
 }
 
@@ -501,12 +501,12 @@ void spursKernelDispatchWorkload(SPUThread & spu, u64 widAndPollStatus) {
     }
 
     // Run workload
-    spu.GPR[0]._u32[3] = ctxt->exitToKernelAddr;
-    spu.GPR[1]._u32[3] = 0x3FFB0;
-    spu.GPR[3]._u32[3] = 0x100;
-    spu.GPR[4]._u64[1] = wklInfo->arg;
-    spu.GPR[5]._u32[3] = pollStatus;
-    spu.PC = 0xA00 - 4;
+    spu.gpr[0]._u32[3] = ctxt->exitToKernelAddr;
+    spu.gpr[1]._u32[3] = 0x3FFB0;
+    spu.gpr[3]._u32[3] = 0x100;
+    spu.gpr[4]._u64[1] = wklInfo->arg;
+    spu.gpr[5]._u32[3] = pollStatus;
+    spu.pc = 0xA00 - 4;
 }
 
 /// SPURS kernel workload exit
@@ -515,14 +515,14 @@ bool spursKernelWorkloadExit(SPUThread & spu) {
     auto isKernel2 = ctxt->spurs->flags1 & SF1_32_WORKLOADS ? true : false;
 
     // Select next workload to run
-    spu.GPR[3].clear();
+    spu.gpr[3].clear();
     if (isKernel2) {
         spursKernel2SelectWorkload(spu);
     } else {
         spursKernel1SelectWorkload(spu);
     }
 
-    spursKernelDispatchWorkload(spu, spu.GPR[3]._u64[1]);
+    spursKernelDispatchWorkload(spu, spu.gpr[3]._u64[1]);
     return false;
 }
 
@@ -537,8 +537,8 @@ bool spursKernelEntry(SPUThread & spu) {
     memset(ctxt, 0, sizeof(SpursKernelContext));
 
     // Save arguments
-    ctxt->spuNum = spu.GPR[3]._u32[3];
-    ctxt->spurs.set(spu.GPR[4]._u64[1]);
+    ctxt->spuNum = spu.gpr[3]._u32[3];
+    ctxt->spurs.set(spu.gpr[4]._u64[1]);
 
     auto isKernel2 = ctxt->spurs->flags1 & SF1_32_WORKLOADS ? true : false;
 
@@ -579,9 +579,9 @@ bool spursKernelEntry(SPUThread & spu) {
 
 /// Entry point of the system service
 bool spursSysServiceEntry(SPUThread & spu) {
-    auto ctxt       = vm::get_ptr<SpursKernelContext>(spu.offset + spu.GPR[3]._u32[3]);
-    auto arg        = spu.GPR[4]._u64[1];
-    auto pollStatus = spu.GPR[5]._u32[3];
+    auto ctxt       = vm::get_ptr<SpursKernelContext>(spu.offset + spu.gpr[3]._u32[3]);
+    auto arg        = spu.gpr[4]._u64[1];
+    auto pollStatus = spu.gpr[5]._u32[3];
 
     try {
         if (ctxt->wklCurrentId == CELL_SPURS_SYS_SERVICE_WORKLOAD_ID) {
@@ -1080,16 +1080,16 @@ enum SpursTasksetRequest {
 /// Taskset PM entry point
 bool spursTasksetEntry(SPUThread & spu) {
     auto ctxt       = vm::get_ptr<SpursTasksetContext>(spu.offset + 0x2700);
-    auto kernelCtxt = vm::get_ptr<SpursKernelContext>(spu.offset + spu.GPR[3]._u32[3]);
+    auto kernelCtxt = vm::get_ptr<SpursKernelContext>(spu.offset + spu.gpr[3]._u32[3]);
 
-    auto arg        = spu.GPR[4]._u64[1];
-    auto pollStatus = spu.GPR[5]._u32[3];
+    auto arg        = spu.gpr[4]._u64[1];
+    auto pollStatus = spu.gpr[5]._u32[3];
 
     // Initialise memory and save args
     memset(ctxt, 0, sizeof(*ctxt));
     ctxt->taskset.set(arg);
     memcpy(ctxt->moduleId, "SPURSTASK MODULE", sizeof(ctxt->moduleId));
-    ctxt->kernelMgmtAddr = spu.GPR[3]._u32[3];
+    ctxt->kernelMgmtAddr = spu.gpr[3]._u32[3];
     ctxt->syscallAddr    = CELL_SPURS_TASKSET_PM_SYSCALL_ADDR;
     ctxt->spuNum         = kernelCtxt->spuNum;
     ctxt->dmaTagId       = kernelCtxt->dmaTagId;
@@ -1120,14 +1120,14 @@ bool spursTasksetSyscallEntry(SPUThread & spu) {
 
     try {
         // Save task context
-        ctxt->savedContextLr = spu.GPR[0];
-        ctxt->savedContextSp = spu.GPR[1];
+        ctxt->savedContextLr = spu.gpr[0];
+        ctxt->savedContextSp = spu.gpr[1];
         for (auto i = 0; i < 48; i++) {
-            ctxt->savedContextR80ToR127[i] = spu.GPR[80 + i];
+            ctxt->savedContextR80ToR127[i] = spu.gpr[80 + i];
         }
 
         // Handle the syscall
-        spu.GPR[3]._u32[3] = spursTasksetProcessSyscall(spu, spu.GPR[3]._u32[3], spu.GPR[4]._u32[3]);
+        spu.gpr[3]._u32[3] = spursTasksetProcessSyscall(spu, spu.gpr[3]._u32[3], spu.gpr[4]._u32[3]);
 
         // Resume the previously executing task if the syscall did not cause a context switch
         throw EXCEPTION("Broken (TODO)");
@@ -1147,13 +1147,13 @@ void spursTasksetResumeTask(SPUThread & spu) {
     auto ctxt = vm::get_ptr<SpursTasksetContext>(spu.offset + 0x2700);
 
     // Restore task context
-    spu.GPR[0] = ctxt->savedContextLr;
-    spu.GPR[1] = ctxt->savedContextSp;
+    spu.gpr[0] = ctxt->savedContextLr;
+    spu.gpr[1] = ctxt->savedContextSp;
     for (auto i = 0; i < 48; i++) {
-        spu.GPR[80 + i] = ctxt->savedContextR80ToR127[i];
+        spu.gpr[80 + i] = ctxt->savedContextR80ToR127[i];
     }
 
-    spu.PC = spu.GPR[0]._u32[3] - 4;
+    spu.pc = spu.gpr[0]._u32[3] - 4;
 }
 
 /// Start a task
@@ -1161,15 +1161,15 @@ void spursTasksetStartTask(SPUThread & spu, CellSpursTaskArgument & taskArgs) {
     auto ctxt    = vm::get_ptr<SpursTasksetContext>(spu.offset + 0x2700);
     auto taskset = vm::get_ptr<CellSpursTaskset>(spu.offset + 0x2700);
 
-    spu.GPR[2].clear();
-    spu.GPR[3]         = v128::from64r(taskArgs._u64[0], taskArgs._u64[1]);
-    spu.GPR[4]._u64[1] = taskset->args;
-    spu.GPR[4]._u64[0] = taskset->spurs.addr();
+    spu.gpr[2].clear();
+    spu.gpr[3]         = v128::from64r(taskArgs._u64[0], taskArgs._u64[1]);
+    spu.gpr[4]._u64[1] = taskset->args;
+    spu.gpr[4]._u64[0] = taskset->spurs.addr();
     for (auto i = 5; i < 128; i++) {
-        spu.GPR[i].clear();
+        spu.gpr[i].clear();
     }
 
-    spu.PC = ctxt->savedContextLr.value()._u32[3] - 4;
+    spu.pc = ctxt->savedContextLr.value()._u32[3] - 4;
 }
 
 /// Process a request and update the state of the taskset
@@ -1382,10 +1382,10 @@ void spursTasksetOnTaskExit(SPUThread & spu, u64 addr, u32 taskId, s32 exitCode,
 
     memcpy(vm::get_ptr(spu.offset + 0x10000), vm::get_ptr(addr & -0x80), (addr & 0x7F) << 11);
 
-    spu.GPR[3]._u64[1] = ctxt->taskset.addr();
-    spu.GPR[4]._u32[3] = taskId;
-    spu.GPR[5]._u32[3] = exitCode;
-    spu.GPR[6]._u64[1] = args;
+    spu.gpr[3]._u64[1] = ctxt->taskset.addr();
+    spu.gpr[4]._u32[3] = taskId;
+    spu.gpr[5]._u32[3] = exitCode;
+    spu.gpr[6]._u64[1] = args;
     spu.fast_call(0x10000);
 }
 
@@ -1422,7 +1422,7 @@ s32 spursTasketSaveTaskContext(SPUThread & spu) {
 
     // Get the processor context
     v128 r;
-    spu.FPSCR.Read(r);
+    spu.fpscr.Read(r);
     ctxt->savedContextFpscr = r;
     ctxt->savedSpuWriteEventMask = spu.get_ch_value(SPU_RdEventMask);
     ctxt->savedWriteTagGroupQueryMask = spu.get_ch_value(MFC_RdTagMask);
@@ -1539,7 +1539,7 @@ void spursTasksetDispatch(SPUThread & spu) {
         //spursDmaWaitForCompletion(spu, 1 << ctxt->dmaTagId);
 
         // Restore saved registers
-        spu.FPSCR.Write(ctxt->savedContextFpscr.value());
+        spu.fpscr.Write(ctxt->savedContextFpscr.value());
         spu.set_ch_value(MFC_WrTagMask, ctxt->savedWriteTagGroupQueryMask);
         spu.set_ch_value(SPU_WrEventMask, ctxt->savedSpuWriteEventMask);
 
@@ -1555,7 +1555,7 @@ void spursTasksetDispatch(SPUThread & spu) {
             return;
         }
 
-        spu.GPR[3].clear();
+        spu.gpr[3].clear();
         spursTasksetResumeTask(spu);
     }
 }
diff --git a/rpcs3/Emu/SysCalls/lv2/sys_spu.cpp b/rpcs3/Emu/SysCalls/lv2/sys_spu.cpp
index 795b028327..2ca96f6239 100644
--- a/rpcs3/Emu/SysCalls/lv2/sys_spu.cpp
+++ b/rpcs3/Emu/SysCalls/lv2/sys_spu.cpp
@@ -209,11 +209,9 @@ s32 sys_spu_thread_get_exit_status(u32 id, vm::ptr<u32> status)
 
 	// TODO: check CELL_ESTAT condition
 
-	bool notify;
+	*status = thread->ch_out_mbox.pop();
 
-	std::tie(*status, notify) = thread->ch_out_mbox.pop();
-
-	if (notify)
+	if (thread->ch_out_mbox.notification_required)
 	{
 		throw EXCEPTION("Unexpected");
 	}
@@ -316,12 +314,12 @@ s32 sys_spu_thread_group_start(u32 id)
 			// TODO: use segment info
 			std::memcpy(vm::get_ptr<void>(t->offset), vm::get_ptr<void>(image->addr), 256 * 1024);
 
-			t->PC = image->entry_point;
+			t->pc = image->entry_point;
 			t->run();
-			t->GPR[3] = v128::from64(0, args.arg1);
-			t->GPR[4] = v128::from64(0, args.arg2);
-			t->GPR[5] = v128::from64(0, args.arg3);
-			t->GPR[6] = v128::from64(0, args.arg4);
+			t->gpr[3] = v128::from64(0, args.arg1);
+			t->gpr[4] = v128::from64(0, args.arg2);
+			t->gpr[5] = v128::from64(0, args.arg3);
+			t->gpr[6] = v128::from64(0, args.arg4);
 
 			t->status.exchange(SPU_STATUS_RUNNING);
 		}
@@ -708,7 +706,7 @@ s32 sys_spu_thread_write_spu_mb(u32 id, u32 value)
 
 	if (thread->ch_in_mbox.push(value))
 	{
-		// notify if necessary
+		// lock for reliable notification
 		std::lock_guard<std::mutex> lock(thread->mutex);
 
 		thread->cv.notify_one();
@@ -1323,13 +1321,11 @@ s32 sys_raw_spu_read_puint_mb(u32 id, vm::ptr<u32> value)
 		return CELL_ESRCH;
 	}
 
-	bool notify;
+	*value = thread->ch_out_intr_mbox.pop();
 
-	std::tie(*value, notify) = thread->ch_out_intr_mbox.pop();
-
-	if (notify)
+	if (thread->ch_out_intr_mbox.notification_required)
 	{
-		// notify if necessary
+		// lock for reliable notification
 		std::lock_guard<std::mutex> lock(thread->mutex);
 
 		thread->cv.notify_one();
diff --git a/rpcs3/Emu/System.h b/rpcs3/Emu/System.h
index 4e90e083b4..331efc0ea2 100644
--- a/rpcs3/Emu/System.h
+++ b/rpcs3/Emu/System.h
@@ -142,8 +142,7 @@ public:
 
 	void ResetInfo()
 	{
-		m_info.~EmuInfo();
-		new (&m_info) EmuInfo();
+		m_info = {};
 	}
 
 	void SetTLSData(u32 addr, u32 filesz, u32 memsz)
diff --git a/rpcs3/Gui/InterpreterDisAsm.cpp b/rpcs3/Gui/InterpreterDisAsm.cpp
index 5703a9b0c3..bba6acddbf 100644
--- a/rpcs3/Gui/InterpreterDisAsm.cpp
+++ b/rpcs3/Gui/InterpreterDisAsm.cpp
@@ -7,7 +7,6 @@
 #include "Emu/CPU/CPUThreadManager.h"
 #include "Emu/Cell/PPUDecoder.h"
 #include "Emu/Cell/PPUDisAsm.h"
-#include "Emu/Cell/SPUDecoder.h"
 #include "Emu/Cell/SPUDisAsm.h"
 #include "Emu/ARMv7/ARMv7DisAsm.h"
 #include "Emu/ARMv7/ARMv7Decoder.h"
@@ -27,7 +26,6 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent)
 	, PC(0)
 	, CPU(nullptr)
 	, m_item_count(30)
-	, decoder(nullptr)
 	, disasm(nullptr)
 {
 	wxBoxSizer* s_p_main = new wxBoxSizer(wxVERTICAL);
@@ -121,11 +119,27 @@ void InterpreterDisAsmFrame::OnSelectUnit(wxCommandEvent& event)
 {
 	CPU = (CPUThread*)event.GetClientData();
 
-	delete decoder;
-	//delete disasm;
-	decoder = nullptr;
+	decoder.reset();
 	disasm = nullptr;
 
+	class SPUDecoder : public CPUDecoder
+	{
+		std::unique_ptr<SPUDisAsm> disasm;
+
+	public:
+		SPUDecoder(SPUDisAsm* disasm)
+			: disasm(disasm)
+		{
+		}
+
+		virtual u32 DecodeMemory(const u32 address) override
+		{
+			disasm->do_disasm(vm::ps3::read32(address));
+
+			return 4;
+		}
+	};
+
 	if(CPU)
 	{
 		switch(CPU->get_type())
@@ -133,7 +147,7 @@ void InterpreterDisAsmFrame::OnSelectUnit(wxCommandEvent& event)
 		case CPU_THREAD_PPU:
 		{
 			PPUDisAsm* dis_asm = new PPUDisAsm(CPUDisAsm_InterpreterMode);
-			decoder = new PPUDecoder(dis_asm);
+			decoder = std::make_unique<PPUDecoder>(dis_asm);
 			disasm = dis_asm;
 		}
 		break;
@@ -141,9 +155,9 @@ void InterpreterDisAsmFrame::OnSelectUnit(wxCommandEvent& event)
 		case CPU_THREAD_SPU:
 		case CPU_THREAD_RAW_SPU:
 		{
-			SPUDisAsm& dis_asm = *new SPUDisAsm(CPUDisAsm_InterpreterMode);
-			decoder = new SPUDecoder(dis_asm);
-			disasm = &dis_asm;
+			SPUDisAsm* dis_asm = new SPUDisAsm(CPUDisAsm_InterpreterMode);
+			decoder = std::make_unique<SPUDecoder>(dis_asm);
+			disasm = dis_asm;
 		}
 		break;
 
@@ -511,12 +525,12 @@ void InterpreterDisAsmFrame::InstrKey(wxListEvent& event)
 	{
 	case 'E':
 		// TODO:: Syphurith: It is said the InstructionEditorDialog would be immediately destroyed.
-		InstructionEditorDialog(this, pc, CPU, decoder, disasm);
+		InstructionEditorDialog(this, pc, CPU, decoder.get(), disasm);
 		DoUpdate();
 		return;
 	case 'R':
 		// TODO:: Syphurith: Eh Similiar for this one.
-		RegisterEditorDialog(this, pc, CPU, decoder, disasm);
+		RegisterEditorDialog(this, pc, CPU, decoder.get(), disasm);
 		DoUpdate();
 		return;
 	}
diff --git a/rpcs3/Gui/InterpreterDisAsm.h b/rpcs3/Gui/InterpreterDisAsm.h
index 0233527f91..7a9838de99 100644
--- a/rpcs3/Gui/InterpreterDisAsm.h
+++ b/rpcs3/Gui/InterpreterDisAsm.h
@@ -7,7 +7,7 @@ class InterpreterDisAsmFrame : public wxPanel
 {
 	wxListView* m_list;
 	CPUDisAsm* disasm;
-	CPUDecoder* decoder;
+	std::unique_ptr<CPUDecoder> decoder;
 	u64 PC;
 	std::vector<u32> remove_markedPC;
 	wxTextCtrl* m_regs;
diff --git a/rpcs3/Gui/SettingsDialog.cpp b/rpcs3/Gui/SettingsDialog.cpp
index c78e3657f1..162b4c7c54 100644
--- a/rpcs3/Gui/SettingsDialog.cpp
+++ b/rpcs3/Gui/SettingsDialog.cpp
@@ -148,8 +148,8 @@ SettingsDialog::SettingsDialog(wxWindow *parent)
 #endif
 
 	wxArrayString spu_decoder_modes;
-	spu_decoder_modes.Add("Interpreter");
-	spu_decoder_modes.Add("Interpreter 2");
+	spu_decoder_modes.Add("Interpreter (precise)");
+	spu_decoder_modes.Add("Interpreter (fast)");
 	spu_decoder_modes.Add("Recompiler (ASMJIT)");
 	rbox_spu_decoder = new wxRadioBox(p_core, wxID_ANY, "SPU Decoder", wxDefaultPosition, wxSize(215, -1), spu_decoder_modes, 1);
 
diff --git a/rpcs3/Loader/ELF64.cpp b/rpcs3/Loader/ELF64.cpp
index b656f28b66..dce872cdd7 100644
--- a/rpcs3/Loader/ELF64.cpp
+++ b/rpcs3/Loader/ELF64.cpp
@@ -330,6 +330,14 @@ namespace loader
 					continue;
 				}
 
+				if (Ini.LoadLibLv2.GetValue())
+				{
+					if (module->name != "liblv2.sprx")
+					{
+						continue;
+					}
+				}
+
 				elf64 sprx_handler;
 
 				vfsFile fsprx(lle_dir.GetPath() + "/" + module->name);
@@ -340,19 +348,19 @@ namespace loader
 
 					if (sprx_handler.is_sprx())
 					{
-						IniEntry<bool> load_lib;
-						load_lib.Init(sprx_handler.sprx_get_module_name(), "LLE");
+						if (!Ini.LoadLibLv2.GetValue())
+						{
+							IniEntry<bool> load_lib;
+							load_lib.Init(sprx_handler.sprx_get_module_name(), "LLE");
 
-						if (!load_lib.LoadValue(false))
-						{
-							LOG_WARNING(LOADER, "Skipped LLE library '%s'", sprx_handler.sprx_get_module_name().c_str());
-							continue;
-						}
-						else
-						{
-							LOG_WARNING(LOADER, "Loading LLE library '%s'", sprx_handler.sprx_get_module_name().c_str());
+							if (!load_lib.LoadValue(false))
+							{
+								continue;
+							}
 						}
 
+						LOG_WARNING(LOADER, "Loading LLE library '%s'", sprx_handler.sprx_get_module_name().c_str());
+
 						sprx_info info;
 						sprx_handler.load_sprx(info);
 
diff --git a/rpcs3/emucore.vcxproj b/rpcs3/emucore.vcxproj
index 806833b1d6..c5bb69b897 100644
--- a/rpcs3/emucore.vcxproj
+++ b/rpcs3/emucore.vcxproj
@@ -53,6 +53,8 @@
     <ClCompile Include="..\Utilities\VirtualMemory.cpp" />
     <ClCompile Include="Emu\Cell\PPUInterpreter.cpp" />
     <ClCompile Include="Emu\Cell\PPULLVMRecompilerCore.cpp" />
+    <ClCompile Include="Emu\Cell\SPUAnalyser.cpp" />
+    <ClCompile Include="Emu\Cell\SPUASMJITRecompiler.cpp" />
     <ClCompile Include="Emu\Cell\SPUInterpreter.cpp" />
     <ClCompile Include="Emu\IdManager.cpp" />
     <ClCompile Include="Emu\RSX\CgBinaryFragmentProgram.cpp" />
@@ -183,7 +185,7 @@
     </ClCompile>
     <ClCompile Include="Emu\Cell\PPUThread.cpp" />
     <ClCompile Include="Emu\Cell\RawSPUThread.cpp" />
-    <ClCompile Include="Emu\Cell\SPURecompilerCore.cpp" />
+    <ClCompile Include="Emu\Cell\SPURecompiler.cpp" />
     <ClCompile Include="Emu\Cell\SPUThread.cpp" />
     <ClCompile Include="Emu\CPU\CPUThread.cpp" />
     <ClCompile Include="Emu\CPU\CPUThreadManager.cpp" />
@@ -485,12 +487,11 @@
     <ClInclude Include="Emu\Cell\PPUOpcodes.h" />
     <ClInclude Include="Emu\Cell\PPUThread.h" />
     <ClInclude Include="Emu\Cell\RawSPUThread.h" />
+    <ClInclude Include="Emu\Cell\SPUAnalyser.h" />
+    <ClInclude Include="Emu\Cell\SPUASMJITRecompiler.h" />
     <ClInclude Include="Emu\Cell\SPUContext.h" />
-    <ClInclude Include="Emu\Cell\SPUDecoder.h" />
     <ClInclude Include="Emu\Cell\SPUDisAsm.h" />
-    <ClInclude Include="Emu\Cell\SPUInstrTable.h" />
     <ClInclude Include="Emu\Cell\SPUInterpreter.h" />
-    <ClInclude Include="Emu\Cell\SPUInterpreter2.h" />
     <ClInclude Include="Emu\Cell\SPUOpcodes.h" />
     <ClInclude Include="Emu\Cell\SPURecompiler.h" />
     <ClInclude Include="Emu\Cell\SPUThread.h" />
diff --git a/rpcs3/emucore.vcxproj.filters b/rpcs3/emucore.vcxproj.filters
index fe0c57f077..0040ea3ba1 100644
--- a/rpcs3/emucore.vcxproj.filters
+++ b/rpcs3/emucore.vcxproj.filters
@@ -350,9 +350,6 @@
     <ClCompile Include="Emu\Cell\RawSPUThread.cpp">
       <Filter>Emu\CPU\Cell</Filter>
     </ClCompile>
-    <ClCompile Include="Emu\Cell\SPURecompilerCore.cpp">
-      <Filter>Emu\CPU\Cell</Filter>
-    </ClCompile>
     <ClCompile Include="Emu\Cell\SPUThread.cpp">
       <Filter>Emu\CPU\Cell</Filter>
     </ClCompile>
@@ -986,6 +983,15 @@
     <ClCompile Include="..\Utilities\VirtualMemory.cpp">
       <Filter>Utilities</Filter>
     </ClCompile>
+    <ClCompile Include="Emu\Cell\SPURecompiler.cpp">
+      <Filter>Emu\CPU\Cell</Filter>
+    </ClCompile>
+    <ClCompile Include="Emu\Cell\SPUAnalyser.cpp">
+      <Filter>Emu\CPU\Cell</Filter>
+    </ClCompile>
+    <ClCompile Include="Emu\Cell\SPUASMJITRecompiler.cpp">
+      <Filter>Emu\CPU\Cell</Filter>
+    </ClCompile>
   </ItemGroup>
   <ItemGroup>
     <ClInclude Include="Crypto\aes.h">
@@ -1252,15 +1258,9 @@
     <ClInclude Include="Emu\Cell\RawSPUThread.h">
       <Filter>Emu\CPU\Cell</Filter>
     </ClInclude>
-    <ClInclude Include="Emu\Cell\SPUDecoder.h">
-      <Filter>Emu\CPU\Cell</Filter>
-    </ClInclude>
     <ClInclude Include="Emu\Cell\SPUDisAsm.h">
       <Filter>Emu\CPU\Cell</Filter>
     </ClInclude>
-    <ClInclude Include="Emu\Cell\SPUInstrTable.h">
-      <Filter>Emu\CPU\Cell</Filter>
-    </ClInclude>
     <ClInclude Include="Emu\Cell\SPUInterpreter.h">
       <Filter>Emu\CPU\Cell</Filter>
     </ClInclude>
@@ -1627,9 +1627,6 @@
     <ClInclude Include="Emu\Cell\PPUInterpreter2.h">
       <Filter>Emu\CPU\Cell</Filter>
     </ClInclude>
-    <ClInclude Include="Emu\Cell\SPUInterpreter2.h">
-      <Filter>Emu\CPU\Cell</Filter>
-    </ClInclude>
     <ClInclude Include="..\Utilities\File.h">
       <Filter>Utilities</Filter>
     </ClInclude>
@@ -1873,5 +1870,11 @@
     <ClInclude Include="..\Utilities\VirtualMemory.h">
       <Filter>Utilities</Filter>
     </ClInclude>
+    <ClInclude Include="Emu\Cell\SPUASMJITRecompiler.h">
+      <Filter>Emu\CPU\Cell</Filter>
+    </ClInclude>
+    <ClInclude Include="Emu\Cell\SPUAnalyser.h">
+      <Filter>Emu\CPU\Cell</Filter>
+    </ClInclude>
   </ItemGroup>
 </Project>
\ No newline at end of file