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https://github.com/RPCS3/rpcs3.git
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SPU: add the concept of inaccurate reservations
Implement cellSpursRequestIdleSpu
This commit is contained in:
Eladash
Ivan
parent
d36cf71a2d
commit
82b1a2bd7a
@ -326,7 +326,7 @@ s32 cellSpursReadyCountAdd(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, u32 wid, v
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//s32 cellSpursUnsetExceptionEventHandler();
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s32 _cellSpursWorkloadFlagReceiver(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, u32 wid, u32 is_set);
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//s32 _cellSpursWorkloadFlagReceiver2();
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//s32 cellSpursRequestIdleSpu();
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//error_code cellSpursRequestIdleSpu();
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//
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// SPURS taskset functions
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@ -1781,7 +1781,7 @@ s32 cellSpursSetMaxContention(vm::ptr<CellSpurs> spurs, u32 wid, u32 maxContenti
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/// Set the priority of a workload on each SPU
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s32 cellSpursSetPriorities(vm::ptr<CellSpurs> spurs, u32 wid, vm::cptr<u8[8]> priorities)
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{
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cellSpurs.warning("cellSpursSetPriorities(spurs=*0x%x, wid=%d, priorities=*0x%x)", spurs, wid, priorities);
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cellSpurs.trace("cellSpursSetPriorities(spurs=*0x%x, wid=%d, priorities=*0x%x)", spurs, wid, priorities);
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if (!spurs)
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{
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@ -1850,9 +1850,9 @@ s32 cellSpursSetPriority(vm::ptr<CellSpurs> spurs, u32 wid, u32 spuId, u32 prior
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if (spurs->exception)
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return CELL_SPURS_CORE_ERROR_STAT;
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vm::light_op(spurs->wklInfo(wid).priority[spuId], [&](u8& v){ atomic_storage<u8>::release(v, priority); });
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vm::light_op(spurs->sysSrvMsgUpdateWorkload, [&](atomic_t<u8>& v){ v.bit_test_set(spuId); });
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vm::light_op(spurs->sysSrvMessage, [&](atomic_t<u8>& v){ v.bit_test_set(spuId); });
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vm::light_op<true>(spurs->wklInfo(wid).priority[spuId], [&](u8& v){ atomic_storage<u8>::release(v, priority); });
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vm::light_op<true>(spurs->sysSrvMsgUpdateWorkload, [&](atomic_t<u8>& v){ v.bit_test_set(spuId); });
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vm::light_op<true>(spurs->sysSrvMessage, [&](atomic_t<u8>& v){ v.bit_test_set(spuId); });
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return CELL_OK;
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}
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@ -2357,14 +2357,45 @@ s32 _spurs::add_workload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32>
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return CELL_SPURS_POLICY_MODULE_ERROR_AGAIN;
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}
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auto& spurs_res = vm::reservation_acquire(spurs.addr());
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auto& spurs_res2 = vm::reservation_acquire(spurs.addr() + 0x80);
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if (!spurs_res2.fetch_op([&](u64& r)
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{
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if (r & vm::rsrv_unique_lock)
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{
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return false;
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}
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r += 1;
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return true;
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}).second)
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{
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vm::reservation_shared_lock_internal(spurs_res2);
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}
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if (!spurs_res.fetch_op([&](u64& r)
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{
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if (r & vm::rsrv_unique_lock)
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{
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return false;
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}
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r += 1;
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return true;
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}).second)
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{
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vm::reservation_shared_lock_internal(spurs_res);
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}
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u32 index = wnum & 0xf;
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if (wnum <= 15)
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{
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ensure((spurs->wklCurrentContention[wnum] & 0xf) == 0);
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ensure((spurs->wklPendingContention[wnum] & 0xf) == 0);
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spurs->wklState1[wnum] = SPURS_WKL_STATE_PREPARING;
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spurs->wklState1[wnum].release(SPURS_WKL_STATE_PREPARING);
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spurs->wklStatus1[wnum] = 0;
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spurs->wklEvent1[wnum] = 0;
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spurs->wklEvent1[wnum].release(0);
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spurs->wklInfo1[wnum].addr = pm;
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spurs->wklInfo1[wnum].arg = data;
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spurs->wklInfo1[wnum].size = size;
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@ -2392,15 +2423,15 @@ s32 _spurs::add_workload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32>
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spurs->wklMinContention[wnum] = minContention > 8 ? 8 : minContention;
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}
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spurs->wklReadyCount1[wnum] = 0;
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spurs->wklReadyCount1[wnum].release(0);
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}
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else
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{
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ensure((spurs->wklCurrentContention[index] & 0xf0) == 0);
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ensure((spurs->wklPendingContention[index] & 0xf0) == 0);
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spurs->wklState2[index] = SPURS_WKL_STATE_PREPARING;
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spurs->wklState2[index].release(SPURS_WKL_STATE_PREPARING);
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spurs->wklStatus2[index] = 0;
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spurs->wklEvent2[index] = 0;
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spurs->wklEvent2[index].release(0);
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spurs->wklInfo2[index].addr = pm;
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spurs->wklInfo2[index].arg = data;
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spurs->wklInfo2[index].size = size;
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@ -2422,21 +2453,31 @@ s32 _spurs::add_workload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32>
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spurs->wklEvent2[index] |= 2;
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}
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spurs->wklIdleSpuCountOrReadyCount2[wnum] = 0;
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spurs->wklIdleSpuCountOrReadyCount2[wnum].release(0);
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}
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vm::atomic_op(spurs->wklMaxContention[index], [&](u8& v)
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spurs->wklMaxContention[index].atomic_op([&](u8& v)
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{
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v &= (wnum <= 15 ? 0xf0 : 0x0f);
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v |= (maxContention > 8 ? 8 : maxContention) << (wnum < CELL_SPURS_MAX_WORKLOAD ? 0 : 4);
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});
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vm::atomic_op<true>((wnum <= 15 ? spurs->wklSignal1 : spurs->wklSignal2), [&](be_t<u16>& data)
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(wnum <= 15 ? spurs->wklSignal1 : spurs->wklSignal2).atomic_op([&](be_t<u16>& data)
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{
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data &= ~(0x8000 >> index);
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});
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spurs->wklFlagReceiver.compare_and_swap(wnum, 0xff);
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// Attempt to avoid CAS
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if (spurs->wklFlagReceiver == wnum && spurs->wklFlagReceiver.compare_and_swap(wnum, 0xff))
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{
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//
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}
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spurs_res += 127;
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spurs_res2 += 127;
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spurs_res.notify_all(-128);
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spurs_res2.notify_all(-128);
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u32 res_wkl;
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const auto wkl = &spurs->wklInfo(wnum);
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@ -2470,7 +2511,7 @@ s32 _spurs::add_workload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32>
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});
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ensure((res_wkl <= 31));
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vm::light_op(spurs->sysSrvMsgUpdateWorkload, [](atomic_t<u8>& v){ v.release(0xff); });
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vm::light_op<true>(spurs->sysSrvMsgUpdateWorkload, [](atomic_t<u8>& v){ v.release(0xff); });
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vm::light_op<true>(spurs->sysSrvMessage, [](atomic_t<u8>& v){ v.release(0xff); });
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return CELL_OK;
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}
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@ -2478,7 +2519,7 @@ s32 _spurs::add_workload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32>
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/// Add workload
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s32 cellSpursAddWorkload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32> wid, vm::cptr<void> pm, u32 size, u64 data, vm::cptr<u8[8]> priority, u32 minCnt, u32 maxCnt)
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{
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cellSpurs.warning("cellSpursAddWorkload(spurs=*0x%x, wid=*0x%x, pm=*0x%x, size=0x%x, data=0x%llx, priority=*0x%x, minCnt=0x%x, maxCnt=0x%x)",
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cellSpurs.trace("cellSpursAddWorkload(spurs=*0x%x, wid=*0x%x, pm=*0x%x, size=0x%x, data=0x%llx, priority=*0x%x, minCnt=0x%x, maxCnt=0x%x)",
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spurs, wid, pm, size, data, priority, minCnt, maxCnt);
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return _spurs::add_workload(ppu, spurs, wid, pm, size, data, *priority, minCnt, maxCnt, vm::null, vm::null, vm::null, vm::null);
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@ -2487,7 +2528,7 @@ s32 cellSpursAddWorkload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32>
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/// Add workload
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s32 cellSpursAddWorkloadWithAttribute(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, vm::ptr<u32> wid, vm::cptr<CellSpursWorkloadAttribute> attr)
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{
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cellSpurs.warning("cellSpursAddWorkloadWithAttribute(spurs=*0x%x, wid=*0x%x, attr=*0x%x)", spurs, wid, attr);
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cellSpurs.trace("cellSpursAddWorkloadWithAttribute(spurs=*0x%x, wid=*0x%x, attr=*0x%x)", spurs, wid, attr);
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if (!attr)
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{
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@ -2647,7 +2688,7 @@ s32 cellSpursRemoveSystemWorkloadForUtility()
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/// Remove workload
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s32 cellSpursRemoveWorkload(ppu_thread& ppu, vm::ptr<CellSpurs> spurs, u32 wid)
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{
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cellSpurs.warning("cellSpursRemoveWorkload(spurs=*0x%x, wid=%u)", spurs, wid);
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cellSpurs.trace("cellSpursRemoveWorkload(spurs=*0x%x, wid=%u)", spurs, wid);
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if (!spurs)
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return CELL_SPURS_POLICY_MODULE_ERROR_NULL_POINTER;
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@ -3101,9 +3142,42 @@ s32 _cellSpursWorkloadFlagReceiver2()
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}
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/// Request assignment of idle SPUs
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s32 cellSpursRequestIdleSpu()
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s32 cellSpursRequestIdleSpu(vm::ptr<CellSpurs> spurs, u32 wid, u32 count)
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{
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UNIMPLEMENTED_FUNC(cellSpurs);
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cellSpurs.trace("cellSpursRequestIdleSpu(spurs=*0x%x, wid=%d, count=%d)", spurs, wid, count);
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if (!spurs)
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{
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return CELL_SPURS_CORE_ERROR_NULL_POINTER;
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}
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if (!spurs.aligned())
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{
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return CELL_SPURS_CORE_ERROR_ALIGN;
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}
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// Old API: This function doesn't support 32 workloads
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if (spurs->flags1 & SF1_32_WORKLOADS)
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{
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return CELL_SPURS_CORE_ERROR_STAT;
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}
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if (wid >= CELL_SPURS_MAX_WORKLOAD || count >= CELL_SPURS_MAX_SPU)
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{
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return CELL_SPURS_CORE_ERROR_INVAL;
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}
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if ((spurs->wklEnabled.load() & (0x80000000u >> wid)) == 0u)
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{
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return CELL_SPURS_CORE_ERROR_SRCH;
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}
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if (spurs->exception)
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{
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return CELL_SPURS_CORE_ERROR_STAT;
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}
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vm::light_op<true>(spurs->wklIdleSpuCountOrReadyCount2[wid], FN(x.release(static_cast<u8>(count))));
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return CELL_OK;
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}
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@ -5221,7 +5295,7 @@ s32 cellSpursSemaphoreGetTasksetAddress()
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return CELL_OK;
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}
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DECLARE(ppu_module_manager::cellSpurs)("cellSpurs", []()
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DECLARE(ppu_module_manager::cellSpurs)("cellSpurs", [](ppu_static_module* _this)
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{
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// Core
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REG_FUNC(cellSpurs, cellSpursInitialize);
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@ -5383,4 +5457,20 @@ DECLARE(ppu_module_manager::cellSpurs)("cellSpurs", []()
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REG_FUNC(cellSpurs, cellSpursTraceStart);
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REG_FUNC(cellSpurs, cellSpursTraceStop);
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REG_FUNC(cellSpurs, cellSpursTraceFinalize);
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_this->add_init_func([](ppu_static_module*)
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{
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const auto val = g_cfg.core.spu_accurate_reservations ? MFF_PERFECT : MFF_FORCED_HLE;
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REINIT_FUNC(cellSpursSetPriorities).flag(val);
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REINIT_FUNC(cellSpursAddWorkload).flag(val);
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REINIT_FUNC(cellSpursAddWorkloadWithAttribute).flag(val);
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REINIT_FUNC(cellSpursShutdownWorkload).flag(val);
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REINIT_FUNC(cellSpursReadyCountStore).flag(val);
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REINIT_FUNC(cellSpursSetPriority).flag(val);
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REINIT_FUNC(cellSpursTraceInitialize).flag(val);
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REINIT_FUNC(cellSpursWaitForWorkloadShutdown).flag(val);
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REINIT_FUNC(cellSpursRequestIdleSpu).flag(val);
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REINIT_FUNC(cellSpursRemoveWorkload).flag(val);
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});
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});
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@ -1453,6 +1453,20 @@ void spu_thread::cpu_task()
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return fmt::format("%sSPU[0x%07x] Thread (%s) [0x%05x]", type >= spu_type::raw ? type == spu_type::isolated ? "Iso" : "Raw" : "", cpu->lv2_id, *name_cache.get(), cpu->pc);
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};
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if (!spurs_addr)
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{
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// Evaluate it
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if (!group)
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{
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spurs_addr = -0x80; // Some invalid non-0 address
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}
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else
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{
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const u32 arg = static_cast<u32>(group->args[index][1]);
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spurs_addr = group->name.ends_with("CellSpursKernelGroup"sv) && vm::check_addr(arg) ? arg : 0u - 0x80;
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}
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}
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if (jit)
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{
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while (true)
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@ -2827,6 +2841,13 @@ bool spu_thread::do_putllc(const spu_mfc_cmd& args)
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return false;
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}
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if (!g_cfg.core.spu_accurate_reservations && addr - spurs_addr <= 0x80)
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{
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mov_rdata(vm::_ref<spu_rdata_t>(addr), to_write);
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res += 64;
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return true;
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}
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if (g_use_rtm) [[likely]]
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{
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switch (u64 count = spu_putllc_tx(addr, rtime, rdata, to_write))
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@ -814,6 +814,7 @@ public:
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const std::add_pointer_t<u8> ls; // SPU LS pointer
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const u32 option; // sys_spu_thread_initialize option
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const u32 lv2_id; // The actual id that is used by syscalls
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u32 spurs_addr = 0;
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spu_thread* next_cpu{}; // LV2 thread queues' node link
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@ -41,6 +41,7 @@ struct cfg_root : cfg::node
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cfg::_enum<spu_block_size_type> spu_block_size{ this, "SPU Block Size", spu_block_size_type::safe };
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cfg::_bool spu_accurate_getllar{ this, "Accurate GETLLAR", false, true };
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cfg::_bool spu_accurate_dma{ this, "Accurate SPU DMA", false };
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cfg::_bool spu_accurate_reservations{ this, "Accurate SPU Reservations", true };
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cfg::_bool accurate_cache_line_stores{ this, "Accurate Cache Line Stores", false };
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cfg::_bool rsx_accurate_res_access{this, "Accurate RSX reservation access", false, true};
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