diff --git a/.gitignore b/.gitignore index 00fb6fe69b..559dedada0 100644 --- a/.gitignore +++ b/.gitignore @@ -70,3 +70,6 @@ rpcs3/x64/* .DS_Store rpcs3/Emu/SysCalls/Modules/prx_*.h + +/CMakeFiles/ +CMakeCache.txt diff --git a/Utilities/Thread.cpp b/Utilities/Thread.cpp index fb194a7323..c2e8273140 100644 --- a/Utilities/Thread.cpp +++ b/Utilities/Thread.cpp @@ -807,9 +807,9 @@ bool handle_access_violation(u32 addr, bool is_writing, x64_context* context) // check if address is RawSPU MMIO register if (addr - RAW_SPU_BASE_ADDR < (6 * RAW_SPU_OFFSET) && (addr % RAW_SPU_OFFSET) >= RAW_SPU_PROB_OFFSET) { - auto t = Emu.GetCPU().GetRawSPUThread((addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET); + auto thread = Emu.GetCPU().GetRawSPUThread((addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET); - if (!t) + if (!thread) { return false; } @@ -820,14 +820,12 @@ bool handle_access_violation(u32 addr, bool is_writing, x64_context* context) return false; } - auto& spu = static_cast(*t); - switch (op) { case X64OP_LOAD: { u32 value; - if (is_writing || !spu.ReadReg(addr, value) || !put_x64_reg_value(context, reg, d_size, _byteswap_ulong(value))) + if (is_writing || !thread->ReadReg(addr, value) || !put_x64_reg_value(context, reg, d_size, _byteswap_ulong(value))) { return false; } @@ -837,7 +835,7 @@ bool handle_access_violation(u32 addr, bool is_writing, x64_context* context) case X64OP_STORE: { u64 reg_value; - if (!is_writing || !get_x64_reg_value(context, reg, d_size, i_size, reg_value) || !spu.WriteReg(addr, _byteswap_ulong((u32)reg_value))) + if (!is_writing || !get_x64_reg_value(context, reg, d_size, i_size, reg_value) || !thread->WriteReg(addr, _byteswap_ulong((u32)reg_value))) { return false; } @@ -1251,11 +1249,11 @@ void thread_t::start(std::function name, std::function fu throw EXCEPTION("Thread already exists"); } - // create new ctrl and assign it - auto ctrl = std::make_shared(std::move(name)); + // create new thread control variable + m_thread = std::make_shared(std::move(name)); // start thread - ctrl->m_thread = std::thread([ctrl, func]() + m_thread->m_thread = std::thread([](std::shared_ptr ctrl, std::function func) { g_thread_count++; @@ -1326,10 +1324,7 @@ void thread_t::start(std::function name, std::function fu #if defined(_MSC_VER) _set_se_translator(old_se_translator); #endif - }); - - // set - m_thread = std::move(ctrl); + }, m_thread, std::move(func)); } void thread_t::detach() @@ -1339,8 +1334,11 @@ void thread_t::detach() throw EXCEPTION("Invalid thread"); } + // +clear m_thread const auto ctrl = std::move(m_thread); + cv.notify_all(); + ctrl->m_thread.detach(); } @@ -1356,8 +1354,11 @@ void thread_t::join(std::unique_lock& lock) throw EXCEPTION("Deadlock"); } + // +clear m_thread const auto ctrl = std::move(m_thread); + cv.notify_all(); + // wait for completion while (ctrl->joinable) { @@ -1381,8 +1382,11 @@ void thread_t::join() throw EXCEPTION("Deadlock"); } + // +clear m_thread const auto ctrl = std::move(m_thread); + cv.notify_all(); + ctrl->m_thread.join(); } diff --git a/rpcs3/Emu/CPU/CPUDecoder.h b/rpcs3/Emu/CPU/CPUDecoder.h index 5ff68f0e70..4a6d0021b0 100644 --- a/rpcs3/Emu/CPU/CPUDecoder.h +++ b/rpcs3/Emu/CPU/CPUDecoder.h @@ -59,7 +59,7 @@ public: virtual void operator ()(TO* op, u32 code) const { - (op->*m_func)((T1)m_arg_func_1(code)); + (op->*m_func)(static_cast(m_arg_func_1(code))); } }; @@ -83,8 +83,8 @@ public: virtual void operator ()(TO* op, u32 code) const { (op->*m_func)( - (T1)m_arg_func_1(code), - (T2)m_arg_func_2(code) + static_cast(m_arg_func_1(code)), + static_cast(m_arg_func_2(code)) ); } }; @@ -114,9 +114,9 @@ public: virtual void operator ()(TO* op, u32 code) const { (op->*m_func)( - (T1)m_arg_func_1(code), - (T2)m_arg_func_2(code), - (T3)m_arg_func_3(code) + static_cast(m_arg_func_1(code)), + static_cast(m_arg_func_2(code)), + static_cast(m_arg_func_3(code)) ); } }; @@ -149,10 +149,10 @@ public: virtual void operator ()(TO* op, u32 code) const { (op->*m_func)( - (T1)m_arg_func_1(code), - (T2)m_arg_func_2(code), - (T3)m_arg_func_3(code), - (T4)m_arg_func_4(code) + static_cast(m_arg_func_1(code)), + static_cast(m_arg_func_2(code)), + static_cast(m_arg_func_3(code)), + static_cast(m_arg_func_4(code)) ); } }; @@ -188,11 +188,11 @@ public: virtual void operator ()(TO* op, u32 code) const { (op->*m_func)( - (T1)m_arg_func_1(code), - (T2)m_arg_func_2(code), - (T3)m_arg_func_3(code), - (T4)m_arg_func_4(code), - (T5)m_arg_func_5(code) + static_cast(m_arg_func_1(code)), + static_cast(m_arg_func_2(code)), + static_cast(m_arg_func_3(code)), + static_cast(m_arg_func_4(code)), + static_cast(m_arg_func_5(code)) ); } }; @@ -231,12 +231,12 @@ public: virtual void operator ()(TO* op, u32 code) const { (op->*m_func)( - (T1)m_arg_func_1(code), - (T2)m_arg_func_2(code), - (T3)m_arg_func_3(code), - (T4)m_arg_func_4(code), - (T5)m_arg_func_5(code), - (T6)m_arg_func_6(code) + static_cast(m_arg_func_1(code)), + static_cast(m_arg_func_2(code)), + static_cast(m_arg_func_3(code)), + static_cast(m_arg_func_4(code)), + static_cast(m_arg_func_5(code)), + static_cast(m_arg_func_6(code)) ); } }; diff --git a/rpcs3/Emu/CPU/CPUThread.cpp b/rpcs3/Emu/CPU/CPUThread.cpp index 7d24a08bbe..f923d316f5 100644 --- a/rpcs3/Emu/CPU/CPUThread.cpp +++ b/rpcs3/Emu/CPU/CPUThread.cpp @@ -168,14 +168,28 @@ void CPUThread::Step() void CPUThread::Sleep() { - m_state ^= CPU_STATE_SLEEP; + m_state += CPU_STATE_MAX; + m_state |= CPU_STATE_SLEEP; cv.notify_one(); } void CPUThread::Awake() { - m_state ^= CPU_STATE_SLEEP; + // must be called after the corresponding Sleep() call + + m_state.atomic_op([](u64& state) + { + if (state < CPU_STATE_MAX) + { + throw EXCEPTION("Sleep()/Awake() inconsistency"); + } + + if ((state -= CPU_STATE_MAX) < CPU_STATE_MAX) + { + state &= ~CPU_STATE_SLEEP; + } + }); cv.notify_one(); } diff --git a/rpcs3/Emu/CPU/CPUThread.h b/rpcs3/Emu/CPU/CPUThread.h index 5fb64486bd..2a5dc80ae5 100644 --- a/rpcs3/Emu/CPU/CPUThread.h +++ b/rpcs3/Emu/CPU/CPUThread.h @@ -14,11 +14,13 @@ enum CPUThreadType enum : u64 { CPU_STATE_STOPPED = (1ull << 0), // basic execution state (stopped by default), removed by Exec() - CPU_STATE_PAUSED = (1ull << 1), // paused by debugger (manually or after step execution) - CPU_STATE_SLEEP = (1ull << 2), - CPU_STATE_STEP = (1ull << 3), - CPU_STATE_DEAD = (1ull << 4), - CPU_STATE_RETURN = (1ull << 5), + CPU_STATE_PAUSED = (1ull << 1), // pauses thread execution, set by the debugger (manually or after step execution) + CPU_STATE_SLEEP = (1ull << 2), // shouldn't affect thread execution, set by Sleep() call, removed by the latest Awake() call, may possibly indicate waiting state of the thread + CPU_STATE_STEP = (1ull << 3), // forces the thread to pause after executing just one instruction or something appropriate, set by the debugger + CPU_STATE_DEAD = (1ull << 4), // indicates irreversible exit of the thread + CPU_STATE_RETURN = (1ull << 5), // used for callback return + + CPU_STATE_MAX = (1ull << 6), // added to (subtracted from) m_state by Sleep()/Awake() calls to trigger status check }; // "HLE return" exception event @@ -71,16 +73,35 @@ public: virtual void InitStack() = 0; virtual void CloseStack() = 0; + // initialize thread void Run(); + + // called by the debugger, don't use void Pause(); + + // called by the debugger, don't use void Resume(); + + // stop thread execution void Stop(); + + // start thread execution (removing STOP status) void Exec(); + + // exit thread execution void Exit(); - void Step(); // set STEP status, don't use - void Sleep(); // flip SLEEP status, don't use - void Awake(); // flip SLEEP status, don't use - bool CheckStatus(); // process m_state flags, returns true if the checker must return + + // called by the debugger, don't use + void Step(); + + // trigger thread status check + void Sleep(); + + // untrigger thread status check + void Awake(); + + // process m_state flags, returns true if the checker must return + bool CheckStatus(); std::string GetFName() const { diff --git a/rpcs3/Emu/Cell/PPCDisAsm.h b/rpcs3/Emu/Cell/PPCDisAsm.h index 2666033919..737c60dd60 100644 --- a/rpcs3/Emu/Cell/PPCDisAsm.h +++ b/rpcs3/Emu/Cell/PPCDisAsm.h @@ -43,7 +43,7 @@ protected: { Write(fmt::Format("%s v%d,r%d,r%d", FixOp(op).c_str(), v0, r1, r2)); } - void DisAsm_CR1_F2_RC(const std::string& op, u32 cr0, u32 f0, u32 f1, bool rc) + void DisAsm_CR1_F2_RC(const std::string& op, u32 cr0, u32 f0, u32 f1, u32 rc) { Write(fmt::Format("%s%s cr%d,f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), cr0, f0, f1)); } @@ -59,7 +59,7 @@ protected: { Write(fmt::Format("%s %d,r%d,%d #%x", FixOp(op).c_str(), i0, r0, imm0, imm0)); } - void DisAsm_INT1_R1_RC(const std::string& op, u32 i0, u32 r0, bool rc) + void DisAsm_INT1_R1_RC(const std::string& op, u32 i0, u32 r0, u32 rc) { Write(fmt::Format("%s%s %d,r%d", FixOp(op).c_str(), (rc ? "." : ""), i0, r0)); } @@ -67,11 +67,11 @@ protected: { DisAsm_INT1_R1_RC(op, i0, r0, false); } - void DisAsm_F4_RC(const std::string& op, u32 f0, u32 f1, u32 f2, u32 f3, bool rc) + void DisAsm_F4_RC(const std::string& op, u32 f0, u32 f1, u32 f2, u32 f3, u32 rc) { Write(fmt::Format("%s%s f%d,f%d,f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), f0, f1, f2, f3)); } - void DisAsm_F3_RC(const std::string& op, u32 f0, u32 f1, u32 f2, bool rc) + void DisAsm_F3_RC(const std::string& op, u32 f0, u32 f1, u32 f2, u32 rc) { Write(fmt::Format("%s%s f%d,f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), f0, f1, f2)); } @@ -79,7 +79,7 @@ protected: { DisAsm_F3_RC(op, f0, f1, f2, false); } - void DisAsm_F2_RC(const std::string& op, u32 f0, u32 f1, bool rc) + void DisAsm_F2_RC(const std::string& op, u32 f0, u32 f1, u32 rc) { Write(fmt::Format("%s%s f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), f0, f1)); } @@ -97,7 +97,7 @@ protected: Write(fmt::Format("%s f%d,r%d(r%d)", FixOp(op).c_str(), f0, r0, r1)); } - void DisAsm_F1_IMM_R1_RC(const std::string& op, u32 f0, s32 imm0, u32 r0, bool rc) + void DisAsm_F1_IMM_R1_RC(const std::string& op, u32 f0, s32 imm0, u32 r0, u32 rc) { if(m_mode == CPUDisAsm_CompilerElfMode) { @@ -111,11 +111,11 @@ protected: { DisAsm_F1_IMM_R1_RC(op, f0, imm0, r0, false); } - void DisAsm_F1_RC(const std::string& op, u32 f0, bool rc) + void DisAsm_F1_RC(const std::string& op, u32 f0, u32 rc) { Write(fmt::Format("%s%s f%d", FixOp(op).c_str(), (rc ? "." : ""), f0)); } - void DisAsm_R1_RC(const std::string& op, u32 r0, bool rc) + void DisAsm_R1_RC(const std::string& op, u32 r0, u32 rc) { Write(fmt::Format("%s%s r%d", FixOp(op).c_str(), (rc ? "." : ""), r0)); } @@ -123,11 +123,11 @@ protected: { DisAsm_R1_RC(op, r0, false); } - void DisAsm_R2_OE_RC(const std::string& op, u32 r0, u32 r1, u32 oe, bool rc) + void DisAsm_R2_OE_RC(const std::string& op, u32 r0, u32 r1, u32 oe, u32 rc) { Write(fmt::Format("%s%s%s r%d,r%d", FixOp(op).c_str(), (oe ? "o" : ""), (rc ? "." : ""), r0, r1)); } - void DisAsm_R2_RC(const std::string& op, u32 r0, u32 r1, bool rc) + void DisAsm_R2_RC(const std::string& op, u32 r0, u32 r1, u32 rc) { DisAsm_R2_OE_RC(op, r0, r1, false, rc); } @@ -135,15 +135,15 @@ protected: { DisAsm_R2_RC(op, r0, r1, false); } - void DisAsm_R3_OE_RC(const std::string& op, u32 r0, u32 r1, u32 r2, u32 oe, bool rc) + void DisAsm_R3_OE_RC(const std::string& op, u32 r0, u32 r1, u32 r2, u32 oe, u32 rc) { Write(fmt::Format("%s%s%s r%d,r%d,r%d", FixOp(op).c_str(), (oe ? "o" : ""), (rc ? "." : ""), r0, r1, r2)); } - void DisAsm_R3_INT2_RC(const std::string& op, u32 r0, u32 r1, u32 r2, s32 i0, s32 i1, bool rc) + void DisAsm_R3_INT2_RC(const std::string& op, u32 r0, u32 r1, u32 r2, s32 i0, s32 i1, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,r%d,%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, r2, i0, i1)); } - void DisAsm_R3_RC(const std::string& op, u32 r0, u32 r1, u32 r2, bool rc) + void DisAsm_R3_RC(const std::string& op, u32 r0, u32 r1, u32 r2, u32 rc) { DisAsm_R3_OE_RC(op, r0, r1, r2, false, rc); } @@ -151,7 +151,7 @@ protected: { DisAsm_R3_RC(op, r0, r1, r2, false); } - void DisAsm_R2_INT3_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2, bool rc) + void DisAsm_R2_INT3_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,%d,%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, i0, i1, i2)); } @@ -159,7 +159,7 @@ protected: { DisAsm_R2_INT3_RC(op, r0, r1, i0, i1, i2, false); } - void DisAsm_R2_INT2_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, bool rc) + void DisAsm_R2_INT2_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, i0, i1)); } @@ -167,7 +167,7 @@ protected: { DisAsm_R2_INT2_RC(op, r0, r1, i0, i1, false); } - void DisAsm_R2_INT1_RC(const std::string& op, u32 r0, u32 r1, s32 i0, bool rc) + void DisAsm_R2_INT1_RC(const std::string& op, u32 r0, u32 r1, s32 i0, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, i0)); } @@ -197,7 +197,7 @@ protected: { Write(fmt::Format("%s cr%d,r%d,%d #%x", FixOp(op).c_str(), cr0, r0, imm0, imm0)); } - void DisAsm_CR1_R2_RC(const std::string& op, u32 cr0, u32 r0, u32 r1, bool rc) + void DisAsm_CR1_R2_RC(const std::string& op, u32 cr0, u32 r0, u32 r1, u32 rc) { Write(fmt::Format("%s%s cr%d,r%d,r%d", FixOp(op).c_str(), (rc ? "." : ""), cr0, r0, r1)); } diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h index 86d988ee67..0ad5d216c1 100644 --- a/rpcs3/Emu/Cell/PPUDisAsm.h +++ b/rpcs3/Emu/Cell/PPUDisAsm.h @@ -50,7 +50,7 @@ private: { Write(fmt::Format("%s v%d,r%d,r%d", FixOp(op).c_str(), v0, r1, r2)); } - void DisAsm_CR1_F2_RC(const std::string& op, u32 cr0, u32 f0, u32 f1, bool rc) + void DisAsm_CR1_F2_RC(const std::string& op, u32 cr0, u32 f0, u32 f1, u32 rc) { Write(fmt::Format("%s%s cr%d,f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), cr0, f0, f1)); } @@ -66,7 +66,7 @@ private: { Write(fmt::Format("%s %d,r%d,%d #%x", FixOp(op).c_str(), i0, r0, imm0, imm0)); } - void DisAsm_INT1_R1_RC(const std::string& op, u32 i0, u32 r0, bool rc) + void DisAsm_INT1_R1_RC(const std::string& op, u32 i0, u32 r0, u32 rc) { Write(fmt::Format("%s%s %d,r%d", FixOp(op).c_str(), (rc ? "." : ""), i0, r0)); } @@ -74,11 +74,11 @@ private: { DisAsm_INT1_R1_RC(op, i0, r0, false); } - void DisAsm_F4_RC(const std::string& op, u32 f0, u32 f1, u32 f2, u32 f3, bool rc) + void DisAsm_F4_RC(const std::string& op, u32 f0, u32 f1, u32 f2, u32 f3, u32 rc) { Write(fmt::Format("%s%s f%d,f%d,f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), f0, f1, f2, f3)); } - void DisAsm_F3_RC(const std::string& op, u32 f0, u32 f1, u32 f2, bool rc) + void DisAsm_F3_RC(const std::string& op, u32 f0, u32 f1, u32 f2, u32 rc) { Write(fmt::Format("%s%s f%d,f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), f0, f1, f2)); } @@ -86,7 +86,7 @@ private: { DisAsm_F3_RC(op, f0, f1, f2, false); } - void DisAsm_F2_RC(const std::string& op, u32 f0, u32 f1, bool rc) + void DisAsm_F2_RC(const std::string& op, u32 f0, u32 f1, u32 rc) { Write(fmt::Format("%s%s f%d,f%d", FixOp(op).c_str(), (rc ? "." : ""), f0, f1)); } @@ -104,7 +104,7 @@ private: Write(fmt::Format("%s f%d,r%d(r%d)", FixOp(op).c_str(), f0, r0, r1)); } - void DisAsm_F1_IMM_R1_RC(const std::string& op, u32 f0, s32 imm0, u32 r0, bool rc) + void DisAsm_F1_IMM_R1_RC(const std::string& op, u32 f0, s32 imm0, u32 r0, u32 rc) { if(m_mode == CPUDisAsm_CompilerElfMode) { @@ -118,11 +118,11 @@ private: { DisAsm_F1_IMM_R1_RC(op, f0, imm0, r0, false); } - void DisAsm_F1_RC(const std::string& op, u32 f0, bool rc) + void DisAsm_F1_RC(const std::string& op, u32 f0, u32 rc) { Write(fmt::Format("%s%s f%d", FixOp(op).c_str(), (rc ? "." : ""), f0)); } - void DisAsm_R1_RC(const std::string& op, u32 r0, bool rc) + void DisAsm_R1_RC(const std::string& op, u32 r0, u32 rc) { Write(fmt::Format("%s%s r%d", FixOp(op).c_str(), (rc ? "." : ""), r0)); } @@ -130,11 +130,11 @@ private: { DisAsm_R1_RC(op, r0, false); } - void DisAsm_R2_OE_RC(const std::string& op, u32 r0, u32 r1, u32 oe, bool rc) + void DisAsm_R2_OE_RC(const std::string& op, u32 r0, u32 r1, u32 oe, u32 rc) { Write(fmt::Format("%s%s%s r%d,r%d", FixOp(op).c_str(), (oe ? "o" : ""), (rc ? "." : ""), r0, r1)); } - void DisAsm_R2_RC(const std::string& op, u32 r0, u32 r1, bool rc) + void DisAsm_R2_RC(const std::string& op, u32 r0, u32 r1, u32 rc) { DisAsm_R2_OE_RC(op, r0, r1, false, rc); } @@ -142,15 +142,15 @@ private: { DisAsm_R2_RC(op, r0, r1, false); } - void DisAsm_R3_OE_RC(const std::string& op, u32 r0, u32 r1, u32 r2, u32 oe, bool rc) + void DisAsm_R3_OE_RC(const std::string& op, u32 r0, u32 r1, u32 r2, u32 oe, u32 rc) { Write(fmt::Format("%s%s%s r%d,r%d,r%d", FixOp(op).c_str(), (oe ? "o" : ""), (rc ? "." : ""), r0, r1, r2)); } - void DisAsm_R3_INT2_RC(const std::string& op, u32 r0, u32 r1, u32 r2, s32 i0, s32 i1, bool rc) + void DisAsm_R3_INT2_RC(const std::string& op, u32 r0, u32 r1, u32 r2, s32 i0, s32 i1, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,r%d,%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, r2, i0, i1)); } - void DisAsm_R3_RC(const std::string& op, u32 r0, u32 r1, u32 r2, bool rc) + void DisAsm_R3_RC(const std::string& op, u32 r0, u32 r1, u32 r2, u32 rc) { DisAsm_R3_OE_RC(op, r0, r1, r2, false, rc); } @@ -158,7 +158,7 @@ private: { DisAsm_R3_RC(op, r0, r1, r2, false); } - void DisAsm_R2_INT3_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2, bool rc) + void DisAsm_R2_INT3_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,%d,%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, i0, i1, i2)); } @@ -166,7 +166,7 @@ private: { DisAsm_R2_INT3_RC(op, r0, r1, i0, i1, i2, false); } - void DisAsm_R2_INT2_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, bool rc) + void DisAsm_R2_INT2_RC(const std::string& op, u32 r0, u32 r1, s32 i0, s32 i1, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, i0, i1)); } @@ -174,7 +174,7 @@ private: { DisAsm_R2_INT2_RC(op, r0, r1, i0, i1, false); } - void DisAsm_R2_INT1_RC(const std::string& op, u32 r0, u32 r1, s32 i0, bool rc) + void DisAsm_R2_INT1_RC(const std::string& op, u32 r0, u32 r1, s32 i0, u32 rc) { Write(fmt::Format("%s%s r%d,r%d,%d", FixOp(op).c_str(), (rc ? "." : ""), r0, r1, i0)); } @@ -204,7 +204,7 @@ private: { Write(fmt::Format("%s cr%d,r%d,%d #%x", FixOp(op).c_str(), cr0, r0, imm0, imm0)); } - void DisAsm_CR1_R2_RC(const std::string& op, u32 cr0, u32 r0, u32 r1, bool rc) + void DisAsm_CR1_R2_RC(const std::string& op, u32 cr0, u32 r0, u32 r1, u32 rc) { Write(fmt::Format("%s%s cr%d,r%d,r%d", FixOp(op).c_str(), (rc ? "." : ""), cr0, r0, r1)); } @@ -1128,15 +1128,15 @@ private: case 1: DisAsm_INT3("bcctrl", bo, bi, bh); break; } } - void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) + void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { DisAsm_R2_INT3_RC("rlwimi", ra, rs, sh, mb, me, rc); } - void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) + void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { DisAsm_R2_INT3_RC("rlwinm", ra, rs, sh, mb, me, rc); } - void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) + void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, u32 rc) { DisAsm_R3_INT2_RC("rlwnm", ra, rs, rb, MB, ME, rc); } @@ -1174,7 +1174,7 @@ private: { DisAsm_R2_IMM("andis.", ra, rs, uimm16); } - void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { if(sh == 0) { @@ -1193,19 +1193,19 @@ private: DisAsm_R2_INT2_RC("rldicl", ra, rs, sh, mb, rc); } } - void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) + void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, u32 rc) { DisAsm_R2_INT2_RC("rldicr", ra, rs, sh, me, rc); } - void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { DisAsm_R2_INT2_RC("rldic", ra, rs, sh, mb, rc); } - void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { DisAsm_R2_INT2_RC("rldimi", ra, rs, sh, mb, rc); } - void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) + void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, u32 is_r, u32 rc) { if (is_r) DisAsm_R3_INT2_RC("rldcr", ra, rs, rb, m_eb, 0, rc); @@ -1228,19 +1228,19 @@ private: { DisAsm_V1_R2("lvebx", vd, ra, rb); } - void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("subfc", rd, ra, rb, oe, rc); } - void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("addc", rd, ra, rb, oe, rc); } - void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) + void MULHDU(u32 rd, u32 ra, u32 rb, u32 rc) { DisAsm_R3_RC("mulhdu", rd, ra, rb, rc); } - void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) + void MULHWU(u32 rd, u32 ra, u32 rb, u32 rc) { DisAsm_R3_RC("mulhwu", rd, ra, rb, rc); } @@ -1267,19 +1267,19 @@ private: { DisAsm_R3("lwzx", rd, ra, rb); } - void SLW(u32 ra, u32 rs, u32 rb, bool rc) + void SLW(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("slw", ra, rs, rb, rc); } - void CNTLZW(u32 ra, u32 rs, bool rc) + void CNTLZW(u32 ra, u32 rs, u32 rc) { DisAsm_R2_RC("cntlzw", ra, rs, rc); } - void SLD(u32 ra, u32 rs, u32 rb, bool rc) + void SLD(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("sld", ra, rs, rb, rc); } - void AND(u32 ra, u32 rs, u32 rb, bool rc) + void AND(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("and", ra, rs, rb, rc); } @@ -1295,7 +1295,7 @@ private: { DisAsm_V1_R2("lvehx", vd, ra, rb); } - void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("subf", rd, ra, rb, oe, rc); } @@ -1311,11 +1311,11 @@ private: { DisAsm_R3("lwzux", rd, ra, rb); } - void CNTLZD(u32 ra, u32 rs, bool rc) + void CNTLZD(u32 ra, u32 rs, u32 rc) { DisAsm_R2_RC("cntlzd", ra, rs, rc); } - void ANDC(u32 ra, u32 rs, u32 rb, bool rc) + void ANDC(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("andc", ra, rs, rb, rc); } @@ -1327,11 +1327,11 @@ private: { DisAsm_V1_R2("lvewx", vd, ra, rb); } - void MULHD(u32 rd, u32 ra, u32 rb, bool rc) + void MULHD(u32 rd, u32 ra, u32 rb, u32 rc) { DisAsm_R3_RC("mulhd", rd, ra, rb, rc); } - void MULHW(u32 rd, u32 ra, u32 rb, bool rc) + void MULHW(u32 rd, u32 ra, u32 rb, u32 rc) { DisAsm_R3_RC("mulhw", rd, ra, rb, rc); } @@ -1351,7 +1351,7 @@ private: { DisAsm_V1_R2("lvx", vd, ra, rb); } - void NEG(u32 rd, u32 ra, u32 oe, bool rc) + void NEG(u32 rd, u32 ra, u32 oe, u32 rc) { DisAsm_R2_OE_RC("neg", rd, ra, oe, rc); } @@ -1359,7 +1359,7 @@ private: { DisAsm_R3("lbzux", rd, ra, rb); } - void NOR(u32 ra, u32 rs, u32 rb, bool rc) + void NOR(u32 ra, u32 rs, u32 rb, u32 rc) { if(rs == rb) { @@ -1374,11 +1374,11 @@ private: { DisAsm_V1_R2("stvebx", vs, ra, rb); } - void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("subfe", rd, ra, rb, oe, rc); } - void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("adde", rd, ra, rb, oe, rc); } @@ -1421,11 +1421,11 @@ private: { DisAsm_V1_R2("stvewx", vs, ra, rb); } - void SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) + void SUBFZE(u32 rd, u32 ra, u32 oe, u32 rc) { DisAsm_R2_OE_RC("subfze", rd, ra, oe, rc); } - void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) + void ADDZE(u32 rd, u32 ra, u32 oe, u32 rc) { DisAsm_R2_OE_RC("addze", rd, ra, oe, rc); } @@ -1441,19 +1441,19 @@ private: { DisAsm_V1_R2("stvx", vd, ra, rb); } - void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) + void SUBFME(u32 rd, u32 ra, u32 oe, u32 rc) { DisAsm_R2_OE_RC("subfme", rd, ra, oe, rc); } - void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("mulld", rd, ra, rb, oe, rc); } - void ADDME(u32 rd, u32 ra, u32 oe, bool rc) + void ADDME(u32 rd, u32 ra, u32 oe, u32 rc) { DisAsm_R2_OE_RC("addme", rd, ra, oe, rc); } - void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("mullw", rd, ra, rb, oe, rc); } @@ -1465,7 +1465,7 @@ private: { DisAsm_R3("stbux", rs, ra, rb); } - void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void ADD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("add", rd, ra, rb, oe, rc); } @@ -1477,7 +1477,7 @@ private: { DisAsm_R3("lhzx", rd, ra, rb); } - void EQV(u32 ra, u32 rs, u32 rb, bool rc) + void EQV(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("eqv", ra, rs, rb, rc); } @@ -1489,7 +1489,7 @@ private: { DisAsm_R3("lhzux", rd, ra, rb); } - void XOR(u32 ra, u32 rs, u32 rb, bool rc) + void XOR(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("xor", ra, rs, rb, rc); } @@ -1560,7 +1560,7 @@ private: { DisAsm_R3("sthx", rs, ra, rb); } - void ORC(u32 ra, u32 rs, u32 rb, bool rc) + void ORC(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("orc", ra, rs, rb, rc); } @@ -1572,7 +1572,7 @@ private: { DisAsm_R3("sthux", rs, ra, rb); } - void OR(u32 ra, u32 rs, u32 rb, bool rc) + void OR(u32 ra, u32 rs, u32 rb, u32 rc) { if(rs==rb) { @@ -1583,11 +1583,11 @@ private: DisAsm_R3_RC("or", ra, rs, rb, rc); } } - void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("divdu", rd, ra, rb, oe, rc); } - void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("divwu", rd, ra, rb, oe, rc); } @@ -1607,7 +1607,7 @@ private: { DisAsm_R2("dcbi", ra, rb); } - void NAND(u32 ra, u32 rs, u32 rb, bool rc) + void NAND(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("nand", ra, rs, rb, rc); } @@ -1615,11 +1615,11 @@ private: { DisAsm_V1_R2("stvxl", vs, ra, rb); } - void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("divd", rd, ra, rb, oe, rc); } - void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { DisAsm_R3_OE_RC("divw", rd, ra, rb, oe, rc); } @@ -1643,11 +1643,11 @@ private: { DisAsm_F1_R2("lfsx", frd, ra, rb); } - void SRW(u32 ra, u32 rs, u32 rb, bool rc) + void SRW(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("srw", ra, rs, rb, rc); } - void SRD(u32 ra, u32 rs, u32 rb, bool rc) + void SRD(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("srd", ra, rs, rb, rc); } @@ -1723,11 +1723,11 @@ private: { DisAsm_R3("lhbrx", rd, ra, rb); } - void SRAW(u32 ra, u32 rs, u32 rb, bool rc) + void SRAW(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("sraw", ra, rs, rb, rc); } - void SRAD(u32 ra, u32 rs, u32 rb, bool rc) + void SRAD(u32 ra, u32 rs, u32 rb, u32 rc) { DisAsm_R3_RC("srad", ra, rs, rb, rc); } @@ -1746,15 +1746,15 @@ private: DisAsm_INT1("dss", strm); } } - void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) + void SRAWI(u32 ra, u32 rs, u32 sh, u32 rc) { DisAsm_R2_INT1_RC("srawi", ra, rs, sh, rc); } - void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) + void SRADI1(u32 ra, u32 rs, u32 sh, u32 rc) { DisAsm_R2_INT1_RC("sradi", ra, rs, sh, rc); } - void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) + void SRADI2(u32 ra, u32 rs, u32 sh, u32 rc) { DisAsm_R2_INT1_RC("sradi", ra, rs, sh, rc); } @@ -1770,7 +1770,7 @@ private: { DisAsm_R3("sthbrx", rs, ra, rb); } - void EXTSH(u32 ra, u32 rs, bool rc) + void EXTSH(u32 ra, u32 rs, u32 rc) { DisAsm_R2_RC("extsh", ra, rs, rc); } @@ -1778,7 +1778,7 @@ private: { DisAsm_V1_R2("stvrxl", sd, ra, rb); } - void EXTSB(u32 ra, u32 rs, bool rc) + void EXTSB(u32 ra, u32 rs, u32 rc) { DisAsm_R2_RC("extsb", ra, rs, rc); } @@ -1786,7 +1786,7 @@ private: { DisAsm_F1_R2("stfiwx", frs, ra, rb); } - void EXTSW(u32 ra, u32 rs, bool rc) + void EXTSW(u32 ra, u32 rs, u32 rc) { DisAsm_R2_RC("extsw", ra, rs, rc); } @@ -1906,43 +1906,43 @@ private: { DisAsm_R2_IMM("lwa", rd, ra, ds); } - void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) + void FDIVS(u32 frd, u32 fra, u32 frb, u32 rc) { DisAsm_F3_RC("fdivs", frd, fra, frb, rc); } - void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) + void FSUBS(u32 frd, u32 fra, u32 frb, u32 rc) { DisAsm_F3_RC("fsubs", frd, fra, frb, rc); } - void FADDS(u32 frd, u32 fra, u32 frb, bool rc) + void FADDS(u32 frd, u32 fra, u32 frb, u32 rc) { DisAsm_F3_RC("fadds", frd, fra, frb, rc); } - void FSQRTS(u32 frd, u32 frb, bool rc) + void FSQRTS(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fsqrts", frd, frb, rc); } - void FRES(u32 frd, u32 frb, bool rc) + void FRES(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fres", frd, frb, rc); } - void FMULS(u32 frd, u32 fra, u32 frc, bool rc) + void FMULS(u32 frd, u32 fra, u32 frc, u32 rc) { DisAsm_F3_RC("fmuls", frd, fra, frc, rc); } - void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fmadds", frd, fra, frc, frb, rc); } - void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fmsubs", frd, fra, frc, frb, rc); } - void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fnmsubs", frd, fra, frc, frb, rc); } - void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fnmadds", frd, fra, frc, frb, rc); } @@ -1954,7 +1954,7 @@ private: { DisAsm_R2_IMM("stdu", rs, ra, ds); } - void MTFSB1(u32 bt, bool rc) + void MTFSB1(u32 bt, u32 rc) { DisAsm_F1_RC("mtfsb1", bt, rc); } @@ -1962,19 +1962,19 @@ private: { DisAsm_F2("mcrfs", bf, bfa); } - void MTFSB0(u32 bt, bool rc) + void MTFSB0(u32 bt, u32 rc) { DisAsm_F1_RC("mtfsb0", bt, rc); } - void MTFSFI(u32 crfd, u32 i, bool rc) + void MTFSFI(u32 crfd, u32 i, u32 rc) { DisAsm_F2_RC("mtfsfi", crfd, i, rc); } - void MFFS(u32 frd, bool rc) + void MFFS(u32 frd, u32 rc) { DisAsm_F1_RC("mffs", frd, rc); } - void MTFSF(u32 flm, u32 frb, bool rc) + void MTFSF(u32 flm, u32 frb, u32 rc) { DisAsm_F2_RC("mtfsf", flm, frb, rc); } @@ -1982,59 +1982,59 @@ private: { DisAsm_CR1_F2("fcmpu", crfd, fra, frb); } - void FRSP(u32 frd, u32 frb, bool rc) + void FRSP(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("frsp", frd, frb, rc); } - void FCTIW(u32 frd, u32 frb, bool rc) + void FCTIW(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fctiw", frd, frb, rc); } - void FCTIWZ(u32 frd, u32 frb, bool rc) + void FCTIWZ(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fctiwz", frd, frb, rc); } - void FDIV(u32 frd, u32 fra, u32 frb, bool rc) + void FDIV(u32 frd, u32 fra, u32 frb, u32 rc) { DisAsm_F3_RC("fdiv", frd, fra, frb, rc); } - void FSUB(u32 frd, u32 fra, u32 frb, bool rc) + void FSUB(u32 frd, u32 fra, u32 frb, u32 rc) { DisAsm_F3_RC("fsub", frd, fra, frb, rc); } - void FADD(u32 frd, u32 fra, u32 frb, bool rc) + void FADD(u32 frd, u32 fra, u32 frb, u32 rc) { DisAsm_F3_RC("fadd", frd, fra, frb, rc); } - void FSQRT(u32 frd, u32 frb, bool rc) + void FSQRT(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fsqrt", frd, frb, rc); } - void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fsel", frd, fra, frc, frb, rc); } - void FMUL(u32 frd, u32 fra, u32 frc, bool rc) + void FMUL(u32 frd, u32 fra, u32 frc, u32 rc) { DisAsm_F3_RC("fmul", frd, fra, frc, rc); } - void FRSQRTE(u32 frd, u32 frb, bool rc) + void FRSQRTE(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("frsqrte", frd, frb, rc); } - void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fmsub", frd, fra, frc, frb, rc); } - void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fmadd", frd, fra, frc, frb, rc); } - void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fnmsub", frd, fra, frc, frb, rc); } - void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { DisAsm_F4_RC("fnmadd", frd, fra, frc, frb, rc); } @@ -2042,31 +2042,31 @@ private: { DisAsm_F3("fcmpo", crfd, fra, frb); } - void FNEG(u32 frd, u32 frb, bool rc) + void FNEG(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fneg", frd, frb, rc); } - void FMR(u32 frd, u32 frb, bool rc) + void FMR(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fmr", frd, frb, rc); } - void FNABS(u32 frd, u32 frb, bool rc) + void FNABS(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fnabs", frd, frb, rc); } - void FABS(u32 frd, u32 frb, bool rc) + void FABS(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fabs", frd, frb, rc); } - void FCTID(u32 frd, u32 frb, bool rc) + void FCTID(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fctid", frd, frb, rc); } - void FCTIDZ(u32 frd, u32 frb, bool rc) + void FCTIDZ(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fctidz", frd, frb, rc); } - void FCFID(u32 frd, u32 frb, bool rc) + void FCFID(u32 frd, u32 frb, u32 rc) { DisAsm_F2_RC("fcfid", frd, frb, rc); } diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h index bc3a0e2c5a..7d66093e90 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter.h +++ b/rpcs3/Emu/Cell/PPUInterpreter.h @@ -466,7 +466,7 @@ private: CPU.VPR[vd]._f[w] = ((float)CPU.VPR[vb]._u32[w]) / scale; } } - void VCMPBFP(u32 vd, u32 va, u32 vb, bool rc) + void VCMPBFP(u32 vd, u32 va, u32 vb, u32 rc) { bool allInBounds = true; @@ -495,7 +495,7 @@ private: } void VCMPBFP(u32 vd, u32 va, u32 vb) {VCMPBFP(vd, va, vb, false);} void VCMPBFP_(u32 vd, u32 va, u32 vb) {VCMPBFP(vd, va, vb, true);} - void VCMPEQFP(u32 vd, u32 va, u32 vb, bool rc) + void VCMPEQFP(u32 vd, u32 va, u32 vb, u32 rc) { int all_equal = 0x8; int none_equal = 0x2; @@ -518,7 +518,7 @@ private: } void VCMPEQFP(u32 vd, u32 va, u32 vb) {VCMPEQFP(vd, va, vb, false);} void VCMPEQFP_(u32 vd, u32 va, u32 vb) {VCMPEQFP(vd, va, vb, true);} - void VCMPEQUB(u32 vd, u32 va, u32 vb, bool rc) + void VCMPEQUB(u32 vd, u32 va, u32 vb, u32 rc) { int all_equal = 0x8; int none_equal = 0x2; @@ -541,7 +541,7 @@ private: } void VCMPEQUB(u32 vd, u32 va, u32 vb) {VCMPEQUB(vd, va, vb, false);} void VCMPEQUB_(u32 vd, u32 va, u32 vb) {VCMPEQUB(vd, va, vb, true);} - void VCMPEQUH(u32 vd, u32 va, u32 vb, bool rc) //nf + void VCMPEQUH(u32 vd, u32 va, u32 vb, u32 rc) //nf { int all_equal = 0x8; int none_equal = 0x2; @@ -564,7 +564,7 @@ private: } void VCMPEQUH(u32 vd, u32 va, u32 vb) {VCMPEQUH(vd, va, vb, false);} void VCMPEQUH_(u32 vd, u32 va, u32 vb) {VCMPEQUH(vd, va, vb, true);} - void VCMPEQUW(u32 vd, u32 va, u32 vb, bool rc) + void VCMPEQUW(u32 vd, u32 va, u32 vb, u32 rc) { int all_equal = 0x8; int none_equal = 0x2; @@ -587,7 +587,7 @@ private: } void VCMPEQUW(u32 vd, u32 va, u32 vb) {VCMPEQUW(vd, va, vb, false);} void VCMPEQUW_(u32 vd, u32 va, u32 vb) {VCMPEQUW(vd, va, vb, true);} - void VCMPGEFP(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGEFP(u32 vd, u32 va, u32 vb, u32 rc) { int all_ge = 0x8; int none_ge = 0x2; @@ -610,7 +610,7 @@ private: } void VCMPGEFP(u32 vd, u32 va, u32 vb) {VCMPGEFP(vd, va, vb, false);} void VCMPGEFP_(u32 vd, u32 va, u32 vb) {VCMPGEFP(vd, va, vb, true);} - void VCMPGTFP(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGTFP(u32 vd, u32 va, u32 vb, u32 rc) { int all_ge = 0x8; int none_ge = 0x2; @@ -633,7 +633,7 @@ private: } void VCMPGTFP(u32 vd, u32 va, u32 vb) {VCMPGTFP(vd, va, vb, false);} void VCMPGTFP_(u32 vd, u32 va, u32 vb) {VCMPGTFP(vd, va, vb, true);} - void VCMPGTSB(u32 vd, u32 va, u32 vb, bool rc) //nf + void VCMPGTSB(u32 vd, u32 va, u32 vb, u32 rc) //nf { int all_gt = 0x8; int none_gt = 0x2; @@ -656,7 +656,7 @@ private: } void VCMPGTSB(u32 vd, u32 va, u32 vb) {VCMPGTSB(vd, va, vb, false);} void VCMPGTSB_(u32 vd, u32 va, u32 vb) {VCMPGTSB(vd, va, vb, true);} - void VCMPGTSH(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGTSH(u32 vd, u32 va, u32 vb, u32 rc) { int all_gt = 0x8; int none_gt = 0x2; @@ -679,7 +679,7 @@ private: } void VCMPGTSH(u32 vd, u32 va, u32 vb) {VCMPGTSH(vd, va, vb, false);} void VCMPGTSH_(u32 vd, u32 va, u32 vb) {VCMPGTSH(vd, va, vb, true);} - void VCMPGTSW(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGTSW(u32 vd, u32 va, u32 vb, u32 rc) { int all_gt = 0x8; int none_gt = 0x2; @@ -702,7 +702,7 @@ private: } void VCMPGTSW(u32 vd, u32 va, u32 vb) {VCMPGTSW(vd, va, vb, false);} void VCMPGTSW_(u32 vd, u32 va, u32 vb) {VCMPGTSW(vd, va, vb, true);} - void VCMPGTUB(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGTUB(u32 vd, u32 va, u32 vb, u32 rc) { int all_gt = 0x8; int none_gt = 0x2; @@ -725,7 +725,7 @@ private: } void VCMPGTUB(u32 vd, u32 va, u32 vb) {VCMPGTUB(vd, va, vb, false);} void VCMPGTUB_(u32 vd, u32 va, u32 vb) {VCMPGTUB(vd, va, vb, true);} - void VCMPGTUH(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGTUH(u32 vd, u32 va, u32 vb, u32 rc) { int all_gt = 0x8; int none_gt = 0x2; @@ -748,7 +748,7 @@ private: } void VCMPGTUH(u32 vd, u32 va, u32 vb) {VCMPGTUH(vd, va, vb, false);} void VCMPGTUH_(u32 vd, u32 va, u32 vb) {VCMPGTUH(vd, va, vb, true);} - void VCMPGTUW(u32 vd, u32 va, u32 vb, bool rc) + void VCMPGTUW(u32 vd, u32 va, u32 vb, u32 rc) { int all_gt = 0x8; int none_gt = 0x2; @@ -2316,18 +2316,18 @@ private: if(lk) CPU.LR = nextLR; } } - void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) + void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { const u64 mask = rotate_mask[32 + mb][32 + me]; CPU.GPR[ra] = (CPU.GPR[ra] & ~mask) | (rotl32(CPU.GPR[rs], sh) & mask); if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) + void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { CPU.GPR[ra] = rotl32(CPU.GPR[rs], sh) & rotate_mask[32 + mb][32 + me]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLWNM(u32 ra, u32 rs, u32 rb, u32 mb, u32 me, bool rc) + void RLWNM(u32 ra, u32 rs, u32 rb, u32 mb, u32 me, u32 rc) { CPU.GPR[ra] = rotl32(CPU.GPR[rs], CPU.GPR[rb] & 0x1f) & rotate_mask[32 + mb][32 + me]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2358,28 +2358,28 @@ private: CPU.GPR[ra] = CPU.GPR[rs] & ((u64)uimm16 << 16); CPU.UpdateCR0(CPU.GPR[ra]); } - void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[mb][63]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) + void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, u32 rc) { CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[0][me]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[mb][63-sh]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { const u64 mask = rotate_mask[mb][63-sh]; CPU.GPR[ra] = (CPU.GPR[ra] & ~mask) | (rotl64(CPU.GPR[rs], sh) & mask); if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) + void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, u32 is_r, u32 rc) { if (is_r) // rldcr { @@ -2441,7 +2441,7 @@ private: CPU.VPR[vd]._u8[15 - (addr & 0xf)] = vm::read8(VM_CAST(addr)); // check LVEWX comments } - void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2450,12 +2450,12 @@ private: if(oe) CPU.SetOV((~RA>>63 == RB>>63) && (~RA>>63 != CPU.GPR[rd]>>63)); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) + void MULHDU(u32 rd, u32 ra, u32 rb, u32 rc) { CPU.GPR[rd] = __umulh(CPU.GPR[ra], CPU.GPR[rb]); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2464,7 +2464,7 @@ private: if(oe) CPU.SetOV((RA>>63 == RB>>63) && (RA>>63 != CPU.GPR[rd]>>63)); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) + void MULHWU(u32 rd, u32 ra, u32 rb, u32 rc) { u32 a = (u32)CPU.GPR[ra]; u32 b = (u32)CPU.GPR[rb]; @@ -2494,7 +2494,7 @@ private: const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; CPU.GPR[rd] = vm::read32(VM_CAST(addr)); } - void SLW(u32 ra, u32 rs, u32 rb, bool rc) + void SLW(u32 ra, u32 rs, u32 rb, u32 rc) { u32 n = CPU.GPR[rb] & 0x1f; u32 r = (u32)rotl32((u32)CPU.GPR[rs], n); @@ -2504,7 +2504,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void CNTLZW(u32 ra, u32 rs, bool rc) + void CNTLZW(u32 ra, u32 rs, u32 rc) { u32 i; for(i=0; i < 32; i++) @@ -2515,7 +2515,7 @@ private: CPU.GPR[ra] = i; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void SLD(u32 ra, u32 rs, u32 rb, bool rc) + void SLD(u32 ra, u32 rs, u32 rb, u32 rc) { u32 n = CPU.GPR[rb] & 0x3f; u64 r = rotl64(CPU.GPR[rs], n); @@ -2525,7 +2525,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void AND(u32 ra, u32 rs, u32 rb, bool rc) + void AND(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = CPU.GPR[rs] & CPU.GPR[rb]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2567,7 +2567,7 @@ private: CPU.VPR[vd]._u16[7 - ((addr >> 1) & 0x7)] = vm::read16(VM_CAST(addr)); // check LVEWX comments } - void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2590,7 +2590,7 @@ private: CPU.GPR[rd] = vm::read32(VM_CAST(addr)); CPU.GPR[ra] = addr; } - void CNTLZD(u32 ra, u32 rs, bool rc) + void CNTLZD(u32 ra, u32 rs, u32 rc) { u32 i; for(i=0; i < 64; i++) @@ -2601,7 +2601,7 @@ private: CPU.GPR[ra] = i; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void ANDC(u32 ra, u32 rs, u32 rb, bool rc) + void ANDC(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2618,12 +2618,12 @@ private: // because it can theoretically read RawSPU 32-bit MMIO register (read128() will fail) //CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); } - void MULHD(u32 rd, u32 ra, u32 rb, bool rc) + void MULHD(u32 rd, u32 ra, u32 rb, u32 rc) { CPU.GPR[rd] = __mulh(CPU.GPR[ra], CPU.GPR[rb]); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void MULHW(u32 rd, u32 ra, u32 rb, bool rc) + void MULHW(u32 rd, u32 ra, u32 rb, u32 rc) { s32 a = (s32)CPU.GPR[ra]; s32 b = (s32)CPU.GPR[rb]; @@ -2652,7 +2652,7 @@ private: const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfull; CPU.VPR[vd] = vm::read128(VM_CAST(addr)); } - void NEG(u32 rd, u32 ra, u32 oe, bool rc) + void NEG(u32 rd, u32 ra, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = 0 - RA; @@ -2665,7 +2665,7 @@ private: CPU.GPR[rd] = vm::read8(VM_CAST(addr)); CPU.GPR[ra] = addr; } - void NOR(u32 ra, u32 rs, u32 rb, bool rc) + void NOR(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = ~(CPU.GPR[rs] | CPU.GPR[rb]); if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2676,7 +2676,7 @@ private: const u8 eb = addr & 0xf; vm::write8(VM_CAST(addr), CPU.VPR[vs]._u8[15 - eb]); } - void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2685,7 +2685,7 @@ private: if(oe) CPU.SetOV((~RA>>63 == RB>>63) && (~RA>>63 != CPU.GPR[rd]>>63)); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2784,7 +2784,7 @@ private: const u8 eb = (addr & 0xf) >> 2; vm::write32(VM_CAST(addr), CPU.VPR[vs]._u32[3 - eb]); } - void SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) + void SUBFZE(u32 rd, u32 ra, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = ~RA + CPU.XER.CA; @@ -2792,7 +2792,7 @@ private: if(oe) CPU.SetOV((~RA>>63 == 0) && (~RA>>63 != CPU.GPR[rd]>>63)); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) + void ADDZE(u32 rd, u32 ra, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = RA + CPU.XER.CA; @@ -2817,7 +2817,7 @@ private: const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfull; vm::write128(VM_CAST(addr), CPU.VPR[vs]); } - void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const s64 RA = CPU.GPR[ra]; const s64 RB = CPU.GPR[rb]; @@ -2829,7 +2829,7 @@ private: } if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) + void SUBFME(u32 rd, u32 ra, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = ~RA + CPU.XER.CA + ~0ULL; @@ -2837,7 +2837,7 @@ private: if(oe) CPU.SetOV((~RA>>63 == 1) && (~RA>>63 != CPU.GPR[rd]>>63)); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void ADDME(u32 rd, u32 ra, u32 oe, bool rc) + void ADDME(u32 rd, u32 ra, u32 oe, u32 rc) { const s64 RA = CPU.GPR[ra]; CPU.GPR[rd] = RA + CPU.XER.CA - 1; @@ -2846,7 +2846,7 @@ private: if(oe) CPU.SetOV((u64(RA)>>63 == 1) && (u64(RA)>>63 != CPU.GPR[rd]>>63)); if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { CPU.GPR[rd] = (s64)((s64)(s32)CPU.GPR[ra] * (s64)(s32)CPU.GPR[rb]); if(oe) CPU.SetOV(s64(CPU.GPR[rd]) < s64(-1)<<31 || s64(CPU.GPR[rd]) >= s64(1)<<31); @@ -2861,7 +2861,7 @@ private: vm::write8(VM_CAST(addr), (u8)CPU.GPR[rs]); CPU.GPR[ra] = addr; } - void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void ADD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2877,7 +2877,7 @@ private: const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; CPU.GPR[rd] = vm::read16(VM_CAST(addr)); } - void EQV(u32 ra, u32 rs, u32 rb, bool rc) + void EQV(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = ~(CPU.GPR[rs] ^ CPU.GPR[rb]); if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2892,7 +2892,7 @@ private: CPU.GPR[rd] = vm::read16(VM_CAST(addr)); CPU.GPR[ra] = addr; } - void XOR(u32 ra, u32 rs, u32 rb, bool rc) + void XOR(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = CPU.GPR[rs] ^ CPU.GPR[rb]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2951,7 +2951,7 @@ private: const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; vm::write16(VM_CAST(addr), (u16)CPU.GPR[rs]); } - void ORC(u32 ra, u32 rs, u32 rb, bool rc) + void ORC(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = CPU.GPR[rs] | ~CPU.GPR[rb]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -2966,12 +2966,12 @@ private: vm::write16(VM_CAST(addr), (u16)CPU.GPR[rs]); CPU.GPR[ra] = addr; } - void OR(u32 ra, u32 rs, u32 rb, bool rc) + void OR(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = CPU.GPR[rs] | CPU.GPR[rb]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u64 RA = CPU.GPR[ra]; const u64 RB = CPU.GPR[rb]; @@ -2989,7 +2989,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const u32 RA = (u32)CPU.GPR[ra]; const u32 RB = (u32)CPU.GPR[rb]; @@ -3014,7 +3014,7 @@ private: void DCBI(u32 ra, u32 rb) { } - void NAND(u32 ra, u32 rs, u32 rb, bool rc) + void NAND(u32 ra, u32 rs, u32 rb, u32 rc) { CPU.GPR[ra] = ~(CPU.GPR[rs] & CPU.GPR[rb]); @@ -3025,7 +3025,7 @@ private: const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfull; vm::write128(VM_CAST(addr), CPU.VPR[vs]); } - void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const s64 RA = CPU.GPR[ra]; const s64 RB = CPU.GPR[rb]; @@ -3043,7 +3043,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[rd]); } - void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { const s32 RA = (s32)CPU.GPR[ra]; const s32 RB = (s32)CPU.GPR[rb]; @@ -3112,7 +3112,7 @@ private: (u64&)CPU.FPR[frd] = (bits & 0x80000000) << 32 | 7ULL << 60 | (bits & 0x7fffffff) << 29; } } - void SRW(u32 ra, u32 rs, u32 rb, bool rc) + void SRW(u32 ra, u32 rs, u32 rb, u32 rc) { u32 n = CPU.GPR[rb] & 0x1f; u32 r = (u32)rotl32((u32)CPU.GPR[rs], 64 - n); @@ -3121,7 +3121,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void SRD(u32 ra, u32 rs, u32 rb, bool rc) + void SRD(u32 ra, u32 rs, u32 rb, u32 rc) { u32 n = CPU.GPR[rb] & 0x3f; u64 r = rotl64(CPU.GPR[rs], 64 - n); @@ -3323,7 +3323,7 @@ private: const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; CPU.GPR[rd] = vm::get_ref(VM_CAST(addr)); } - void SRAW(u32 ra, u32 rs, u32 rb, bool rc) + void SRAW(u32 ra, u32 rs, u32 rb, u32 rc) { s32 RS = (s32)CPU.GPR[rs]; u8 shift = CPU.GPR[rb] & 63; @@ -3340,7 +3340,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void SRAD(u32 ra, u32 rs, u32 rb, bool rc) + void SRAD(u32 ra, u32 rs, u32 rb, u32 rc) { s64 RS = CPU.GPR[rs]; u8 shift = CPU.GPR[rb] & 127; @@ -3368,7 +3368,7 @@ private: void DSS(u32 strm, u32 a) { } - void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) + void SRAWI(u32 ra, u32 rs, u32 sh, u32 rc) { s32 RS = (u32)CPU.GPR[rs]; CPU.GPR[ra] = RS >> sh; @@ -3376,7 +3376,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) + void SRADI1(u32 ra, u32 rs, u32 sh, u32 rc) { s64 RS = CPU.GPR[rs]; CPU.GPR[ra] = RS >> sh; @@ -3384,7 +3384,7 @@ private: if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) + void SRADI2(u32 ra, u32 rs, u32 sh, u32 rc) { SRADI1(ra, rs, sh, rc); } @@ -3404,7 +3404,7 @@ private: const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; vm::get_ref(VM_CAST(addr)) = (u16)CPU.GPR[rs]; } - void EXTSH(u32 ra, u32 rs, bool rc) + void EXTSH(u32 ra, u32 rs, u32 rc) { CPU.GPR[ra] = (s64)(s16)CPU.GPR[rs]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -3416,7 +3416,7 @@ private: for (u32 i = 16 - eb; i < 16; ++i) vm::write8(VM_CAST(addr + i - 16), CPU.VPR[vs]._u8[15 - i]); } - void EXTSB(u32 ra, u32 rs, bool rc) + void EXTSB(u32 ra, u32 rs, u32 rc) { CPU.GPR[ra] = (s64)(s8)CPU.GPR[rs]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -3426,7 +3426,7 @@ private: const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; vm::write32(VM_CAST(addr), (u32&)CPU.FPR[frs]); } - void EXTSW(u32 ra, u32 rs, bool rc) + void EXTSW(u32 ra, u32 rs, u32 rc) { CPU.GPR[ra] = (s64)(s32)CPU.GPR[rs]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); @@ -3632,11 +3632,11 @@ private: const u64 addr = ra ? CPU.GPR[ra] + ds : ds; CPU.GPR[rd] = (s64)(s32)vm::read32(VM_CAST(addr)); } - void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) {FDIV(frd, fra, frb, rc, true);} - void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) {FSUB(frd, fra, frb, rc, true);} - void FADDS(u32 frd, u32 fra, u32 frb, bool rc) {FADD(frd, fra, frb, rc, true);} - void FSQRTS(u32 frd, u32 frb, bool rc) {FSQRT(frd, frb, rc, true);} - void FRES(u32 frd, u32 frb, bool rc) + void FDIVS(u32 frd, u32 fra, u32 frb, u32 rc) {FDIV(frd, fra, frb, rc, true);} + void FSUBS(u32 frd, u32 fra, u32 frb, u32 rc) {FSUB(frd, fra, frb, rc, true);} + void FADDS(u32 frd, u32 fra, u32 frb, u32 rc) {FADD(frd, fra, frb, rc, true);} + void FSQRTS(u32 frd, u32 frb, u32 rc) {FSQRT(frd, frb, rc, true);} + void FRES(u32 frd, u32 frb, u32 rc) { SetHostRoundingMode(CPU.FPSCR.RN); const double b = CPU.FPR[frb]; @@ -3676,11 +3676,11 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FMULS(u32 frd, u32 fra, u32 frc, bool rc) {FMUL(frd, fra, frc, rc, true);} - void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, false, false, true);} - void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, false, true, true);} - void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, true, true, true);} - void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, true, false, true);} + void FMULS(u32 frd, u32 fra, u32 frc, u32 rc) {FMUL(frd, fra, frc, rc, true);} + void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, false, false, true);} + void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, false, true, true);} + void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, true, true, true);} + void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, true, false, true);} void STD(u32 rs, u32 ra, s32 d) { const u64 addr = ra ? CPU.GPR[ra] + d : d; @@ -3692,7 +3692,7 @@ private: vm::write64(VM_CAST(addr), CPU.GPR[rs]); CPU.GPR[ra] = addr; } - void MTFSB1(u32 crbd, bool rc) + void MTFSB1(u32 crbd, u32 rc) { u32 mask = 1 << (31 - crbd); if ((crbd >= 3 && crbd <= 6) && !(CPU.FPSCR.FPSCR & mask)) mask |= 1 << 31; //FPSCR.FX @@ -3707,7 +3707,7 @@ private: const u32 exceptions_mask = 0x9FF80700; CPU.SetFPSCR(CPU.FPSCR.FPSCR & ~(exceptions_mask & 0xf << ((7 - crbs) * 4))); } - void MTFSB0(u32 crbd, bool rc) + void MTFSB0(u32 crbd, u32 rc) { u32 mask = 1 << (31 - crbd); if ((crbd == 29) && !CPU.FPSCR.NI) LOG_WARNING(PPU, "Non-IEEE mode disabled"); @@ -3715,7 +3715,7 @@ private: if(rc) CPU.UpdateCR1(); } - void MTFSFI(u32 crfd, u32 i, bool rc) + void MTFSFI(u32 crfd, u32 i, u32 rc) { u32 mask = 0xF0000000 >> (crfd * 4); u32 val = (i & 0xF) << ((7 - crfd) * 4); @@ -3732,12 +3732,12 @@ private: if(rc) CPU.UpdateCR1(); } - void MFFS(u32 frd, bool rc) + void MFFS(u32 frd, u32 rc) { (u64&)CPU.FPR[frd] = CPU.FPSCR.FPSCR; if(rc) CPU.UpdateCR1(); } - void MTFSF(u32 flm, u32 frb, bool rc) + void MTFSF(u32 flm, u32 frb, u32 rc) { u32 mask = 0; for(u32 i=0; i<8; ++i) @@ -3772,7 +3772,7 @@ private: CPU.FPSCR.FPRF = cmp_res; CPU.SetCR(crfd, cmp_res); } - void FRSP(u32 frd, u32 frb, bool rc) + void FRSP(u32 frd, u32 frb, u32 rc) { SetHostRoundingMode(CPU.FPSCR.RN); const double b = CPU.FPR[frb]; @@ -3811,8 +3811,8 @@ private: CPU.FPR[frd] = r; if(rc) CPU.UpdateCR1(); } - void FCTIW(u32 frd, u32 frb, bool rc) {FCTIW(frd, frb, rc, false);} - void FCTIW(u32 frd, u32 frb, bool rc, bool truncate) + void FCTIW(u32 frd, u32 frb, u32 rc) {FCTIW(frd, frb, rc, false);} + void FCTIW(u32 frd, u32 frb, u32 rc, bool truncate) { const double b = CPU.FPR[frb]; u32 r; @@ -3878,9 +3878,9 @@ private: (u64&)CPU.FPR[frd] = r; if(rc) CPU.UpdateCR1(); } - void FCTIWZ(u32 frd, u32 frb, bool rc) {FCTIW(frd, frb, rc, true);} - void FDIV(u32 frd, u32 fra, u32 frb, bool rc) {FDIV(frd, fra, frb, rc, false);} - void FDIV(u32 frd, u32 fra, u32 frb, bool rc, bool single) + void FCTIWZ(u32 frd, u32 frb, u32 rc) {FCTIW(frd, frb, rc, true);} + void FDIV(u32 frd, u32 fra, u32 frb, u32 rc) {FDIV(frd, fra, frb, rc, false);} + void FDIV(u32 frd, u32 fra, u32 frb, u32 rc, bool single) { SetHostRoundingMode(CPU.FPSCR.RN); const double a = CPU.FPR[fra]; @@ -3951,8 +3951,8 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FSUB(u32 frd, u32 fra, u32 frb, bool rc) {FSUB(frd, fra, frb, rc, false);} - void FSUB(u32 frd, u32 fra, u32 frb, bool rc, bool single) + void FSUB(u32 frd, u32 fra, u32 frb, u32 rc) {FSUB(frd, fra, frb, rc, false);} + void FSUB(u32 frd, u32 fra, u32 frb, u32 rc, bool single) { SetHostRoundingMode(CPU.FPSCR.RN); const double a = CPU.FPR[fra]; @@ -3999,8 +3999,8 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FADD(u32 frd, u32 fra, u32 frb, bool rc) {FADD(frd, fra, frb, rc, false);} - void FADD(u32 frd, u32 fra, u32 frb, bool rc, bool single) + void FADD(u32 frd, u32 fra, u32 frb, u32 rc) {FADD(frd, fra, frb, rc, false);} + void FADD(u32 frd, u32 fra, u32 frb, u32 rc, bool single) { SetHostRoundingMode(CPU.FPSCR.RN); const double a = CPU.FPR[fra]; @@ -4047,8 +4047,8 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FSQRT(u32 frd, u32 frb, bool rc) {FSQRT(frd, frb, rc, false);} - void FSQRT(u32 frd, u32 frb, bool rc, bool single) + void FSQRT(u32 frd, u32 frb, u32 rc) {FSQRT(frd, frb, rc, false);} + void FSQRT(u32 frd, u32 frb, u32 rc, bool single) { SetHostRoundingMode(CPU.FPSCR.RN); const double b = CPU.FPR[frb]; @@ -4090,13 +4090,13 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { CPU.FPR[frd] = CPU.FPR[fra] >= 0.0 ? CPU.FPR[frc] : CPU.FPR[frb]; if(rc) CPU.UpdateCR1(); } - void FMUL(u32 frd, u32 fra, u32 frc, bool rc) {FMUL(frd, fra, frc, rc, false);} - void FMUL(u32 frd, u32 fra, u32 frc, bool rc, bool single) + void FMUL(u32 frd, u32 fra, u32 frc, u32 rc) {FMUL(frd, fra, frc, rc, false);} + void FMUL(u32 frd, u32 fra, u32 frc, u32 rc, bool single) { SetHostRoundingMode(CPU.FPSCR.RN); const double a = CPU.FPR[fra]; @@ -4143,7 +4143,7 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FRSQRTE(u32 frd, u32 frb, bool rc) + void FRSQRTE(u32 frd, u32 frb, u32 rc) { SetHostRoundingMode(CPU.FPSCR.RN); const double b = CPU.FPR[frb]; @@ -4195,9 +4195,9 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, false, true, false);} - void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, false, false, false);} - void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc, bool neg, bool sub, bool single) + void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, false, true, false);} + void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, false, false, false);} + void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc, bool neg, bool sub, bool single) { SetHostRoundingMode(CPU.FPSCR.RN); const double a = CPU.FPR[fra]; @@ -4264,8 +4264,8 @@ private: CPU.FPSCR.FPRF = CPU.FPR[frd].GetType(); if(rc) CPU.UpdateCR1(); } - void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, true, true, false);} - void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, true, false, false);} + void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, true, true, false);} + void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) {FMADD(frd, fra, frc, frb, rc, true, false, false);} void FCMPO(u32 crfd, u32 fra, u32 frb) { int cmp_res = FPRdouble::Cmp(CPU.FPR[fra], CPU.FPR[frb]); @@ -4288,28 +4288,28 @@ private: CPU.FPSCR.FPRF = cmp_res; CPU.SetCR(crfd, cmp_res); } - void FNEG(u32 frd, u32 frb, bool rc) + void FNEG(u32 frd, u32 frb, u32 rc) { CPU.FPR[frd] = -CPU.FPR[frb]; if(rc) CPU.UpdateCR1(); } - void FMR(u32 frd, u32 frb, bool rc) + void FMR(u32 frd, u32 frb, u32 rc) { CPU.FPR[frd] = CPU.FPR[frb]; if(rc) CPU.UpdateCR1(); } - void FNABS(u32 frd, u32 frb, bool rc) + void FNABS(u32 frd, u32 frb, u32 rc) { CPU.FPR[frd] = -fabs(CPU.FPR[frb]); if(rc) CPU.UpdateCR1(); } - void FABS(u32 frd, u32 frb, bool rc) + void FABS(u32 frd, u32 frb, u32 rc) { CPU.FPR[frd] = fabs(CPU.FPR[frb]); if(rc) CPU.UpdateCR1(); } - void FCTID(u32 frd, u32 frb, bool rc) {FCTID(frd, frb, rc, false);} - void FCTID(u32 frd, u32 frb, bool rc, bool truncate) + void FCTID(u32 frd, u32 frb, u32 rc) {FCTID(frd, frb, rc, false);} + void FCTID(u32 frd, u32 frb, u32 rc, bool truncate) { const double b = CPU.FPR[frb]; u64 r; @@ -4375,8 +4375,8 @@ private: (u64&)CPU.FPR[frd] = r; if(rc) CPU.UpdateCR1(); } - void FCTIDZ(u32 frd, u32 frb, bool rc) {FCTID(frd, frb, rc, true);} - void FCFID(u32 frd, u32 frb, bool rc) + void FCTIDZ(u32 frd, u32 frb, u32 rc) {FCTID(frd, frb, rc, true);} + void FCFID(u32 frd, u32 frb, u32 rc) { s64 bi = (s64&)CPU.FPR[frb]; double bf = (double)bi; diff --git a/rpcs3/Emu/Cell/PPUInterpreter2.h b/rpcs3/Emu/Cell/PPUInterpreter2.h index 9ad6989714..0bed8052ef 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter2.h +++ b/rpcs3/Emu/Cell/PPUInterpreter2.h @@ -736,59 +736,59 @@ public: virtual void CRORC(u32 bt, u32 ba, u32 bb) { func = ppu_interpreter::CRORC; } virtual void CROR(u32 bt, u32 ba, u32 bb) { func = ppu_interpreter::CROR; } virtual void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) { func = ppu_interpreter::BCCTR; } - virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { func = ppu_interpreter::RLWIMI; } - virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { func = ppu_interpreter::RLWINM; } - virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) { func = ppu_interpreter::RLWNM; } + virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { func = ppu_interpreter::RLWIMI; } + virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { func = ppu_interpreter::RLWINM; } + virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, u32 rc) { func = ppu_interpreter::RLWNM; } virtual void ORI(u32 rs, u32 ra, u32 uimm16) { func = ppu_interpreter::ORI; } virtual void ORIS(u32 rs, u32 ra, u32 uimm16) { func = ppu_interpreter::ORIS; } virtual void XORI(u32 ra, u32 rs, u32 uimm16) { func = ppu_interpreter::XORI; } virtual void XORIS(u32 ra, u32 rs, u32 uimm16) { func = ppu_interpreter::XORIS; } virtual void ANDI_(u32 ra, u32 rs, u32 uimm16) { func = ppu_interpreter::ANDI_; } virtual void ANDIS_(u32 ra, u32 rs, u32 uimm16) { func = ppu_interpreter::ANDIS_; } - virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { func = ppu_interpreter::RLDICL; } - virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) { func = ppu_interpreter::RLDICR; } - virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { func = ppu_interpreter::RLDIC; } - virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { func = ppu_interpreter::RLDIMI; } - virtual void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) { func = ppu_interpreter::RLDC_LR; } + virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { func = ppu_interpreter::RLDICL; } + virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, u32 rc) { func = ppu_interpreter::RLDICR; } + virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { func = ppu_interpreter::RLDIC; } + virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { func = ppu_interpreter::RLDIMI; } + virtual void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, u32 is_r, u32 rc) { func = ppu_interpreter::RLDC_LR; } virtual void CMP(u32 crfd, u32 l, u32 ra, u32 rb) { func = ppu_interpreter::CMP; } virtual void TW(u32 to, u32 ra, u32 rb) { func = ppu_interpreter::TW; } virtual void LVSL(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVSL; } virtual void LVEBX(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVEBX; } - virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::SUBFC; } - virtual void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) { func = ppu_interpreter::MULHDU; } - virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::ADDC; } - virtual void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) { func = ppu_interpreter::MULHWU; } + virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::SUBFC; } + virtual void MULHDU(u32 rd, u32 ra, u32 rb, u32 rc) { func = ppu_interpreter::MULHDU; } + virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::ADDC; } + virtual void MULHWU(u32 rd, u32 ra, u32 rb, u32 rc) { func = ppu_interpreter::MULHWU; } virtual void MFOCRF(u32 a, u32 rd, u32 crm) { func = ppu_interpreter::MFOCRF; } virtual void LWARX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LWARX; } virtual void LDX(u32 ra, u32 rs, u32 rb) { func = ppu_interpreter::LDX; } virtual void LWZX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LWZX; } - virtual void SLW(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::SLW; } - virtual void CNTLZW(u32 ra, u32 rs, bool rc) { func = ppu_interpreter::CNTLZW; } - virtual void SLD(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::SLD; } - virtual void AND(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::AND; } + virtual void SLW(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::SLW; } + virtual void CNTLZW(u32 ra, u32 rs, u32 rc) { func = ppu_interpreter::CNTLZW; } + virtual void SLD(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::SLD; } + virtual void AND(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::AND; } virtual void CMPL(u32 bf, u32 l, u32 ra, u32 rb) { func = ppu_interpreter::CMPL; } virtual void LVSR(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVSR; } virtual void LVEHX(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVEHX; } - virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::SUBF; } + virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::SUBF; } virtual void LDUX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LDUX; } virtual void DCBST(u32 ra, u32 rb) { func = ppu_interpreter::DCBST; } virtual void LWZUX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LWZUX; } - virtual void CNTLZD(u32 ra, u32 rs, bool rc) { func = ppu_interpreter::CNTLZD; } - virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::ANDC; } + virtual void CNTLZD(u32 ra, u32 rs, u32 rc) { func = ppu_interpreter::CNTLZD; } + virtual void ANDC(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::ANDC; } virtual void TD(u32 to, u32 ra, u32 rb) { func = ppu_interpreter::TD; } virtual void LVEWX(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVEWX; } - virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) { func = ppu_interpreter::MULHD; } - virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) { func = ppu_interpreter::MULHW; } + virtual void MULHD(u32 rd, u32 ra, u32 rb, u32 rc) { func = ppu_interpreter::MULHD; } + virtual void MULHW(u32 rd, u32 ra, u32 rb, u32 rc) { func = ppu_interpreter::MULHW; } virtual void LDARX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LDARX; } virtual void DCBF(u32 ra, u32 rb) { func = ppu_interpreter::DCBF; } virtual void LBZX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LBZX; } virtual void LVX(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVX; } - virtual void NEG(u32 rd, u32 ra, u32 oe, bool rc) { func = ppu_interpreter::NEG; } + virtual void NEG(u32 rd, u32 ra, u32 oe, u32 rc) { func = ppu_interpreter::NEG; } virtual void LBZUX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LBZUX; } - virtual void NOR(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::NOR; } + virtual void NOR(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::NOR; } virtual void STVEBX(u32 vs, u32 ra, u32 rb) { func = ppu_interpreter::STVEBX; } - virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::SUBFE; } - virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::ADDE; } + virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::SUBFE; } + virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::ADDE; } virtual void MTOCRF(u32 l, u32 crm, u32 rs) { func = ppu_interpreter::MTOCRF; } virtual void STDX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STDX; } virtual void STWCX_(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STWCX_; } @@ -797,24 +797,24 @@ public: virtual void STDUX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STDUX; } virtual void STWUX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STWUX; } virtual void STVEWX(u32 vs, u32 ra, u32 rb) { func = ppu_interpreter::STVEWX; } - virtual void SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) { func = ppu_interpreter::SUBFZE; } - virtual void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) { func = ppu_interpreter::ADDZE; } + virtual void SUBFZE(u32 rd, u32 ra, u32 oe, u32 rc) { func = ppu_interpreter::SUBFZE; } + virtual void ADDZE(u32 rd, u32 ra, u32 oe, u32 rc) { func = ppu_interpreter::ADDZE; } virtual void STDCX_(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STDCX_; } virtual void STBX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STBX; } virtual void STVX(u32 vs, u32 ra, u32 rb) { func = ppu_interpreter::STVX; } - virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::MULLD; } - virtual void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) { func = ppu_interpreter::SUBFME; } - virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) { func = ppu_interpreter::ADDME; } - virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::MULLW; } + virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::MULLD; } + virtual void SUBFME(u32 rd, u32 ra, u32 oe, u32 rc) { func = ppu_interpreter::SUBFME; } + virtual void ADDME(u32 rd, u32 ra, u32 oe, u32 rc) { func = ppu_interpreter::ADDME; } + virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::MULLW; } virtual void DCBTST(u32 ra, u32 rb, u32 th) { func = ppu_interpreter::DCBTST; } virtual void STBUX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STBUX; } - virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::ADD; } + virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::ADD; } virtual void DCBT(u32 ra, u32 rb, u32 th) { func = ppu_interpreter::DCBT; } virtual void LHZX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LHZX; } - virtual void EQV(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::EQV; } + virtual void EQV(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::EQV; } virtual void ECIWX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::ECIWX; } virtual void LHZUX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LHZUX; } - virtual void XOR(u32 rs, u32 ra, u32 rb, bool rc) { func = ppu_interpreter::XOR; } + virtual void XOR(u32 rs, u32 ra, u32 rb, u32 rc) { func = ppu_interpreter::XOR; } virtual void MFSPR(u32 rd, u32 spr) { func = ppu_interpreter::MFSPR; } virtual void LWAX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LWAX; } virtual void DST(u32 ra, u32 rb, u32 strm, u32 t) { func = ppu_interpreter::DST; } @@ -825,25 +825,25 @@ public: virtual void DSTST(u32 ra, u32 rb, u32 strm, u32 t) { func = ppu_interpreter::DSTST; } virtual void LHAUX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LHAUX; } virtual void STHX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STHX; } - virtual void ORC(u32 rs, u32 ra, u32 rb, bool rc) { func = ppu_interpreter::ORC; } + virtual void ORC(u32 rs, u32 ra, u32 rb, u32 rc) { func = ppu_interpreter::ORC; } virtual void ECOWX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::ECOWX; } virtual void STHUX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STHUX; } - virtual void OR(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::OR; } - virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::DIVDU; } - virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::DIVWU; } + virtual void OR(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::OR; } + virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::DIVDU; } + virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::DIVWU; } virtual void MTSPR(u32 spr, u32 rs) { func = ppu_interpreter::MTSPR; } virtual void DCBI(u32 ra, u32 rb) { func = ppu_interpreter::DCBI; } - virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::NAND; } + virtual void NAND(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::NAND; } virtual void STVXL(u32 vs, u32 ra, u32 rb) { func = ppu_interpreter::STVXL; } - virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::DIVD; } - virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { func = ppu_interpreter::DIVW; } + virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::DIVD; } + virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { func = ppu_interpreter::DIVW; } virtual void LVLX(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVLX; } virtual void LDBRX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LDBRX; } virtual void LSWX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LSWX; } virtual void LWBRX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LWBRX; } virtual void LFSX(u32 frd, u32 ra, u32 rb) { func = ppu_interpreter::LFSX; } - virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::SRW; } - virtual void SRD(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::SRD; } + virtual void SRW(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::SRW; } + virtual void SRD(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::SRD; } virtual void LVRX(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVRX; } virtual void LSWI(u32 rd, u32 ra, u32 nb) { func = ppu_interpreter::LSWI; } virtual void LFSUX(u32 frd, u32 ra, u32 rb) { func = ppu_interpreter::LFSUX; } @@ -862,21 +862,21 @@ public: virtual void STFDUX(u32 frs, u32 ra, u32 rb) { func = ppu_interpreter::STFDUX; } virtual void LVLXL(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVLXL; } virtual void LHBRX(u32 rd, u32 ra, u32 rb) { func = ppu_interpreter::LHBRX; } - virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::SRAW; } - virtual void SRAD(u32 ra, u32 rs, u32 rb, bool rc) { func = ppu_interpreter::SRAD; } + virtual void SRAW(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::SRAW; } + virtual void SRAD(u32 ra, u32 rs, u32 rb, u32 rc) { func = ppu_interpreter::SRAD; } virtual void LVRXL(u32 vd, u32 ra, u32 rb) { func = ppu_interpreter::LVRXL; } virtual void DSS(u32 strm, u32 a) { func = ppu_interpreter::DSS; } - virtual void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) { func = ppu_interpreter::SRAWI; } - virtual void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) { func = ppu_interpreter::SRADI; } - virtual void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) { func = ppu_interpreter::SRADI; } + virtual void SRAWI(u32 ra, u32 rs, u32 sh, u32 rc) { func = ppu_interpreter::SRAWI; } + virtual void SRADI1(u32 ra, u32 rs, u32 sh, u32 rc) { func = ppu_interpreter::SRADI; } + virtual void SRADI2(u32 ra, u32 rs, u32 sh, u32 rc) { func = ppu_interpreter::SRADI; } virtual void EIEIO() { func = ppu_interpreter::EIEIO; } virtual void STVLXL(u32 vs, u32 ra, u32 rb) { func = ppu_interpreter::STVLXL; } virtual void STHBRX(u32 rs, u32 ra, u32 rb) { func = ppu_interpreter::STHBRX; } - virtual void EXTSH(u32 ra, u32 rs, bool rc) { func = ppu_interpreter::EXTSH; } + virtual void EXTSH(u32 ra, u32 rs, u32 rc) { func = ppu_interpreter::EXTSH; } virtual void STVRXL(u32 sd, u32 ra, u32 rb) { func = ppu_interpreter::STVRXL; } - virtual void EXTSB(u32 ra, u32 rs, bool rc) { func = ppu_interpreter::EXTSB; } + virtual void EXTSB(u32 ra, u32 rs, u32 rc) { func = ppu_interpreter::EXTSB; } virtual void STFIWX(u32 frs, u32 ra, u32 rb) { func = ppu_interpreter::STFIWX; } - virtual void EXTSW(u32 ra, u32 rs, bool rc) { func = ppu_interpreter::EXTSW; } + virtual void EXTSW(u32 ra, u32 rs, u32 rc) { func = ppu_interpreter::EXTSW; } virtual void ICBI(u32 ra, u32 rb) { func = ppu_interpreter::ICBI; } virtual void DCBZ(u32 ra, u32 rb) { func = ppu_interpreter::DCBZ; } virtual void LWZ(u32 rd, u32 ra, s32 d) { func = ppu_interpreter::LWZ; } @@ -906,48 +906,48 @@ public: virtual void LD(u32 rd, u32 ra, s32 ds) { func = ppu_interpreter::LD; } virtual void LDU(u32 rd, u32 ra, s32 ds) { func = ppu_interpreter::LDU; } virtual void LWA(u32 rd, u32 ra, s32 ds) { func = ppu_interpreter::LWA; } - virtual void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) { func = ppu_interpreter::FDIVS; } - virtual void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) { func = ppu_interpreter::FSUBS; } - virtual void FADDS(u32 frd, u32 fra, u32 frb, bool rc) { func = ppu_interpreter::FADDS; } - virtual void FSQRTS(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FSQRTS; } - virtual void FRES(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FRES; } - virtual void FMULS(u32 frd, u32 fra, u32 frc, bool rc) { func = ppu_interpreter::FMULS; } - virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FMADDS; } - virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FMSUBS; } - virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FNMSUBS; } - virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FNMADDS; } + virtual void FDIVS(u32 frd, u32 fra, u32 frb, u32 rc) { func = ppu_interpreter::FDIVS; } + virtual void FSUBS(u32 frd, u32 fra, u32 frb, u32 rc) { func = ppu_interpreter::FSUBS; } + virtual void FADDS(u32 frd, u32 fra, u32 frb, u32 rc) { func = ppu_interpreter::FADDS; } + virtual void FSQRTS(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FSQRTS; } + virtual void FRES(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FRES; } + virtual void FMULS(u32 frd, u32 fra, u32 frc, u32 rc) { func = ppu_interpreter::FMULS; } + virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FMADDS; } + virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FMSUBS; } + virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FNMSUBS; } + virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FNMADDS; } virtual void STD(u32 rs, u32 ra, s32 ds) { func = ppu_interpreter::STD; } virtual void STDU(u32 rs, u32 ra, s32 ds) { func = ppu_interpreter::STDU; } - virtual void MTFSB1(u32 bt, bool rc) { func = ppu_interpreter::MTFSB1; } + virtual void MTFSB1(u32 bt, u32 rc) { func = ppu_interpreter::MTFSB1; } virtual void MCRFS(u32 bf, u32 bfa) { func = ppu_interpreter::MCRFS; } - virtual void MTFSB0(u32 bt, bool rc) { func = ppu_interpreter::MTFSB0; } - virtual void MTFSFI(u32 crfd, u32 i, bool rc) { func = ppu_interpreter::MTFSFI; } - virtual void MFFS(u32 frd, bool rc) { func = ppu_interpreter::MFFS; } - virtual void MTFSF(u32 flm, u32 frb, bool rc) { func = ppu_interpreter::MTFSF; } + virtual void MTFSB0(u32 bt, u32 rc) { func = ppu_interpreter::MTFSB0; } + virtual void MTFSFI(u32 crfd, u32 i, u32 rc) { func = ppu_interpreter::MTFSFI; } + virtual void MFFS(u32 frd, u32 rc) { func = ppu_interpreter::MFFS; } + virtual void MTFSF(u32 flm, u32 frb, u32 rc) { func = ppu_interpreter::MTFSF; } virtual void FCMPU(u32 bf, u32 fra, u32 frb) { func = ppu_interpreter::FCMPU; } - virtual void FRSP(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FRSP; } - virtual void FCTIW(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FCTIW; } - virtual void FCTIWZ(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FCTIWZ; } - virtual void FDIV(u32 frd, u32 fra, u32 frb, bool rc) { func = ppu_interpreter::FDIV; } - virtual void FSUB(u32 frd, u32 fra, u32 frb, bool rc) { func = ppu_interpreter::FSUB; } - virtual void FADD(u32 frd, u32 fra, u32 frb, bool rc) { func = ppu_interpreter::FADD; } - virtual void FSQRT(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FSQRT; } - virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FSEL; } - virtual void FMUL(u32 frd, u32 fra, u32 frc, bool rc) { func = ppu_interpreter::FMUL; } - virtual void FRSQRTE(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FRSQRTE; } - virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FMSUB; } - virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FMADD; } - virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FNMSUB; } - virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { func = ppu_interpreter::FNMADD; } + virtual void FRSP(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FRSP; } + virtual void FCTIW(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FCTIW; } + virtual void FCTIWZ(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FCTIWZ; } + virtual void FDIV(u32 frd, u32 fra, u32 frb, u32 rc) { func = ppu_interpreter::FDIV; } + virtual void FSUB(u32 frd, u32 fra, u32 frb, u32 rc) { func = ppu_interpreter::FSUB; } + virtual void FADD(u32 frd, u32 fra, u32 frb, u32 rc) { func = ppu_interpreter::FADD; } + virtual void FSQRT(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FSQRT; } + virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FSEL; } + virtual void FMUL(u32 frd, u32 fra, u32 frc, u32 rc) { func = ppu_interpreter::FMUL; } + virtual void FRSQRTE(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FRSQRTE; } + virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FMSUB; } + virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FMADD; } + virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FNMSUB; } + virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { func = ppu_interpreter::FNMADD; } virtual void FCMPO(u32 crfd, u32 fra, u32 frb) { func = ppu_interpreter::FCMPO; } - virtual void FNEG(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FNEG; } - virtual void FMR(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FMR; } - virtual void FNABS(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FNABS; } - virtual void FABS(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FABS; } - virtual void FCTID(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FCTID; } - virtual void FCTIDZ(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FCTIDZ; } - virtual void FCFID(u32 frd, u32 frb, bool rc) { func = ppu_interpreter::FCFID; } + virtual void FNEG(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FNEG; } + virtual void FMR(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FMR; } + virtual void FNABS(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FNABS; } + virtual void FABS(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FABS; } + virtual void FCTID(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FCTID; } + virtual void FCTIDZ(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FCTIDZ; } + virtual void FCFID(u32 frd, u32 frb, u32 rc) { func = ppu_interpreter::FCFID; } virtual void UNK(const u32 code, const u32 opcode, const u32 gcode) { func = ppu_interpreter::UNK; } }; \ No newline at end of file diff --git a/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp b/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp index 119be09b8a..bbd95897c3 100644 --- a/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp +++ b/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp @@ -2158,7 +2158,7 @@ void Compiler::BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) { CreateBranch(CheckBranchCondition(bo, bi), ctr_i32, lk ? true : false); } -void Compiler::RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { +void Compiler::RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); auto rsh_i64 = m_ir_builder->CreateShl(rs_i64, 32); @@ -2182,7 +2182,7 @@ void Compiler::RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { } } -void Compiler::RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { +void Compiler::RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); auto rsh_i64 = m_ir_builder->CreateShl(rs_i64, 32); @@ -2202,7 +2202,7 @@ void Compiler::RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { } } -void Compiler::RLWNM(u32 ra, u32 rs, u32 rb, u32 mb, u32 me, bool rc) { +void Compiler::RLWNM(u32 ra, u32 rs, u32 rb, u32 mb, u32 me, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); auto rsh_i64 = m_ir_builder->CreateShl(rs_i64, 32); @@ -2259,7 +2259,7 @@ void Compiler::ANDIS_(u32 ra, u32 rs, u32 uimm16) { SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0)); } -void Compiler::RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { +void Compiler::RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { auto rs_i64 = GetGpr(rs); auto res_i64 = rs_i64; if (sh) { @@ -2276,7 +2276,7 @@ void Compiler::RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { } } -void Compiler::RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) { +void Compiler::RLDICR(u32 ra, u32 rs, u32 sh, u32 me, u32 rc) { auto rs_i64 = GetGpr(rs); auto res_i64 = rs_i64; if (sh) { @@ -2293,7 +2293,7 @@ void Compiler::RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) { } } -void Compiler::RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { +void Compiler::RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { auto rs_i64 = GetGpr(rs); auto res_i64 = rs_i64; if (sh) { @@ -2310,7 +2310,7 @@ void Compiler::RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { } } -void Compiler::RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { +void Compiler::RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) { auto rs_i64 = GetGpr(rs); auto ra_i64 = GetGpr(ra); auto res_i64 = rs_i64; @@ -2331,7 +2331,7 @@ void Compiler::RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) { } } -void Compiler::RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) { +void Compiler::RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, u32 is_r, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto shl_i64 = m_ir_builder->CreateAnd(rb_i64, 0x3F); @@ -2419,7 +2419,7 @@ void Compiler::LVEBX(u32 vd, u32 ra, u32 rb) { SetVr(vd, vd_v16i8); } -void Compiler::SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); ra_i64 = m_ir_builder->CreateNeg(ra_i64); auto rb_i64 = GetGpr(rb); @@ -2439,7 +2439,7 @@ void Compiler::SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { } } -void Compiler::ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::ADDC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, rb_i64); @@ -2457,7 +2457,7 @@ void Compiler::ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { } } -void Compiler::MULHDU(u32 rd, u32 ra, u32 rb, bool rc) { +void Compiler::MULHDU(u32 rd, u32 ra, u32 rb, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto ra_i128 = m_ir_builder->CreateZExt(ra_i64, m_ir_builder->getIntNTy(128)); @@ -2472,7 +2472,7 @@ void Compiler::MULHDU(u32 rd, u32 ra, u32 rb, bool rc) { } } -void Compiler::MULHWU(u32 rd, u32 ra, u32 rb, bool rc) { +void Compiler::MULHWU(u32 rd, u32 ra, u32 rb, u32 rc) { auto ra_i32 = GetGpr(ra, 32); auto rb_i32 = GetGpr(rb, 32); auto ra_i64 = m_ir_builder->CreateZExt(ra_i32, m_ir_builder->getInt64Ty()); @@ -2532,7 +2532,7 @@ void Compiler::LWZX(u32 rd, u32 ra, u32 rb) { SetGpr(rd, mem_i64); } -void Compiler::SLW(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::SLW(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); auto rb_i8 = GetGpr(rb, 8); @@ -2548,7 +2548,7 @@ void Compiler::SLW(u32 ra, u32 rs, u32 rb, bool rc) { } } -void Compiler::CNTLZW(u32 ra, u32 rs, bool rc) { +void Compiler::CNTLZW(u32 ra, u32 rs, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto res_i32 = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::ctlz, m_ir_builder->getInt32Ty()), rs_i32, m_ir_builder->getInt1(false)); auto res_i64 = m_ir_builder->CreateZExt(res_i32, m_ir_builder->getInt64Ty()); @@ -2559,7 +2559,7 @@ void Compiler::CNTLZW(u32 ra, u32 rs, bool rc) { } } -void Compiler::SLD(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::SLD(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rs_i128 = m_ir_builder->CreateZExt(rs_i64, m_ir_builder->getIntNTy(128)); auto rb_i8 = GetGpr(rb, 8); @@ -2574,7 +2574,7 @@ void Compiler::SLD(u32 ra, u32 rs, u32 rb, bool rc) { } } -void Compiler::AND(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::AND(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateAnd(rs_i64, rb_i64); @@ -2649,7 +2649,7 @@ void Compiler::LVEHX(u32 vd, u32 ra, u32 rb) { SetVr(vd, vd_v8i16); } -void Compiler::SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::SUBF(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto diff_i64 = m_ir_builder->CreateSub(rb_i64, ra_i64); @@ -2691,7 +2691,7 @@ void Compiler::LWZUX(u32 rd, u32 ra, u32 rb) { SetGpr(ra, addr_i64); } -void Compiler::CNTLZD(u32 ra, u32 rs, bool rc) { +void Compiler::CNTLZD(u32 ra, u32 rs, u32 rc) { auto rs_i64 = GetGpr(rs); auto res_i64 = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::ctlz, m_ir_builder->getInt64Ty()), rs_i64, m_ir_builder->getInt1(false)); SetGpr(ra, res_i64); @@ -2701,7 +2701,7 @@ void Compiler::CNTLZD(u32 ra, u32 rs, bool rc) { } } -void Compiler::ANDC(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::ANDC(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); rb_i64 = m_ir_builder->CreateNot(rb_i64); @@ -2734,7 +2734,7 @@ void Compiler::LVEWX(u32 vd, u32 ra, u32 rb) { SetVr(vd, vd_v4i32); } -void Compiler::MULHD(u32 rd, u32 ra, u32 rb, bool rc) { +void Compiler::MULHD(u32 rd, u32 ra, u32 rb, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto ra_i128 = m_ir_builder->CreateSExt(ra_i64, m_ir_builder->getIntNTy(128)); @@ -2749,7 +2749,7 @@ void Compiler::MULHD(u32 rd, u32 ra, u32 rb, bool rc) { } } -void Compiler::MULHW(u32 rd, u32 ra, u32 rb, bool rc) { +void Compiler::MULHW(u32 rd, u32 ra, u32 rb, u32 rc) { auto ra_i32 = GetGpr(ra, 32); auto rb_i32 = GetGpr(rb, 32); auto ra_i64 = m_ir_builder->CreateSExt(ra_i32, m_ir_builder->getInt64Ty()); @@ -2808,7 +2808,7 @@ void Compiler::LVX(u32 vd, u32 ra, u32 rb) { SetVr(vd, mem_i128); } -void Compiler::NEG(u32 rd, u32 ra, u32 oe, bool rc) { +void Compiler::NEG(u32 rd, u32 ra, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto diff_i64 = m_ir_builder->CreateSub(m_ir_builder->getInt64(0), ra_i64); SetGpr(rd, diff_i64); @@ -2834,7 +2834,7 @@ void Compiler::LBZUX(u32 rd, u32 ra, u32 rb) { SetGpr(ra, addr_i64); } -void Compiler::NOR(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::NOR(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateOr(rs_i64, rb_i64); @@ -2860,7 +2860,7 @@ void Compiler::STVEBX(u32 vs, u32 ra, u32 rb) { WriteMemory(addr_i64, val_i8); } -void Compiler::SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ca_i64 = GetXerCa(); auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); @@ -2885,7 +2885,7 @@ void Compiler::SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { } } -void Compiler::ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::ADDE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ca_i64 = GetXerCa(); auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); @@ -3019,7 +3019,7 @@ void Compiler::STVEWX(u32 vs, u32 ra, u32 rb) { WriteMemory(addr_i64, val_i32, 4); } -void Compiler::ADDZE(u32 rd, u32 ra, u32 oe, bool rc) { +void Compiler::ADDZE(u32 rd, u32 ra, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto ca_i64 = GetXerCa(); auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64); @@ -3038,7 +3038,7 @@ void Compiler::ADDZE(u32 rd, u32 ra, u32 oe, bool rc) { } } -void Compiler::SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) { +void Compiler::SUBFZE(u32 rd, u32 ra, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); ra_i64 = m_ir_builder->CreateNot(ra_i64); auto ca_i64 = GetXerCa(); @@ -3099,7 +3099,7 @@ void Compiler::STVX(u32 vs, u32 ra, u32 rb) { WriteMemory(addr_i64, GetVr(vs), 16); } -void Compiler::SUBFME(u32 rd, u32 ra, u32 oe, bool rc) { +void Compiler::SUBFME(u32 rd, u32 ra, u32 oe, u32 rc) { auto ca_i64 = GetXerCa(); auto ra_i64 = GetGpr(ra); ra_i64 = m_ir_builder->CreateNot(ra_i64); @@ -3123,7 +3123,7 @@ void Compiler::SUBFME(u32 rd, u32 ra, u32 oe, bool rc) { } } -void Compiler::MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::MULLD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto prod_i64 = m_ir_builder->CreateMul(ra_i64, rb_i64); @@ -3139,7 +3139,7 @@ void Compiler::MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { } } -void Compiler::ADDME(u32 rd, u32 ra, u32 oe, bool rc) { +void Compiler::ADDME(u32 rd, u32 ra, u32 oe, u32 rc) { auto ca_i64 = GetXerCa(); auto ra_i64 = GetGpr(ra); auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64); @@ -3162,7 +3162,7 @@ void Compiler::ADDME(u32 rd, u32 ra, u32 oe, bool rc) { } } -void Compiler::MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::MULLW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i32 = GetGpr(ra, 32); auto rb_i32 = GetGpr(rb, 32); auto ra_i64 = m_ir_builder->CreateSExt(ra_i32, m_ir_builder->getInt64Ty()); @@ -3194,7 +3194,7 @@ void Compiler::STBUX(u32 rs, u32 ra, u32 rb) { SetGpr(ra, addr_i64); } -void Compiler::ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::ADD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto sum_i64 = m_ir_builder->CreateAdd(ra_i64, rb_i64); @@ -3227,7 +3227,7 @@ void Compiler::LHZX(u32 rd, u32 ra, u32 rb) { SetGpr(rd, mem_i64); } -void Compiler::EQV(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::EQV(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateXor(rs_i64, rb_i64); @@ -3263,7 +3263,7 @@ void Compiler::LHZUX(u32 rd, u32 ra, u32 rb) { SetGpr(ra, addr_i64); } -void Compiler::XOR(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::XOR(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateXor(rs_i64, rb_i64); @@ -3387,7 +3387,7 @@ void Compiler::STHX(u32 rs, u32 ra, u32 rb) { WriteMemory(addr_i64, GetGpr(rs, 16)); } -void Compiler::ORC(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::ORC(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); rb_i64 = m_ir_builder->CreateNot(rb_i64); @@ -3419,7 +3419,7 @@ void Compiler::STHUX(u32 rs, u32 ra, u32 rb) { SetGpr(ra, addr_i64); } -void Compiler::OR(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::OR(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateOr(rs_i64, rb_i64); @@ -3430,7 +3430,7 @@ void Compiler::OR(u32 ra, u32 rs, u32 rb, bool rc) { } } -void Compiler::DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateUDiv(ra_i64, rb_i64); @@ -3448,7 +3448,7 @@ void Compiler::DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { // TODO make sure an exception does not occur on divide by 0 and overflow } -void Compiler::DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i32 = GetGpr(ra, 32); auto rb_i32 = GetGpr(rb, 32); auto res_i32 = m_ir_builder->CreateUDiv(ra_i32, rb_i32); @@ -3491,7 +3491,7 @@ void Compiler::MTSPR(u32 spr, u32 rs) { } -void Compiler::NAND(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::NAND(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateAnd(rs_i64, rb_i64); @@ -3507,7 +3507,7 @@ void Compiler::STVXL(u32 vs, u32 ra, u32 rb) { STVX(vs, ra, rb); } -void Compiler::DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::DIVD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i64 = GetGpr(ra); auto rb_i64 = GetGpr(rb); auto res_i64 = m_ir_builder->CreateSDiv(ra_i64, rb_i64); @@ -3525,7 +3525,7 @@ void Compiler::DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { // TODO make sure an exception does not occur on divide by 0 and overflow } -void Compiler::DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { +void Compiler::DIVW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) { auto ra_i32 = GetGpr(ra, 32); auto rb_i32 = GetGpr(rb, 32); auto res_i32 = m_ir_builder->CreateSDiv(ra_i32, rb_i32); @@ -3598,7 +3598,7 @@ void Compiler::LFSX(u32 frd, u32 ra, u32 rb) { SetFpr(frd, mem_i32); } -void Compiler::SRW(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::SRW(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); auto rb_i8 = GetGpr(rb, 8); @@ -3612,7 +3612,7 @@ void Compiler::SRW(u32 ra, u32 rs, u32 rb, bool rc) { } } -void Compiler::SRD(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::SRD(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rs_i128 = m_ir_builder->CreateZExt(rs_i64, m_ir_builder->getIntNTy(128)); auto rb_i8 = GetGpr(rb, 8); @@ -3866,7 +3866,7 @@ void Compiler::LHBRX(u32 rd, u32 ra, u32 rb) { SetGpr(rd, mem_i64); } -void Compiler::SRAW(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::SRAW(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); rs_i64 = m_ir_builder->CreateShl(rs_i64, 32); @@ -3888,7 +3888,7 @@ void Compiler::SRAW(u32 ra, u32 rs, u32 rb, bool rc) { } } -void Compiler::SRAD(u32 ra, u32 rs, u32 rb, bool rc) { +void Compiler::SRAD(u32 ra, u32 rs, u32 rb, u32 rc) { auto rs_i64 = GetGpr(rs); auto rs_i128 = m_ir_builder->CreateZExt(rs_i64, m_ir_builder->getIntNTy(128)); rs_i128 = m_ir_builder->CreateShl(rs_i128, 64); @@ -3920,7 +3920,7 @@ void Compiler::DSS(u32 strm, u32 a) { m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing)); } -void Compiler::SRAWI(u32 ra, u32 rs, u32 sh, bool rc) { +void Compiler::SRAWI(u32 ra, u32 rs, u32 sh, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateZExt(rs_i32, m_ir_builder->getInt64Ty()); rs_i64 = m_ir_builder->CreateShl(rs_i64, 32); @@ -3939,7 +3939,7 @@ void Compiler::SRAWI(u32 ra, u32 rs, u32 sh, bool rc) { } } -void Compiler::SRADI1(u32 ra, u32 rs, u32 sh, bool rc) { +void Compiler::SRADI1(u32 ra, u32 rs, u32 sh, u32 rc) { auto rs_i64 = GetGpr(rs); auto rs_i128 = m_ir_builder->CreateZExt(rs_i64, m_ir_builder->getIntNTy(128)); rs_i128 = m_ir_builder->CreateShl(rs_i128, 64); @@ -3959,7 +3959,7 @@ void Compiler::SRADI1(u32 ra, u32 rs, u32 sh, bool rc) { } } -void Compiler::SRADI2(u32 ra, u32 rs, u32 sh, bool rc) { +void Compiler::SRADI2(u32 ra, u32 rs, u32 sh, u32 rc) { SRADI1(ra, rs, sh, rc); } @@ -3981,7 +3981,7 @@ void Compiler::STHBRX(u32 rs, u32 ra, u32 rb) { WriteMemory(addr_i64, GetGpr(rs, 16), 0, false); } -void Compiler::EXTSH(u32 ra, u32 rs, bool rc) { +void Compiler::EXTSH(u32 ra, u32 rs, u32 rc) { auto rs_i16 = GetGpr(rs, 16); auto rs_i64 = m_ir_builder->CreateSExt(rs_i16, m_ir_builder->getInt64Ty()); SetGpr(ra, rs_i64); @@ -3995,7 +3995,7 @@ void Compiler::STVRXL(u32 vs, u32 ra, u32 rb) { STVRX(vs, ra, rb); } -void Compiler::EXTSB(u32 ra, u32 rs, bool rc) { +void Compiler::EXTSB(u32 ra, u32 rs, u32 rc) { auto rs_i8 = GetGpr(rs, 8); auto rs_i64 = m_ir_builder->CreateSExt(rs_i8, m_ir_builder->getInt64Ty()); SetGpr(ra, rs_i64); @@ -4017,7 +4017,7 @@ void Compiler::STFIWX(u32 frs, u32 ra, u32 rb) { WriteMemory(addr_i64, frs_i32); } -void Compiler::EXTSW(u32 ra, u32 rs, bool rc) { +void Compiler::EXTSW(u32 ra, u32 rs, u32 rc) { auto rs_i32 = GetGpr(rs, 32); auto rs_i64 = m_ir_builder->CreateSExt(rs_i32, m_ir_builder->getInt64Ty()); SetGpr(ra, rs_i64); @@ -4340,7 +4340,7 @@ void Compiler::LWA(u32 rd, u32 ra, s32 ds) { SetGpr(rd, mem_i64); } -void Compiler::FDIVS(u32 frd, u32 fra, u32 frb, bool rc) { +void Compiler::FDIVS(u32 frd, u32 fra, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFDiv(ra_f64, rb_f64); @@ -4355,7 +4355,7 @@ void Compiler::FDIVS(u32 frd, u32 fra, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FSUBS(u32 frd, u32 fra, u32 frb, bool rc) { +void Compiler::FSUBS(u32 frd, u32 fra, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFSub(ra_f64, rb_f64); @@ -4370,7 +4370,7 @@ void Compiler::FSUBS(u32 frd, u32 fra, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FADDS(u32 frd, u32 fra, u32 frb, bool rc) { +void Compiler::FADDS(u32 frd, u32 fra, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFAdd(ra_f64, rb_f64); @@ -4385,7 +4385,7 @@ void Compiler::FADDS(u32 frd, u32 fra, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FSQRTS(u32 frd, u32 frb, bool rc) { +void Compiler::FSQRTS(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f64 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::sqrt, m_ir_builder->getDoubleTy()), rb_f64); auto res_f32 = m_ir_builder->CreateFPTrunc(res_f64, m_ir_builder->getFloatTy()); @@ -4399,7 +4399,7 @@ void Compiler::FSQRTS(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FRES(u32 frd, u32 frb, bool rc) { +void Compiler::FRES(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFDiv(ConstantFP::get(m_ir_builder->getDoubleTy(), 1.0), rb_f64); auto res_f32 = m_ir_builder->CreateFPTrunc(res_f64, m_ir_builder->getFloatTy()); @@ -4413,7 +4413,7 @@ void Compiler::FRES(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FMULS(u32 frd, u32 fra, u32 frc, bool rc) { +void Compiler::FMULS(u32 frd, u32 fra, u32 frc, u32 rc) { auto ra_f64 = GetFpr(fra); auto rc_f64 = GetFpr(frc); auto res_f64 = m_ir_builder->CreateFMul(ra_f64, rc_f64); @@ -4428,7 +4428,7 @@ void Compiler::FMULS(u32 frd, u32 fra, u32 frc, bool rc) { // TODO: Set flags } -void Compiler::FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4444,7 +4444,7 @@ void Compiler::FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4461,7 +4461,7 @@ void Compiler::FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4479,7 +4479,7 @@ void Compiler::FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4515,7 +4515,7 @@ void Compiler::STDU(u32 rs, u32 ra, s32 ds) { SetGpr(ra, addr_i64); } -void Compiler::MTFSB1(u32 crbd, bool rc) { +void Compiler::MTFSB1(u32 crbd, u32 rc) { auto fpscr_i32 = GetFpscr(); fpscr_i32 = SetBit(fpscr_i32, crbd, m_ir_builder->getInt32(1), false); SetFpscr(fpscr_i32); @@ -4557,7 +4557,7 @@ void Compiler::MCRFS(u32 crbd, u32 crbs) { SetFpscr(fpscr_i32); } -void Compiler::MTFSB0(u32 crbd, bool rc) { +void Compiler::MTFSB0(u32 crbd, u32 rc) { auto fpscr_i32 = GetFpscr(); fpscr_i32 = ClrBit(fpscr_i32, crbd); SetFpscr(fpscr_i32); @@ -4568,7 +4568,7 @@ void Compiler::MTFSB0(u32 crbd, bool rc) { } } -void Compiler::MTFSFI(u32 crfd, u32 i, bool rc) { +void Compiler::MTFSFI(u32 crfd, u32 i, u32 rc) { auto fpscr_i32 = GetFpscr(); fpscr_i32 = SetNibble(fpscr_i32, crfd, m_ir_builder->getInt32(i & 0xF)); SetFpscr(fpscr_i32); @@ -4579,7 +4579,7 @@ void Compiler::MTFSFI(u32 crfd, u32 i, bool rc) { } } -void Compiler::MFFS(u32 frd, bool rc) { +void Compiler::MFFS(u32 frd, u32 rc) { auto fpscr_i32 = GetFpscr(); auto fpscr_i64 = m_ir_builder->CreateZExt(fpscr_i32, m_ir_builder->getInt64Ty()); SetFpr(frd, fpscr_i64); @@ -4590,7 +4590,7 @@ void Compiler::MFFS(u32 frd, bool rc) { } } -void Compiler::MTFSF(u32 flm, u32 frb, bool rc) { +void Compiler::MTFSF(u32 flm, u32 frb, u32 rc) { u32 mask = 0; for(u32 i = 0; i < 8; i++) { if (flm & (1 << i)) { @@ -4624,7 +4624,7 @@ void Compiler::FCMPU(u32 crfd, u32 fra, u32 frb) { // TODO: Set flags / Handle NaN } -void Compiler::FRSP(u32 frd, u32 frb, bool rc) { +void Compiler::FRSP(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f32 = m_ir_builder->CreateFPTrunc(rb_f64, m_ir_builder->getFloatTy()); auto res_f64 = m_ir_builder->CreateFPExt(res_f32, m_ir_builder->getDoubleTy()); @@ -4639,7 +4639,7 @@ void Compiler::FRSP(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FCTIW(u32 frd, u32 frb, bool rc) { +void Compiler::FCTIW(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto max_i1 = m_ir_builder->CreateFCmpOGT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), 2147483647.0)); auto min_i1 = m_ir_builder->CreateFCmpULT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), -2147483648.0)); @@ -4657,7 +4657,7 @@ void Compiler::FCTIW(u32 frd, u32 frb, bool rc) { // TODO: Set flags / Implement rounding modes } -void Compiler::FCTIWZ(u32 frd, u32 frb, bool rc) { +void Compiler::FCTIWZ(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto max_i1 = m_ir_builder->CreateFCmpOGT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), 2147483647.0)); auto min_i1 = m_ir_builder->CreateFCmpULT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), -2147483648.0)); @@ -4675,7 +4675,7 @@ void Compiler::FCTIWZ(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FDIV(u32 frd, u32 fra, u32 frb, bool rc) { +void Compiler::FDIV(u32 frd, u32 fra, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFDiv(ra_f64, rb_f64); @@ -4689,7 +4689,7 @@ void Compiler::FDIV(u32 frd, u32 fra, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FSUB(u32 frd, u32 fra, u32 frb, bool rc) { +void Compiler::FSUB(u32 frd, u32 fra, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFSub(ra_f64, rb_f64); @@ -4703,7 +4703,7 @@ void Compiler::FSUB(u32 frd, u32 fra, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FADD(u32 frd, u32 fra, u32 frb, bool rc) { +void Compiler::FADD(u32 frd, u32 fra, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto res_f64 = m_ir_builder->CreateFAdd(ra_f64, rb_f64); @@ -4717,7 +4717,7 @@ void Compiler::FADD(u32 frd, u32 fra, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FSQRT(u32 frd, u32 frb, bool rc) { +void Compiler::FSQRT(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f64 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::sqrt, m_ir_builder->getDoubleTy()), rb_f64); SetFpr(frd, res_f64); @@ -4730,7 +4730,7 @@ void Compiler::FSQRT(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FSEL(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4746,7 +4746,7 @@ void Compiler::FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FMUL(u32 frd, u32 fra, u32 frc, bool rc) { +void Compiler::FMUL(u32 frd, u32 fra, u32 frc, u32 rc) { auto ra_f64 = GetFpr(fra); auto rc_f64 = GetFpr(frc); auto res_f64 = m_ir_builder->CreateFMul(ra_f64, rc_f64); @@ -4760,7 +4760,7 @@ void Compiler::FMUL(u32 frd, u32 fra, u32 frc, bool rc) { // TODO: Set flags } -void Compiler::FRSQRTE(u32 frd, u32 frb, bool rc) { +void Compiler::FRSQRTE(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f64 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::sqrt, m_ir_builder->getDoubleTy()), rb_f64); res_f64 = m_ir_builder->CreateFDiv(ConstantFP::get(m_ir_builder->getDoubleTy(), 1.0), res_f64); @@ -4772,7 +4772,7 @@ void Compiler::FRSQRTE(u32 frd, u32 frb, bool rc) { } } -void Compiler::FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4788,7 +4788,7 @@ void Compiler::FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4803,7 +4803,7 @@ void Compiler::FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4819,7 +4819,7 @@ void Compiler::FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) { +void Compiler::FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) { auto ra_f64 = GetFpr(fra); auto rb_f64 = GetFpr(frb); auto rc_f64 = GetFpr(frc); @@ -4849,7 +4849,7 @@ void Compiler::FCMPO(u32 crfd, u32 fra, u32 frb) { // TODO: Set flags / Handle NaN } -void Compiler::FNEG(u32 frd, u32 frb, bool rc) { +void Compiler::FNEG(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); rb_f64 = m_ir_builder->CreateFNeg(rb_f64); SetFpr(frd, rb_f64); @@ -4862,7 +4862,7 @@ void Compiler::FNEG(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FMR(u32 frd, u32 frb, bool rc) { +void Compiler::FMR(u32 frd, u32 frb, u32 rc) { SetFpr(frd, GetFpr(frb)); if (rc) { @@ -4873,7 +4873,7 @@ void Compiler::FMR(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FNABS(u32 frd, u32 frb, bool rc) { +void Compiler::FNABS(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f64 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::fabs, m_ir_builder->getDoubleTy()), rb_f64); res_f64 = m_ir_builder->CreateFNeg(res_f64); @@ -4887,7 +4887,7 @@ void Compiler::FNABS(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FABS(u32 frd, u32 frb, bool rc) { +void Compiler::FABS(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto res_f64 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::fabs, m_ir_builder->getDoubleTy()), rb_f64); SetFpr(frd, res_f64); @@ -4900,7 +4900,7 @@ void Compiler::FABS(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FCTID(u32 frd, u32 frb, bool rc) { +void Compiler::FCTID(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto max_i1 = m_ir_builder->CreateFCmpOGT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), 9223372036854775807.0)); auto min_i1 = m_ir_builder->CreateFCmpULT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), -9223372036854775808.0)); @@ -4917,7 +4917,7 @@ void Compiler::FCTID(u32 frd, u32 frb, bool rc) { // TODO: Set flags / Implement rounding modes } -void Compiler::FCTIDZ(u32 frd, u32 frb, bool rc) { +void Compiler::FCTIDZ(u32 frd, u32 frb, u32 rc) { auto rb_f64 = GetFpr(frb); auto max_i1 = m_ir_builder->CreateFCmpOGT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), 9223372036854775807.0)); auto min_i1 = m_ir_builder->CreateFCmpULT(rb_f64, ConstantFP::get(m_ir_builder->getDoubleTy(), -9223372036854775808.0)); @@ -4934,7 +4934,7 @@ void Compiler::FCTIDZ(u32 frd, u32 frb, bool rc) { // TODO: Set flags } -void Compiler::FCFID(u32 frd, u32 frb, bool rc) { +void Compiler::FCFID(u32 frd, u32 frb, u32 rc) { auto rb_i64 = GetFpr(frb, 64, true); auto res_f64 = m_ir_builder->CreateSIToFP(rb_i64, m_ir_builder->getDoubleTy()); SetFpr(frd, res_f64); @@ -5603,7 +5603,6 @@ RecompilationEngine::RecompilationEngine() } RecompilationEngine::~RecompilationEngine() { - cv.notify_one(); join(); } diff --git a/rpcs3/Emu/Cell/PPULLVMRecompiler.h b/rpcs3/Emu/Cell/PPULLVMRecompiler.h index 0627332c72..fc3867006e 100644 --- a/rpcs3/Emu/Cell/PPULLVMRecompiler.h +++ b/rpcs3/Emu/Cell/PPULLVMRecompiler.h @@ -486,59 +486,59 @@ namespace ppu_recompiler_llvm { void CRORC(u32 bt, u32 ba, u32 bb) override; void CROR(u32 bt, u32 ba, u32 bb) override; void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) override; - void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) override; - void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) override; - void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) override; + void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) override; + void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) override; + void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, u32 rc) override; void ORI(u32 rs, u32 ra, u32 uimm16) override; void ORIS(u32 rs, u32 ra, u32 uimm16) override; void XORI(u32 ra, u32 rs, u32 uimm16) override; void XORIS(u32 ra, u32 rs, u32 uimm16) override; void ANDI_(u32 ra, u32 rs, u32 uimm16) override; void ANDIS_(u32 ra, u32 rs, u32 uimm16) override; - void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) override; - void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) override; - void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) override; - void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) override; - void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) override; + void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) override; + void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, u32 rc) override; + void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) override; + void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) override; + void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, u32 is_r, u32 rc) override; void CMP(u32 crfd, u32 l, u32 ra, u32 rb) override; void TW(u32 to, u32 ra, u32 rb) override; void LVSL(u32 vd, u32 ra, u32 rb) override; void LVEBX(u32 vd, u32 ra, u32 rb) override; - void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; - void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) override; - void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; - void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) override; + void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; + void MULHDU(u32 rd, u32 ra, u32 rb, u32 rc) override; + void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; + void MULHWU(u32 rd, u32 ra, u32 rb, u32 rc) override; void MFOCRF(u32 a, u32 rd, u32 crm) override; void LWARX(u32 rd, u32 ra, u32 rb) override; void LDX(u32 ra, u32 rs, u32 rb) override; void LWZX(u32 rd, u32 ra, u32 rb) override; - void SLW(u32 ra, u32 rs, u32 rb, bool rc) override; - void CNTLZW(u32 ra, u32 rs, bool rc) override; - void SLD(u32 ra, u32 rs, u32 rb, bool rc) override; - void AND(u32 ra, u32 rs, u32 rb, bool rc) override; + void SLW(u32 ra, u32 rs, u32 rb, u32 rc) override; + void CNTLZW(u32 ra, u32 rs, u32 rc) override; + void SLD(u32 ra, u32 rs, u32 rb, u32 rc) override; + void AND(u32 ra, u32 rs, u32 rb, u32 rc) override; void CMPL(u32 bf, u32 l, u32 ra, u32 rb) override; void LVSR(u32 vd, u32 ra, u32 rb) override; void LVEHX(u32 vd, u32 ra, u32 rb) override; - void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; + void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; void LDUX(u32 rd, u32 ra, u32 rb) override; void DCBST(u32 ra, u32 rb) override; void LWZUX(u32 rd, u32 ra, u32 rb) override; - void CNTLZD(u32 ra, u32 rs, bool rc) override; - void ANDC(u32 ra, u32 rs, u32 rb, bool rc) override; + void CNTLZD(u32 ra, u32 rs, u32 rc) override; + void ANDC(u32 ra, u32 rs, u32 rb, u32 rc) override; void TD(u32 to, u32 ra, u32 rb) override; void LVEWX(u32 vd, u32 ra, u32 rb) override; - void MULHD(u32 rd, u32 ra, u32 rb, bool rc) override; - void MULHW(u32 rd, u32 ra, u32 rb, bool rc) override; + void MULHD(u32 rd, u32 ra, u32 rb, u32 rc) override; + void MULHW(u32 rd, u32 ra, u32 rb, u32 rc) override; void LDARX(u32 rd, u32 ra, u32 rb) override; void DCBF(u32 ra, u32 rb) override; void LBZX(u32 rd, u32 ra, u32 rb) override; void LVX(u32 vd, u32 ra, u32 rb) override; - void NEG(u32 rd, u32 ra, u32 oe, bool rc) override; + void NEG(u32 rd, u32 ra, u32 oe, u32 rc) override; void LBZUX(u32 rd, u32 ra, u32 rb) override; - void NOR(u32 ra, u32 rs, u32 rb, bool rc) override; + void NOR(u32 ra, u32 rs, u32 rb, u32 rc) override; void STVEBX(u32 vs, u32 ra, u32 rb) override; - void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; - void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; + void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; + void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; void MTOCRF(u32 l, u32 crm, u32 rs) override; void STDX(u32 rs, u32 ra, u32 rb) override; void STWCX_(u32 rs, u32 ra, u32 rb) override; @@ -547,24 +547,24 @@ namespace ppu_recompiler_llvm { void STDUX(u32 rs, u32 ra, u32 rb) override; void STWUX(u32 rs, u32 ra, u32 rb) override; void STVEWX(u32 vs, u32 ra, u32 rb) override; - void SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) override; - void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) override; + void SUBFZE(u32 rd, u32 ra, u32 oe, u32 rc) override; + void ADDZE(u32 rd, u32 ra, u32 oe, u32 rc) override; void STDCX_(u32 rs, u32 ra, u32 rb) override; void STBX(u32 rs, u32 ra, u32 rb) override; void STVX(u32 vs, u32 ra, u32 rb) override; - void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; - void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) override; - void ADDME(u32 rd, u32 ra, u32 oe, bool rc) override; - void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; + void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; + void SUBFME(u32 rd, u32 ra, u32 oe, u32 rc) override; + void ADDME(u32 rd, u32 ra, u32 oe, u32 rc) override; + void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; void DCBTST(u32 ra, u32 rb, u32 th) override; void STBUX(u32 rs, u32 ra, u32 rb) override; - void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; + void ADD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; void DCBT(u32 ra, u32 rb, u32 th) override; void LHZX(u32 rd, u32 ra, u32 rb) override; - void EQV(u32 ra, u32 rs, u32 rb, bool rc) override; + void EQV(u32 ra, u32 rs, u32 rb, u32 rc) override; void ECIWX(u32 rd, u32 ra, u32 rb) override; void LHZUX(u32 rd, u32 ra, u32 rb) override; - void XOR(u32 rs, u32 ra, u32 rb, bool rc) override; + void XOR(u32 rs, u32 ra, u32 rb, u32 rc) override; void MFSPR(u32 rd, u32 spr) override; void LWAX(u32 rd, u32 ra, u32 rb) override; void DST(u32 ra, u32 rb, u32 strm, u32 t) override; @@ -575,25 +575,25 @@ namespace ppu_recompiler_llvm { void DSTST(u32 ra, u32 rb, u32 strm, u32 t) override; void LHAUX(u32 rd, u32 ra, u32 rb) override; void STHX(u32 rs, u32 ra, u32 rb) override; - void ORC(u32 rs, u32 ra, u32 rb, bool rc) override; + void ORC(u32 rs, u32 ra, u32 rb, u32 rc) override; void ECOWX(u32 rs, u32 ra, u32 rb) override; void STHUX(u32 rs, u32 ra, u32 rb) override; - void OR(u32 ra, u32 rs, u32 rb, bool rc) override; - void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; - void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; + void OR(u32 ra, u32 rs, u32 rb, u32 rc) override; + void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; + void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; void MTSPR(u32 spr, u32 rs) override; void DCBI(u32 ra, u32 rb) override; - void NAND(u32 ra, u32 rs, u32 rb, bool rc) override; + void NAND(u32 ra, u32 rs, u32 rb, u32 rc) override; void STVXL(u32 vs, u32 ra, u32 rb) override; - void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; - void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; + void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; + void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) override; void LVLX(u32 vd, u32 ra, u32 rb) override; void LDBRX(u32 rd, u32 ra, u32 rb) override; void LSWX(u32 rd, u32 ra, u32 rb) override; void LWBRX(u32 rd, u32 ra, u32 rb) override; void LFSX(u32 frd, u32 ra, u32 rb) override; - void SRW(u32 ra, u32 rs, u32 rb, bool rc) override; - void SRD(u32 ra, u32 rs, u32 rb, bool rc) override; + void SRW(u32 ra, u32 rs, u32 rb, u32 rc) override; + void SRD(u32 ra, u32 rs, u32 rb, u32 rc) override; void LVRX(u32 vd, u32 ra, u32 rb) override; void LSWI(u32 rd, u32 ra, u32 nb) override; void LFSUX(u32 frd, u32 ra, u32 rb) override; @@ -612,21 +612,21 @@ namespace ppu_recompiler_llvm { void STFDUX(u32 frs, u32 ra, u32 rb) override; void LVLXL(u32 vd, u32 ra, u32 rb) override; void LHBRX(u32 rd, u32 ra, u32 rb) override; - void SRAW(u32 ra, u32 rs, u32 rb, bool rc) override; - void SRAD(u32 ra, u32 rs, u32 rb, bool rc) override; + void SRAW(u32 ra, u32 rs, u32 rb, u32 rc) override; + void SRAD(u32 ra, u32 rs, u32 rb, u32 rc) override; void LVRXL(u32 vd, u32 ra, u32 rb) override; void DSS(u32 strm, u32 a) override; - void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) override; - void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) override; - void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) override; + void SRAWI(u32 ra, u32 rs, u32 sh, u32 rc) override; + void SRADI1(u32 ra, u32 rs, u32 sh, u32 rc) override; + void SRADI2(u32 ra, u32 rs, u32 sh, u32 rc) override; void EIEIO() override; void STVLXL(u32 vs, u32 ra, u32 rb) override; void STHBRX(u32 rs, u32 ra, u32 rb) override; - void EXTSH(u32 ra, u32 rs, bool rc) override; + void EXTSH(u32 ra, u32 rs, u32 rc) override; void STVRXL(u32 sd, u32 ra, u32 rb) override; - void EXTSB(u32 ra, u32 rs, bool rc) override; + void EXTSB(u32 ra, u32 rs, u32 rc) override; void STFIWX(u32 frs, u32 ra, u32 rb) override; - void EXTSW(u32 ra, u32 rs, bool rc) override; + void EXTSW(u32 ra, u32 rs, u32 rc) override; void ICBI(u32 ra, u32 rb) override; void DCBZ(u32 ra, u32 rb) override; void LWZ(u32 rd, u32 ra, s32 d) override; @@ -656,48 +656,48 @@ namespace ppu_recompiler_llvm { void LD(u32 rd, u32 ra, s32 ds) override; void LDU(u32 rd, u32 ra, s32 ds) override; void LWA(u32 rd, u32 ra, s32 ds) override; - void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) override; - void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) override; - void FADDS(u32 frd, u32 fra, u32 frb, bool rc) override; - void FSQRTS(u32 frd, u32 frb, bool rc) override; - void FRES(u32 frd, u32 frb, bool rc) override; - void FMULS(u32 frd, u32 fra, u32 frc, bool rc) override; - void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; + void FDIVS(u32 frd, u32 fra, u32 frb, u32 rc) override; + void FSUBS(u32 frd, u32 fra, u32 frb, u32 rc) override; + void FADDS(u32 frd, u32 fra, u32 frb, u32 rc) override; + void FSQRTS(u32 frd, u32 frb, u32 rc) override; + void FRES(u32 frd, u32 frb, u32 rc) override; + void FMULS(u32 frd, u32 fra, u32 frc, u32 rc) override; + void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; void STD(u32 rs, u32 ra, s32 ds) override; void STDU(u32 rs, u32 ra, s32 ds) override; - void MTFSB1(u32 bt, bool rc) override; + void MTFSB1(u32 bt, u32 rc) override; void MCRFS(u32 bf, u32 bfa) override; - void MTFSB0(u32 bt, bool rc) override; - void MTFSFI(u32 crfd, u32 i, bool rc) override; - void MFFS(u32 frd, bool rc) override; - void MTFSF(u32 flm, u32 frb, bool rc) override; + void MTFSB0(u32 bt, u32 rc) override; + void MTFSFI(u32 crfd, u32 i, u32 rc) override; + void MFFS(u32 frd, u32 rc) override; + void MTFSF(u32 flm, u32 frb, u32 rc) override; void FCMPU(u32 bf, u32 fra, u32 frb) override; - void FRSP(u32 frd, u32 frb, bool rc) override; - void FCTIW(u32 frd, u32 frb, bool rc) override; - void FCTIWZ(u32 frd, u32 frb, bool rc) override; - void FDIV(u32 frd, u32 fra, u32 frb, bool rc) override; - void FSUB(u32 frd, u32 fra, u32 frb, bool rc) override; - void FADD(u32 frd, u32 fra, u32 frb, bool rc) override; - void FSQRT(u32 frd, u32 frb, bool rc) override; - void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FMUL(u32 frd, u32 fra, u32 frc, bool rc) override; - void FRSQRTE(u32 frd, u32 frb, bool rc) override; - void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; - void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) override; + void FRSP(u32 frd, u32 frb, u32 rc) override; + void FCTIW(u32 frd, u32 frb, u32 rc) override; + void FCTIWZ(u32 frd, u32 frb, u32 rc) override; + void FDIV(u32 frd, u32 fra, u32 frb, u32 rc) override; + void FSUB(u32 frd, u32 fra, u32 frb, u32 rc) override; + void FADD(u32 frd, u32 fra, u32 frb, u32 rc) override; + void FSQRT(u32 frd, u32 frb, u32 rc) override; + void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FMUL(u32 frd, u32 fra, u32 frc, u32 rc) override; + void FRSQRTE(u32 frd, u32 frb, u32 rc) override; + void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; + void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) override; void FCMPO(u32 crfd, u32 fra, u32 frb) override; - void FNEG(u32 frd, u32 frb, bool rc) override; - void FMR(u32 frd, u32 frb, bool rc) override; - void FNABS(u32 frd, u32 frb, bool rc) override; - void FABS(u32 frd, u32 frb, bool rc) override; - void FCTID(u32 frd, u32 frb, bool rc) override; - void FCTIDZ(u32 frd, u32 frb, bool rc) override; - void FCFID(u32 frd, u32 frb, bool rc) override; + void FNEG(u32 frd, u32 frb, u32 rc) override; + void FMR(u32 frd, u32 frb, u32 rc) override; + void FNABS(u32 frd, u32 frb, u32 rc) override; + void FABS(u32 frd, u32 frb, u32 rc) override; + void FCTID(u32 frd, u32 frb, u32 rc) override; + void FCTIDZ(u32 frd, u32 frb, u32 rc) override; + void FCFID(u32 frd, u32 frb, u32 rc) override; void UNK(const u32 code, const u32 opcode, const u32 gcode) override; diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h index c23669d3bf..185f22905b 100644 --- a/rpcs3/Emu/Cell/PPUOpcodes.h +++ b/rpcs3/Emu/Cell/PPUOpcodes.h @@ -664,59 +664,59 @@ public: virtual void CRORC(u32 bt, u32 ba, u32 bb) = 0; virtual void CROR(u32 bt, u32 ba, u32 bb) = 0; virtual void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) = 0; - virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0; - virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0; - virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) = 0; + virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) = 0; + virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, u32 rc) = 0; + virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, u32 rc) = 0; virtual void ORI(u32 rs, u32 ra, u32 uimm16) = 0; virtual void ORIS(u32 rs, u32 ra, u32 uimm16) = 0; virtual void XORI(u32 ra, u32 rs, u32 uimm16) = 0; virtual void XORIS(u32 ra, u32 rs, u32 uimm16) = 0; virtual void ANDI_(u32 ra, u32 rs, u32 uimm16) = 0; virtual void ANDIS_(u32 ra, u32 rs, u32 uimm16) = 0; - virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0; - virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) = 0; - virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0; - virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0; - virtual void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) = 0; + virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) = 0; + virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, u32 rc) = 0; + virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) = 0; + virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 rc) = 0; + virtual void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, u32 is_r, u32 rc) = 0; virtual void CMP(u32 crfd, u32 l, u32 ra, u32 rb) = 0; virtual void TW(u32 to, u32 ra, u32 rb) = 0; virtual void LVSL(u32 vd, u32 ra, u32 rb) = 0; virtual void LVEBX(u32 vd, u32 ra, u32 rb) = 0; - virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; - virtual void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) = 0; - virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; - virtual void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) = 0; + virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; + virtual void MULHDU(u32 rd, u32 ra, u32 rb, u32 rc) = 0; + virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; + virtual void MULHWU(u32 rd, u32 ra, u32 rb, u32 rc) = 0; virtual void MFOCRF(u32 a, u32 rd, u32 crm) = 0; virtual void LWARX(u32 rd, u32 ra, u32 rb) = 0; virtual void LDX(u32 ra, u32 rs, u32 rb) = 0; virtual void LWZX(u32 rd, u32 ra, u32 rb) = 0; - virtual void SLW(u32 ra, u32 rs, u32 rb, bool rc) = 0; - virtual void CNTLZW(u32 ra, u32 rs, bool rc) = 0; - virtual void SLD(u32 ra, u32 rs, u32 rb, bool rc) = 0; - virtual void AND(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void SLW(u32 ra, u32 rs, u32 rb, u32 rc) = 0; + virtual void CNTLZW(u32 ra, u32 rs, u32 rc) = 0; + virtual void SLD(u32 ra, u32 rs, u32 rb, u32 rc) = 0; + virtual void AND(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void CMPL(u32 bf, u32 l, u32 ra, u32 rb) = 0; virtual void LVSR(u32 vd, u32 ra, u32 rb) = 0; virtual void LVEHX(u32 vd, u32 ra, u32 rb) = 0; - virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; virtual void LDUX(u32 rd, u32 ra, u32 rb) = 0; virtual void DCBST(u32 ra, u32 rb) = 0; virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0; - virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0; - virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void CNTLZD(u32 ra, u32 rs, u32 rc) = 0; + virtual void ANDC(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void TD(u32 to, u32 ra, u32 rb) = 0; virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0; - virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0; - virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0; + virtual void MULHD(u32 rd, u32 ra, u32 rb, u32 rc) = 0; + virtual void MULHW(u32 rd, u32 ra, u32 rb, u32 rc) = 0; virtual void LDARX(u32 rd, u32 ra, u32 rb) = 0; virtual void DCBF(u32 ra, u32 rb) = 0; virtual void LBZX(u32 rd, u32 ra, u32 rb) = 0; virtual void LVX(u32 vd, u32 ra, u32 rb) = 0; - virtual void NEG(u32 rd, u32 ra, u32 oe, bool rc) = 0; + virtual void NEG(u32 rd, u32 ra, u32 oe, u32 rc) = 0; virtual void LBZUX(u32 rd, u32 ra, u32 rb) = 0; - virtual void NOR(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void NOR(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void STVEBX(u32 vs, u32 ra, u32 rb) = 0; - virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; - virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; + virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; virtual void MTOCRF(u32 l, u32 crm, u32 rs) = 0; virtual void STDX(u32 rs, u32 ra, u32 rb) = 0; virtual void STWCX_(u32 rs, u32 ra, u32 rb) = 0; @@ -725,24 +725,24 @@ public: virtual void STDUX(u32 rs, u32 ra, u32 rb) = 0; virtual void STWUX(u32 rs, u32 ra, u32 rb) = 0; virtual void STVEWX(u32 vs, u32 ra, u32 rb) = 0; - virtual void SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) = 0; - virtual void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) = 0; + virtual void SUBFZE(u32 rd, u32 ra, u32 oe, u32 rc) = 0; + virtual void ADDZE(u32 rd, u32 ra, u32 oe, u32 rc) = 0; virtual void STDCX_(u32 rs, u32 ra, u32 rb) = 0; virtual void STBX(u32 rs, u32 ra, u32 rb) = 0; virtual void STVX(u32 vs, u32 ra, u32 rb) = 0; - virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; - virtual void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) = 0; - virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0; - virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; + virtual void SUBFME(u32 rd, u32 ra, u32 oe, u32 rc) = 0; + virtual void ADDME(u32 rd, u32 ra, u32 oe, u32 rc) = 0; + virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; virtual void DCBTST(u32 ra, u32 rb, u32 th) = 0; virtual void STBUX(u32 rs, u32 ra, u32 rb) = 0; - virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; virtual void DCBT(u32 ra, u32 rb, u32 th) = 0; virtual void LHZX(u32 rd, u32 ra, u32 rb) = 0; - virtual void EQV(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void EQV(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void ECIWX(u32 rd, u32 ra, u32 rb) = 0; virtual void LHZUX(u32 rd, u32 ra, u32 rb) = 0; - virtual void XOR(u32 rs, u32 ra, u32 rb, bool rc) = 0; + virtual void XOR(u32 rs, u32 ra, u32 rb, u32 rc) = 0; virtual void MFSPR(u32 rd, u32 spr) = 0; virtual void LWAX(u32 rd, u32 ra, u32 rb) = 0; virtual void DST(u32 ra, u32 rb, u32 strm, u32 t) = 0; @@ -753,25 +753,25 @@ public: virtual void DSTST(u32 ra, u32 rb, u32 strm, u32 t) = 0; virtual void LHAUX(u32 rd, u32 ra, u32 rb) = 0; virtual void STHX(u32 rs, u32 ra, u32 rb) = 0; - virtual void ORC(u32 rs, u32 ra, u32 rb, bool rc) = 0; + virtual void ORC(u32 rs, u32 ra, u32 rb, u32 rc) = 0; virtual void ECOWX(u32 rs, u32 ra, u32 rb) = 0; virtual void STHUX(u32 rs, u32 ra, u32 rb) = 0; - virtual void OR(u32 ra, u32 rs, u32 rb, bool rc) = 0; - virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; - virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void OR(u32 ra, u32 rs, u32 rb, u32 rc) = 0; + virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; + virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; virtual void MTSPR(u32 spr, u32 rs) = 0; virtual void DCBI(u32 ra, u32 rb) = 0; - virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void NAND(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0; - virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; - virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; + virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, u32 rc) = 0; virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0; virtual void LDBRX(u32 rd, u32 ra, u32 rb) = 0; virtual void LSWX(u32 rd, u32 ra, u32 rb) = 0; virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0; virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0; - virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0; - virtual void SRD(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void SRW(u32 ra, u32 rs, u32 rb, u32 rc) = 0; + virtual void SRD(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void LVRX(u32 vd, u32 ra, u32 rb) = 0; virtual void LSWI(u32 rd, u32 ra, u32 nb) = 0; virtual void LFSUX(u32 frd, u32 ra, u32 rb) = 0; @@ -790,21 +790,21 @@ public: virtual void STFDUX(u32 frs, u32 ra, u32 rb) = 0; virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0; virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0; - virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0; - virtual void SRAD(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void SRAW(u32 ra, u32 rs, u32 rb, u32 rc) = 0; + virtual void SRAD(u32 ra, u32 rs, u32 rb, u32 rc) = 0; virtual void LVRXL(u32 vd, u32 ra, u32 rb) = 0; virtual void DSS(u32 strm, u32 a) = 0; - virtual void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) = 0; - virtual void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) = 0; - virtual void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) = 0; + virtual void SRAWI(u32 ra, u32 rs, u32 sh, u32 rc) = 0; + virtual void SRADI1(u32 ra, u32 rs, u32 sh, u32 rc) = 0; + virtual void SRADI2(u32 ra, u32 rs, u32 sh, u32 rc) = 0; virtual void EIEIO() = 0; virtual void STVLXL(u32 vs, u32 ra, u32 rb) = 0; virtual void STHBRX(u32 rs, u32 ra, u32 rb) = 0; - virtual void EXTSH(u32 ra, u32 rs, bool rc) = 0; + virtual void EXTSH(u32 ra, u32 rs, u32 rc) = 0; virtual void STVRXL(u32 sd, u32 ra, u32 rb) = 0; - virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0; + virtual void EXTSB(u32 ra, u32 rs, u32 rc) = 0; virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0; - virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0; + virtual void EXTSW(u32 ra, u32 rs, u32 rc) = 0; virtual void ICBI(u32 ra, u32 rb) = 0; virtual void DCBZ(u32 ra, u32 rb) = 0; virtual void LWZ(u32 rd, u32 ra, s32 d) = 0; @@ -834,48 +834,48 @@ public: virtual void LD(u32 rd, u32 ra, s32 ds) = 0; virtual void LDU(u32 rd, u32 ra, s32 ds) = 0; virtual void LWA(u32 rd, u32 ra, s32 ds) = 0; - virtual void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) = 0; - virtual void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) = 0; - virtual void FADDS(u32 frd, u32 fra, u32 frb, bool rc) = 0; - virtual void FSQRTS(u32 frd, u32 frb, bool rc) = 0; - virtual void FRES(u32 frd, u32 frb, bool rc) = 0; - virtual void FMULS(u32 frd, u32 fra, u32 frc, bool rc) = 0; - virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FDIVS(u32 frd, u32 fra, u32 frb, u32 rc) = 0; + virtual void FSUBS(u32 frd, u32 fra, u32 frb, u32 rc) = 0; + virtual void FADDS(u32 frd, u32 fra, u32 frb, u32 rc) = 0; + virtual void FSQRTS(u32 frd, u32 frb, u32 rc) = 0; + virtual void FRES(u32 frd, u32 frb, u32 rc) = 0; + virtual void FMULS(u32 frd, u32 fra, u32 frc, u32 rc) = 0; + virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; virtual void STD(u32 rs, u32 ra, s32 ds) = 0; virtual void STDU(u32 rs, u32 ra, s32 ds) = 0; - virtual void MTFSB1(u32 bt, bool rc) = 0; + virtual void MTFSB1(u32 bt, u32 rc) = 0; virtual void MCRFS(u32 bf, u32 bfa) = 0; - virtual void MTFSB0(u32 bt, bool rc) = 0; - virtual void MTFSFI(u32 crfd, u32 i, bool rc) = 0; - virtual void MFFS(u32 frd, bool rc) = 0; - virtual void MTFSF(u32 flm, u32 frb, bool rc) = 0; + virtual void MTFSB0(u32 bt, u32 rc) = 0; + virtual void MTFSFI(u32 crfd, u32 i, u32 rc) = 0; + virtual void MFFS(u32 frd, u32 rc) = 0; + virtual void MTFSF(u32 flm, u32 frb, u32 rc) = 0; virtual void FCMPU(u32 bf, u32 fra, u32 frb) = 0; - virtual void FRSP(u32 frd, u32 frb, bool rc) = 0; - virtual void FCTIW(u32 frd, u32 frb, bool rc) = 0; - virtual void FCTIWZ(u32 frd, u32 frb, bool rc) = 0; - virtual void FDIV(u32 frd, u32 fra, u32 frb, bool rc) = 0; - virtual void FSUB(u32 frd, u32 fra, u32 frb, bool rc) = 0; - virtual void FADD(u32 frd, u32 fra, u32 frb, bool rc) = 0; - virtual void FSQRT(u32 frd, u32 frb, bool rc) = 0; - virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FMUL(u32 frd, u32 fra, u32 frc, bool rc) = 0; - virtual void FRSQRTE(u32 frd, u32 frb, bool rc) = 0; - virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; - virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FRSP(u32 frd, u32 frb, u32 rc) = 0; + virtual void FCTIW(u32 frd, u32 frb, u32 rc) = 0; + virtual void FCTIWZ(u32 frd, u32 frb, u32 rc) = 0; + virtual void FDIV(u32 frd, u32 fra, u32 frb, u32 rc) = 0; + virtual void FSUB(u32 frd, u32 fra, u32 frb, u32 rc) = 0; + virtual void FADD(u32 frd, u32 fra, u32 frb, u32 rc) = 0; + virtual void FSQRT(u32 frd, u32 frb, u32 rc) = 0; + virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FMUL(u32 frd, u32 fra, u32 frc, u32 rc) = 0; + virtual void FRSQRTE(u32 frd, u32 frb, u32 rc) = 0; + virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; + virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, u32 rc) = 0; virtual void FCMPO(u32 crfd, u32 fra, u32 frb) = 0; - virtual void FNEG(u32 frd, u32 frb, bool rc) = 0; - virtual void FMR(u32 frd, u32 frb, bool rc) = 0; - virtual void FNABS(u32 frd, u32 frb, bool rc) = 0; - virtual void FABS(u32 frd, u32 frb, bool rc) = 0; - virtual void FCTID(u32 frd, u32 frb, bool rc) = 0; - virtual void FCTIDZ(u32 frd, u32 frb, bool rc) = 0; - virtual void FCFID(u32 frd, u32 frb, bool rc) = 0; + virtual void FNEG(u32 frd, u32 frb, u32 rc) = 0; + virtual void FMR(u32 frd, u32 frb, u32 rc) = 0; + virtual void FNABS(u32 frd, u32 frb, u32 rc) = 0; + virtual void FABS(u32 frd, u32 frb, u32 rc) = 0; + virtual void FCTID(u32 frd, u32 frb, u32 rc) = 0; + virtual void FCTIDZ(u32 frd, u32 frb, u32 rc) = 0; + virtual void FCFID(u32 frd, u32 frb, u32 rc) = 0; virtual void UNK(const u32 code, const u32 opcode, const u32 gcode) = 0; }; diff --git a/rpcs3/Emu/Cell/PPUThread.cpp b/rpcs3/Emu/Cell/PPUThread.cpp index 02f59d7df8..83b829fb9a 100644 --- a/rpcs3/Emu/Cell/PPUThread.cpp +++ b/rpcs3/Emu/Cell/PPUThread.cpp @@ -498,7 +498,6 @@ PPUThread::PPUThread(const std::string& name) PPUThread::~PPUThread() { - cv.notify_one(); join(); CloseStack(); @@ -507,7 +506,7 @@ PPUThread::~PPUThread() void PPUThread::DumpInformation() const { - if (hle_code < 0) + if (~hle_code < 1024) { LOG_SUCCESS(HLE, "Last function: syscall %lld (%s)", ~hle_code, SysCalls::GetFuncName(hle_code)); } diff --git a/rpcs3/Emu/Cell/PPUThread.h b/rpcs3/Emu/Cell/PPUThread.h index 6204e799a3..276da10924 100644 --- a/rpcs3/Emu/Cell/PPUThread.h +++ b/rpcs3/Emu/Cell/PPUThread.h @@ -543,7 +543,7 @@ public: bool is_joinable = true; bool is_joining = false; - s64 hle_code = 0; // current syscall (inverted value) or function id (positive value) + u64 hle_code = 0; // current syscall (~0..~1023) or function id (1..UINT32_MAX) std::function custom_task; diff --git a/rpcs3/Emu/Cell/RawSPUThread.cpp b/rpcs3/Emu/Cell/RawSPUThread.cpp index 24dfa388d1..4f484a243e 100644 --- a/rpcs3/Emu/Cell/RawSPUThread.cpp +++ b/rpcs3/Emu/Cell/RawSPUThread.cpp @@ -16,7 +16,6 @@ RawSPUThread::RawSPUThread(const std::string& name, u32 index) RawSPUThread::~RawSPUThread() { - cv.notify_one(); join(); Memory.Unmap(offset); diff --git a/rpcs3/Emu/Cell/SPUThread.cpp b/rpcs3/Emu/Cell/SPUThread.cpp index 6fbe114688..b6f33c78d2 100644 --- a/rpcs3/Emu/Cell/SPUThread.cpp +++ b/rpcs3/Emu/Cell/SPUThread.cpp @@ -64,10 +64,10 @@ SPUThread::SPUThread(CPUThreadType type, const std::string& name, u32 index, u32 { } -SPUThread::SPUThread(const std::string& name, u32 index, u32 offset) +SPUThread::SPUThread(const std::string& name, u32 index) : CPUThread(CPU_THREAD_SPU, name, [this]{ return fmt::format("%s[0x%x] Thread (%s)[0x%08x]", GetTypeString(), GetId(), GetName(), PC); }) , index(index) - , offset(offset) + , offset(Memory.MainMem.AllocAlign(0x40000)) { } @@ -75,8 +75,9 @@ SPUThread::~SPUThread() { if (m_type == CPU_THREAD_SPU) { - cv.notify_one(); join(); + + Memory.MainMem.Free(offset); } else if (joinable()) { @@ -86,15 +87,20 @@ SPUThread::~SPUThread() bool SPUThread::IsPaused() const { + if (CPUThread::IsPaused()) + { + return true; + } + if (const auto group = tg.lock()) { - if (group->state == SPU_THREAD_GROUP_STATUS_WAITING || group->state == SPU_THREAD_GROUP_STATUS_SUSPENDED) + if (group->state >= SPU_THREAD_GROUP_STATUS_WAITING && group->state <= SPU_THREAD_GROUP_STATUS_SUSPENDED) { return true; } } - return CPUThread::IsPaused(); + return false; } void SPUThread::DumpInformation() const @@ -511,6 +517,26 @@ u32 SPUThread::get_ch_value(u32 ch) LOG_NOTICE(SPU, "get_ch_value(ch=%d [%s])", ch, ch < 128 ? spu_ch_name[ch] : "???"); } + auto read_channel = [this](spu_channel_t& channel) -> u32 + { + std::unique_lock lock(mutex, std::defer_lock); + + u32 result; + + while (!channel.try_pop(result)) + { + CHECK_EMU_STATUS; + + if (IsStopped()) throw CPUThreadStop{}; + + if (!lock) lock.lock(); + + cv.wait_for(lock, std::chrono::milliseconds(1)); + } + + return result; + }; + switch (ch) { //case SPU_RdSRR0: @@ -518,11 +544,19 @@ u32 SPUThread::get_ch_value(u32 ch) // break; case SPU_RdInMbox: { + std::unique_lock lock(mutex, std::defer_lock); + u32 result, count; - while (!ch_in_mbox.pop(result, count) && !Emu.IsStopped()) + while (!ch_in_mbox.try_pop(result, count)) { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack + CHECK_EMU_STATUS; + + if (IsStopped()) throw CPUThreadStop{}; + + if (!lock) lock.lock(); + + cv.wait_for(lock, std::chrono::milliseconds(1)); } if (count + 1 == 4 /* SPU_IN_MBOX_THRESHOLD */) // TODO: check this @@ -535,13 +569,7 @@ u32 SPUThread::get_ch_value(u32 ch) case MFC_RdTagStat: { - u32 result; - while (!ch_tag_stat.pop(result) && !Emu.IsStopped()) - { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack - } - - return result; + return read_channel(ch_tag_stat); } case MFC_RdTagMask: @@ -551,46 +579,22 @@ u32 SPUThread::get_ch_value(u32 ch) case SPU_RdSigNotify1: { - u32 result; - while (!ch_snr1.pop(result) && !Emu.IsStopped()) - { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack - } - - return result; + return read_channel(ch_snr1); } case SPU_RdSigNotify2: { - u32 result; - while (!ch_snr2.pop(result) && !Emu.IsStopped()) - { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack - } - - return result; + return read_channel(ch_snr2); } case MFC_RdAtomicStat: { - u32 result; - while (!ch_atomic_stat.pop(result) && !Emu.IsStopped()) - { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack - } - - return result; + return read_channel(ch_atomic_stat); } case MFC_RdListStallStat: { - u32 result; - while (!ch_stall_stat.pop(result) && !Emu.IsStopped()) - { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack - } - - return result; + return read_channel(ch_stall_stat); } case SPU_RdDec: @@ -639,9 +643,17 @@ void SPUThread::set_ch_value(u32 ch, u32 value) { if (m_type == CPU_THREAD_RAW_SPU) { - while (!ch_out_intr_mbox.push(value) && !Emu.IsStopped()) + std::unique_lock lock(mutex, std::defer_lock); + + while (!ch_out_intr_mbox.try_push(value)) { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack + CHECK_EMU_STATUS; + + if (IsStopped()) throw CPUThreadStop{}; + + if (!lock) lock.lock(); + + cv.wait_for(lock, std::chrono::milliseconds(1)); } int2.set(SPU_INT2_STAT_MAILBOX_INT); @@ -657,7 +669,7 @@ void SPUThread::set_ch_value(u32 ch, u32 value) u8 spup = code & 63; u32 data; - if (!ch_out_mbox.pop(data)) + if (!ch_out_mbox.try_pop(data)) { throw EXCEPTION("sys_spu_thread_send_event(value=0x%x, spup=%d): Out_MBox is empty", value, spup); } @@ -693,7 +705,7 @@ void SPUThread::set_ch_value(u32 ch, u32 value) const u8 spup = code & 63; u32 data; - if (!ch_out_mbox.pop(data)) + if (!ch_out_mbox.try_pop(data)) { throw EXCEPTION("sys_spu_thread_throw_event(value=0x%x, spup=%d): Out_MBox is empty", value, spup); } @@ -729,7 +741,7 @@ void SPUThread::set_ch_value(u32 ch, u32 value) u32 flag = value & 0xffffff; u32 data; - if (!ch_out_mbox.pop(data)) + if (!ch_out_mbox.try_pop(data)) { throw EXCEPTION("sys_event_flag_set_bit(value=0x%x (flag=%d)): Out_MBox is empty", value, flag); } @@ -773,7 +785,7 @@ void SPUThread::set_ch_value(u32 ch, u32 value) u32 flag = value & 0xffffff; u32 data; - if (!ch_out_mbox.pop(data)) + if (!ch_out_mbox.try_pop(data)) { throw EXCEPTION("sys_event_flag_set_bit_impatient(value=0x%x (flag=%d)): Out_MBox is empty", value, flag); } @@ -827,9 +839,17 @@ void SPUThread::set_ch_value(u32 ch, u32 value) case SPU_WrOutMbox: { - while (!ch_out_mbox.push(value) && !Emu.IsStopped()) + std::unique_lock lock(mutex, std::defer_lock); + + while (!ch_out_mbox.try_push(value)) { - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack + CHECK_EMU_STATUS; + + if (IsStopped()) throw CPUThreadStop{}; + + if (!lock) lock.lock(); + + cv.wait_for(lock, std::chrono::milliseconds(1)); } return; @@ -1015,7 +1035,7 @@ void SPUThread::stop_and_signal(u32 code) /* ===== sys_spu_thread_receive_event ===== */ u32 spuq = 0; - if (!ch_out_mbox.pop(spuq)) + if (!ch_out_mbox.try_pop(spuq)) { throw EXCEPTION("sys_spu_thread_receive_event(): cannot read Out_MBox"); } @@ -1033,6 +1053,18 @@ void SPUThread::stop_and_signal(u32 code) LV2_LOCK; + const auto group = tg.lock(); + + if (!group) + { + throw EXCEPTION("Invalid SPU Thread Group"); + } + + if (group->type & SYS_SPU_THREAD_GROUP_TYPE_EXCLUSIVE_NON_CONTEXT) // this check may be inaccurate + { + return ch_in_mbox.push_uncond(CELL_EINVAL); + } + std::shared_ptr queue; for (auto& v : this->spuq) @@ -1053,40 +1085,85 @@ void SPUThread::stop_and_signal(u32 code) return ch_in_mbox.push_uncond(CELL_EINVAL); // TODO: check error value } + // check thread group status + while (group->state >= SPU_THREAD_GROUP_STATUS_WAITING && group->state <= SPU_THREAD_GROUP_STATUS_SUSPENDED) + { + CHECK_EMU_STATUS; + + if (IsStopped()) throw CPUThreadStop{}; + + group->cv.wait_for(lv2_lock, std::chrono::milliseconds(1)); + } + + // change group status + if (group->state == SPU_THREAD_GROUP_STATUS_RUNNING) + { + group->state = SPU_THREAD_GROUP_STATUS_WAITING; + + for (auto& t : group->threads) + { + if (t) t->Sleep(); // trigger status check + } + } + else + { + throw EXCEPTION("Unexpected SPU Thread Group state (%d)", group->state); + } + // protocol is ignored in current implementation queue->waiters++; - while (queue->events.empty()) + // wait on the event queue + while (queue->events.empty() && !queue->cancelled) { - if (queue->cancelled) - { - return ch_in_mbox.push_uncond(CELL_ECANCELED); - } - CHECK_EMU_STATUS; - if (IsStopped()) - { - LOG_WARNING(SPU, "sys_spu_thread_receive_event(spuq=0x%x) aborted", spuq); - return; - } + if (IsStopped()) throw CPUThreadStop{}; queue->cv.wait_for(lv2_lock, std::chrono::milliseconds(1)); } - auto& event = queue->events.front(); - ch_in_mbox.push_uncond(CELL_OK); - ch_in_mbox.push_uncond((u32)event.data1); - ch_in_mbox.push_uncond((u32)event.data2); - ch_in_mbox.push_uncond((u32)event.data3); - - queue->events.pop_front(); - queue->waiters--; - - if (queue->events.size()) + if (queue->cancelled) { - queue->cv.notify_one(); + ch_in_mbox.push_uncond(CELL_ECANCELED); } + else + { + auto& event = queue->events.front(); + ch_in_mbox.push_uncond(CELL_OK); + ch_in_mbox.push_uncond((u32)event.data1); + ch_in_mbox.push_uncond((u32)event.data2); + ch_in_mbox.push_uncond((u32)event.data3); + + queue->events.pop_front(); + queue->waiters--; + + if (queue->events.size()) + { + queue->cv.notify_one(); + } + } + + // restore thread group status + if (group->state == SPU_THREAD_GROUP_STATUS_WAITING) + { + group->state = SPU_THREAD_GROUP_STATUS_RUNNING; + } + else if (group->state == SPU_THREAD_GROUP_STATUS_WAITING_AND_SUSPENDED) + { + group->state = SPU_THREAD_GROUP_STATUS_SUSPENDED; + } + else + { + throw EXCEPTION("Unexpected SPU Thread Group state (%d)", group->state); + } + + for (auto& t : group->threads) + { + if (t) t->Awake(); // untrigger status check + } + + group->cv.notify_all(); return; } @@ -1096,7 +1173,7 @@ void SPUThread::stop_and_signal(u32 code) /* ===== sys_spu_thread_group_exit ===== */ u32 value; - if (!ch_out_mbox.pop(value)) + if (!ch_out_mbox.try_pop(value)) { throw EXCEPTION("sys_spu_thread_group_exit(): cannot read Out_MBox"); } @@ -1112,7 +1189,7 @@ void SPUThread::stop_and_signal(u32 code) if (!group) { - throw EXCEPTION("sys_spu_thread_group_exit(status=0x%x): invalid group", value); + throw EXCEPTION("Invalid SPU Thread Group"); } for (auto t : group->threads) @@ -1126,7 +1203,7 @@ void SPUThread::stop_and_signal(u32 code) group->state = SPU_THREAD_GROUP_STATUS_INITIALIZED; group->exit_status = value; group->join_state |= SPU_TGJSF_GROUP_EXIT; - group->join_cv.notify_one(); + group->cv.notify_one(); return Stop(); } @@ -1147,7 +1224,15 @@ void SPUThread::stop_and_signal(u32 code) LV2_LOCK; + const auto group = tg.lock(); + + if (!group) + { + throw EXCEPTION("Invalid SPU Thread Group"); + } + status |= SPU_STATUS_STOPPED_BY_STOP; + group->cv.notify_one(); return Stop(); } @@ -1189,7 +1274,7 @@ void SPUThread::halt() spu_thread::spu_thread(u32 entry, const std::string& name, u32 stack_size, u32 prio) { - auto spu = Emu.GetIdManager().make_ptr(name, 0, 0x10000); + auto spu = Emu.GetIdManager().make_ptr(name, 0x13370666); spu->PC = entry; diff --git a/rpcs3/Emu/Cell/SPUThread.h b/rpcs3/Emu/Cell/SPUThread.h index f6be10300a..46b9e80aee 100644 --- a/rpcs3/Emu/Cell/SPUThread.h +++ b/rpcs3/Emu/Cell/SPUThread.h @@ -140,7 +140,7 @@ union spu_channel_t atomic sync_var; // atomic variable public: - bool push(u32 value) + bool try_push(u32 value) { bool out_result; @@ -166,7 +166,7 @@ public: sync_var.exchange({ 1, value }); } - bool pop(u32& out_value) + bool try_pop(u32& out_value) { bool out_result; @@ -250,7 +250,7 @@ public: } // out_count: count after removing first element - bool pop(u32& out_value, u32& out_count) + bool try_pop(u32& out_value, u32& out_count) { bool out_result; @@ -633,7 +633,7 @@ protected: SPUThread(CPUThreadType type, const std::string& name, u32 index, u32 offset); public: - SPUThread(const std::string& name, u32 index, u32 offset); + SPUThread(const std::string& name, u32 index); virtual ~SPUThread() override; virtual bool IsPaused() const override; diff --git a/rpcs3/Emu/Memory/atomic.h b/rpcs3/Emu/Memory/atomic.h index 27a5f73bef..e5cc022962 100644 --- a/rpcs3/Emu/Memory/atomic.h +++ b/rpcs3/Emu/Memory/atomic.h @@ -208,40 +208,69 @@ public: } }; -template using if_integral_le_t = std::enable_if_t::value && std::is_integral::value, le_t>; -template using if_integral_be_t = std::enable_if_t::value && std::is_integral::value, be_t>; +template using if_integral_t = std::enable_if_t::value>; -template inline if_integral_le_t operator ++(_atomic_base>& left) +template> inline T operator ++(_atomic_base& left) { return left.from_subtype(sync_fetch_and_add(&left.sub_data, 1) + 1); } -template inline if_integral_le_t operator --(_atomic_base>& left) +template> inline T operator --(_atomic_base& left) { return left.from_subtype(sync_fetch_and_sub(&left.sub_data, 1) - 1); } -template inline if_integral_le_t operator ++(_atomic_base>& left, int) +template> inline T operator ++(_atomic_base& left, int) { return left.from_subtype(sync_fetch_and_add(&left.sub_data, 1)); } -template inline if_integral_le_t operator --(_atomic_base>& left, int) +template> inline T operator --(_atomic_base& left, int) { return left.from_subtype(sync_fetch_and_sub(&left.sub_data, 1)); } -template inline if_integral_le_t operator +=(_atomic_base>& left, T2 right) +template> inline auto operator +=(_atomic_base& left, T2 right) -> decltype(std::declval() + std::declval()) { return left.from_subtype(sync_fetch_and_add(&left.sub_data, right) + right); } -template inline if_integral_le_t operator -=(_atomic_base>& left, T2 right) +template> inline auto operator -=(_atomic_base& left, T2 right) -> decltype(std::declval() - std::declval()) { return left.from_subtype(sync_fetch_and_sub(&left.sub_data, right) - right); } -template inline if_integral_be_t operator ++(_atomic_base>& left) +template> inline le_t operator ++(_atomic_base>& left) +{ + return left.from_subtype(sync_fetch_and_add(&left.sub_data, 1) + 1); +} + +template> inline le_t operator --(_atomic_base>& left) +{ + return left.from_subtype(sync_fetch_and_sub(&left.sub_data, 1) - 1); +} + +template> inline le_t operator ++(_atomic_base>& left, int) +{ + return left.from_subtype(sync_fetch_and_add(&left.sub_data, 1)); +} + +template> inline le_t operator --(_atomic_base>& left, int) +{ + return left.from_subtype(sync_fetch_and_sub(&left.sub_data, 1)); +} + +template> inline auto operator +=(_atomic_base>& left, T2 right) -> decltype(std::declval() + std::declval()) +{ + return left.from_subtype(sync_fetch_and_add(&left.sub_data, right) + right); +} + +template> inline auto operator -=(_atomic_base>& left, T2 right) -> decltype(std::declval() - std::declval()) +{ + return left.from_subtype(sync_fetch_and_sub(&left.sub_data, right) - right); +} + +template> inline be_t operator ++(_atomic_base>& left) { return left.atomic_op([](be_t& value) -> be_t { @@ -249,7 +278,7 @@ template inline if_integral_be_t operator ++(_atomic_base }); } -template inline if_integral_be_t operator --(_atomic_base>& left) +template> inline be_t operator --(_atomic_base>& left) { return left.atomic_op([](be_t& value) -> be_t { @@ -257,7 +286,7 @@ template inline if_integral_be_t operator --(_atomic_base }); } -template inline if_integral_be_t operator ++(_atomic_base>& left, int) +template> inline be_t operator ++(_atomic_base>& left, int) { return left.atomic_op([](be_t& value) -> be_t { @@ -265,7 +294,7 @@ template inline if_integral_be_t operator ++(_atomic_base }); } -template inline if_integral_be_t operator --(_atomic_base>& left, int) +template> inline be_t operator --(_atomic_base>& left, int) { return left.atomic_op([](be_t& value) -> be_t { @@ -273,7 +302,7 @@ template inline if_integral_be_t operator --(_atomic_base }); } -template inline if_integral_be_t operator +=(_atomic_base>& left, T2 right) +template> inline auto operator +=(_atomic_base>& left, T2 right) -> be_t() + std::declval())> { return left.atomic_op([right](be_t& value) -> be_t { @@ -281,7 +310,7 @@ template inline if_integral_be_t operator +=(_at }); } -template inline if_integral_be_t operator -=(_atomic_base>& left, T2 right) +template> inline auto operator -=(_atomic_base>& left, T2 right) -> be_t() - std::declval())> { return left.atomic_op([right](be_t& value) -> be_t { diff --git a/rpcs3/Emu/RSX/GL/GLGSRender.cpp b/rpcs3/Emu/RSX/GL/GLGSRender.cpp index 224128473a..9b9ea7c484 100644 --- a/rpcs3/Emu/RSX/GL/GLGSRender.cpp +++ b/rpcs3/Emu/RSX/GL/GLGSRender.cpp @@ -821,7 +821,6 @@ void GLGSRender::Close() { if (joinable()) { - cv.notify_one(); join(); } diff --git a/rpcs3/Emu/RSX/Null/NullGSRender.h b/rpcs3/Emu/RSX/Null/NullGSRender.h index f12d31d2be..1bd5a26a16 100644 --- a/rpcs3/Emu/RSX/Null/NullGSRender.h +++ b/rpcs3/Emu/RSX/Null/NullGSRender.h @@ -11,8 +11,10 @@ public: virtual ~NullGSRender() override { - cv.notify_one(); - join(); + if (joinable()) + { + throw EXCEPTION("Thread not joined"); + } } private: @@ -46,6 +48,10 @@ private: virtual void Close() { + if (joinable()) + { + join(); + } } virtual void semaphorePGRAPHTextureReadRelease(u32 offset, u32 value) override @@ -59,4 +65,4 @@ private: virtual void semaphorePFIFOAcquire(u32 offset, u32 value) override { } -}; \ No newline at end of file +}; diff --git a/rpcs3/Emu/SysCalls/FuncList.cpp b/rpcs3/Emu/SysCalls/FuncList.cpp index dd5d1e58fa..b240a0d6ed 100644 --- a/rpcs3/Emu/SysCalls/FuncList.cpp +++ b/rpcs3/Emu/SysCalls/FuncList.cpp @@ -2,7 +2,7 @@ #include "Modules.h" #include "SysCalls.h" -std::string SysCalls::GetFuncName(const s64 fid) +std::string SysCalls::GetFuncName(const u64 fid) { // check syscalls switch (~fid) diff --git a/rpcs3/Emu/SysCalls/Modules/cellAudio.cpp b/rpcs3/Emu/SysCalls/Modules/cellAudio.cpp index a118b5a576..ee0be9b527 100644 --- a/rpcs3/Emu/SysCalls/Modules/cellAudio.cpp +++ b/rpcs3/Emu/SysCalls/Modules/cellAudio.cpp @@ -443,7 +443,6 @@ s32 cellAudioQuit() return CELL_AUDIO_ERROR_NOT_INIT; } - g_audio.thread.cv.notify_one(); g_audio.thread.join(); g_audio.state.exchange(AUDIO_STATE_NOT_INITIALIZED); return CELL_OK; diff --git a/rpcs3/Emu/SysCalls/Modules/cellFs.cpp b/rpcs3/Emu/SysCalls/Modules/cellFs.cpp index c59ce26cf3..4a8cd86fd5 100644 --- a/rpcs3/Emu/SysCalls/Modules/cellFs.cpp +++ b/rpcs3/Emu/SysCalls/Modules/cellFs.cpp @@ -924,7 +924,7 @@ s32 cellFsAioFinish(vm::cptr mount_point) return CELL_OK; } -std::atomic g_fs_aio_id(0); +std::atomic g_fs_aio_id; s32 cellFsAioRead(vm::ptr aio, vm::ptr id, fs_aio_cb_t func) { @@ -984,6 +984,8 @@ s32 cellFsSetIoBufferFromDefaultContainer(u32 fd, u32 buffer_size, u32 page_type Module cellFs("cellFs", []() { + g_fs_aio_id = 1; + REG_FUNC(cellFs, cellFsOpen); REG_FUNC(cellFs, cellFsSdataOpen); REG_FUNC(cellFs, cellFsSdataOpenByFd); diff --git a/rpcs3/Emu/SysCalls/SysCalls.h b/rpcs3/Emu/SysCalls/SysCalls.h index be9f52d76e..888f7aa617 100644 --- a/rpcs3/Emu/SysCalls/SysCalls.h +++ b/rpcs3/Emu/SysCalls/SysCalls.h @@ -25,5 +25,5 @@ class SysCalls { public: static void DoSyscall(PPUThread& CPU, u64 code); - static std::string GetFuncName(const s64 fid); + static std::string GetFuncName(const u64 fid); }; diff --git a/rpcs3/Emu/SysCalls/lv2/sys_event.cpp b/rpcs3/Emu/SysCalls/lv2/sys_event.cpp index cb31f7be07..46948f16e8 100644 --- a/rpcs3/Emu/SysCalls/lv2/sys_event.cpp +++ b/rpcs3/Emu/SysCalls/lv2/sys_event.cpp @@ -171,6 +171,8 @@ s32 sys_event_queue_receive(PPUThread& CPU, u32 equeue_id, vm::ptr while (queue->events.empty()) { + CHECK_EMU_STATUS; + if (queue->cancelled) { return CELL_ECANCELED; @@ -182,12 +184,6 @@ s32 sys_event_queue_receive(PPUThread& CPU, u32 equeue_id, vm::ptr return CELL_ETIMEDOUT; } - if (Emu.IsStopped()) - { - sys_event.Warning("sys_event_queue_receive(equeue_id=0x%x) aborted", equeue_id); - return CELL_OK; - } - queue->cv.wait_for(lv2_lock, std::chrono::milliseconds(1)); } diff --git a/rpcs3/Emu/SysCalls/lv2/sys_interrupt.cpp b/rpcs3/Emu/SysCalls/lv2/sys_interrupt.cpp index eaae6b7467..0c9ae4ab42 100644 --- a/rpcs3/Emu/SysCalls/lv2/sys_interrupt.cpp +++ b/rpcs3/Emu/SysCalls/lv2/sys_interrupt.cpp @@ -23,16 +23,14 @@ s32 sys_interrupt_tag_destroy(u32 intrtag) return CELL_ESRCH; } - const auto t = Emu.GetCPU().GetRawSPUThread(intrtag & 0xff); + const auto thread = Emu.GetCPU().GetRawSPUThread(intrtag & 0xff); - if (!t) + if (!thread) { return CELL_ESRCH; } - RawSPUThread& spu = static_cast(*t); - - auto& tag = class_id ? spu.int2 : spu.int0; + auto& tag = class_id ? thread->int2 : thread->int0; if (s32 old = tag.assigned.compare_and_swap(0, -1)) { @@ -58,16 +56,14 @@ s32 sys_interrupt_thread_establish(vm::ptr ih, u32 intrtag, u32 intrthread, return CELL_ESRCH; } - const auto t = Emu.GetCPU().GetRawSPUThread(intrtag & 0xff); + const auto thread = Emu.GetCPU().GetRawSPUThread(intrtag & 0xff); - if (!t) + if (!thread) { return CELL_ESRCH; } - RawSPUThread& spu = static_cast(*t); - - auto& tag = class_id ? spu.int2 : spu.int0; + auto& tag = class_id ? thread->int2 : thread->int0; // CELL_ESTAT is not returned (can't detect exact condition) @@ -78,12 +74,10 @@ s32 sys_interrupt_thread_establish(vm::ptr ih, u32 intrtag, u32 intrthread, return CELL_ESRCH; } - PPUThread& ppu = static_cast(*it); - { LV2_LOCK; - if (ppu.custom_task) + if (it->custom_task) { return CELL_EAGAIN; } @@ -102,7 +96,7 @@ s32 sys_interrupt_thread_establish(vm::ptr ih, u32 intrtag, u32 intrthread, return res; } - ppu.custom_task = [t, &tag, arg](PPUThread& CPU) + it->custom_task = [thread, &tag, arg](PPUThread& CPU) { const auto pc = CPU.PC; const auto rtoc = CPU.GPR[2]; @@ -124,7 +118,7 @@ s32 sys_interrupt_thread_establish(vm::ptr ih, u32 intrtag, u32 intrthread, } *ih = Emu.GetIdManager().make(it); - ppu.Exec(); + it->Exec(); return CELL_OK; } @@ -140,11 +134,9 @@ s32 _sys_interrupt_thread_disestablish(u32 ih, vm::ptr r13) return CELL_ESRCH; } - PPUThread& ppu = static_cast(*handler->handler); - // TODO: wait for sys_interrupt_thread_eoi() and destroy interrupt thread - *r13 = ppu.GPR[13]; + *r13 = handler->thread->GPR[13]; return CELL_OK; } @@ -153,8 +145,9 @@ void sys_interrupt_thread_eoi(PPUThread& CPU) { sys_interrupt.Log("sys_interrupt_thread_eoi()"); - // TODO: maybe it should actually unwind the stack (ensure that all the automatic objects are finalized)? - CPU.GPR[1] = align(CPU.stack_addr + CPU.stack_size, 0x200) - 0x200; // supercrutch (just to hide error messages) + // TODO: maybe it should actually unwind the stack of PPU thread? + + CPU.GPR[1] = align(CPU.stack_addr + CPU.stack_size, 0x200) - 0x200; // supercrutch to avoid stack check CPU.FastStop(); } diff --git a/rpcs3/Emu/SysCalls/lv2/sys_interrupt.h b/rpcs3/Emu/SysCalls/lv2/sys_interrupt.h index 755f96d66f..2a34aa42fd 100644 --- a/rpcs3/Emu/SysCalls/lv2/sys_interrupt.h +++ b/rpcs3/Emu/SysCalls/lv2/sys_interrupt.h @@ -6,10 +6,10 @@ class PPUThread; struct lv2_int_handler_t { - std::shared_ptr handler; + const std::shared_ptr thread; - lv2_int_handler_t(const std::shared_ptr& handler) - : handler(handler) + lv2_int_handler_t(const std::shared_ptr& thread) + : thread(thread) { } }; diff --git a/rpcs3/Emu/SysCalls/lv2/sys_ppu_thread.cpp b/rpcs3/Emu/SysCalls/lv2/sys_ppu_thread.cpp index fbf26aae7b..dedf73d6aa 100644 --- a/rpcs3/Emu/SysCalls/lv2/sys_ppu_thread.cpp +++ b/rpcs3/Emu/SysCalls/lv2/sys_ppu_thread.cpp @@ -33,8 +33,8 @@ void _sys_ppu_thread_exit(PPUThread& CPU, u64 errorcode) void sys_ppu_thread_yield() { sys_ppu_thread.Log("sys_ppu_thread_yield()"); - // Note: Or do we actually want to yield? - std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack + + std::this_thread::yield(); } s32 sys_ppu_thread_join(PPUThread& CPU, u32 thread_id, vm::ptr vptr) diff --git a/rpcs3/Emu/SysCalls/lv2/sys_prx.cpp b/rpcs3/Emu/SysCalls/lv2/sys_prx.cpp index 0c199ebcb8..9f08e5d0b4 100644 --- a/rpcs3/Emu/SysCalls/lv2/sys_prx.cpp +++ b/rpcs3/Emu/SysCalls/lv2/sys_prx.cpp @@ -102,7 +102,7 @@ s32 prx_load_module(std::string path, u64 flags, vm::ptr img, { if (option) { - sys_spu.Todo("Unsupported SPU Thread options (0x%x)", option); + sys_spu.Error("Unsupported SPU Thread options (0x%x)", option); } - const auto spu = Emu.GetIdManager().make_ptr(name, spu_num, Memory.MainMem.AllocAlign(0x40000)); + const auto spu = Emu.GetIdManager().make_ptr(name, spu_num); spu->m_custom_task = task; @@ -120,9 +120,13 @@ u32 spu_thread_initialize(u32 group_id, u32 spu_num, vm::ptr img, } } - if (count >= group->num) + if (count > group->num) + { + throw EXCEPTION("Unexpected thread count (%d)", count); + } + + if (count == group->num) { - assert(count == group->num); group->state = SPU_THREAD_GROUP_STATUS_INITIALIZED; } @@ -152,7 +156,7 @@ s32 sys_spu_thread_initialize(vm::ptr thread, u32 group_id, u32 spu_num, vm return CELL_EBUSY; } - *thread = spu_thread_initialize(group_id, spu_num, img, attr->name ? std::string(attr->name.get_ptr(), attr->name_len) : "SPUThread", attr->option, arg->arg1, arg->arg2, arg->arg3, arg->arg4); + *thread = spu_thread_initialize(group_id, spu_num, img, attr->name ? std::string(attr->name.get_ptr(), attr->name_len) : "", attr->option, arg->arg1, arg->arg2, arg->arg3, arg->arg4); return CELL_OK; } @@ -171,7 +175,15 @@ s32 sys_spu_thread_set_argument(u32 id, vm::ptr arg) const auto group = thread->tg.lock(); - assert(thread->index < group->threads.size()); + if (!group) + { + throw EXCEPTION("Invalid SPU thread group"); + } + + if (thread->index >= group->threads.size() || group->threads[thread->index] != thread) + { + throw EXCEPTION("Unexpected SPU thread index (%d)", thread->index); + } group->args[thread->index].arg1 = arg->arg1; group->args[thread->index].arg2 = arg->arg2; @@ -245,10 +257,7 @@ s32 sys_spu_thread_group_destroy(u32 id) { if (t) { - auto& spu = static_cast(*t); - - Memory.MainMem.Free(spu.offset); - Emu.GetIdManager().remove(spu.GetId()); + Emu.GetIdManager().remove(t->GetId()); t.reset(); } @@ -287,24 +296,26 @@ s32 sys_spu_thread_group_start(u32 id) { if (t) { - auto& spu = static_cast(*t); + if (t->index >= group->threads.size()) + { + throw EXCEPTION("Unexpected SPU thread index (%d)", t->index); + } - assert(spu.index < group->threads.size()); - auto& args = group->args[spu.index]; - auto& image = group->images[spu.index]; + auto& args = group->args[t->index]; + auto& image = group->images[t->index]; // Copy SPU image: // TODO: use segment info - memcpy(vm::get_ptr(spu.offset), vm::get_ptr(image->addr), 256 * 1024); + std::memcpy(vm::get_ptr(t->offset), vm::get_ptr(image->addr), 256 * 1024); - spu.Run(); - spu.PC = image->entry_point; - spu.GPR[3] = u128::from64(0, args.arg1); - spu.GPR[4] = u128::from64(0, args.arg2); - spu.GPR[5] = u128::from64(0, args.arg3); - spu.GPR[6] = u128::from64(0, args.arg4); + t->PC = image->entry_point; + t->Run(); + t->GPR[3] = u128::from64(0, args.arg1); + t->GPR[4] = u128::from64(0, args.arg2); + t->GPR[5] = u128::from64(0, args.arg3); + t->GPR[6] = u128::from64(0, args.arg4); - spu.status.exchange(SPU_STATUS_RUNNING); + t->status.exchange(SPU_STATUS_RUNNING); } } @@ -314,10 +325,7 @@ s32 sys_spu_thread_group_start(u32 id) for (auto& t : group->threads) { - if (t) - { - t->Exec(); - } + if (t) t->Exec(); } return CELL_OK; @@ -367,10 +375,7 @@ s32 sys_spu_thread_group_suspend(u32 id) for (auto& t : group->threads) { - if (t) - { - t->Sleep(); // trigger m_state check - } + if (t) t->Sleep(); // trigger status check } return CELL_OK; @@ -403,7 +408,6 @@ s32 sys_spu_thread_group_resume(u32 id) else if (group->state == SPU_THREAD_GROUP_STATUS_WAITING_AND_SUSPENDED) { group->state = SPU_THREAD_GROUP_STATUS_WAITING; - return CELL_OK; // probably, nothing to do there } else { @@ -412,12 +416,11 @@ s32 sys_spu_thread_group_resume(u32 id) for (auto& t : group->threads) { - if (t) - { - t->Awake(); // trigger m_state check - } + if (t) t->Awake(); // untrigger status check } + group->cv.notify_all(); + return CELL_OK; } @@ -452,19 +455,15 @@ s32 sys_spu_thread_group_terminate(u32 id, s32 value) // seems the id can be either SPU Thread Group or SPU Thread const auto thread = Emu.GetIdManager().get(id); - auto group = Emu.GetIdManager().get(id); + const auto group = thread ? thread->tg.lock() : Emu.GetIdManager().get(id); if (!group && !thread) { return CELL_ESRCH; } - auto& spu = static_cast(*thread); - if (thread) { - group = spu.tg.lock(); - for (auto& t : group->threads) { // find primary (?) thread and compare it with the one specified @@ -482,26 +481,22 @@ s32 sys_spu_thread_group_terminate(u32 id, s32 value) } } - if ((group->state <= SPU_THREAD_GROUP_STATUS_INITIALIZED) || (group->state == SPU_THREAD_GROUP_STATUS_WAITING)) + if (group->state <= SPU_THREAD_GROUP_STATUS_INITIALIZED || + group->state == SPU_THREAD_GROUP_STATUS_WAITING || + group->state == SPU_THREAD_GROUP_STATUS_WAITING_AND_SUSPENDED) { return CELL_ESTAT; } for (auto& t : group->threads) { - if (t) - { - auto& spu = static_cast(*t); - - spu.status.exchange(SPU_STATUS_STOPPED); - spu.Stop(); - } + if (t) t->Stop(); } group->state = SPU_THREAD_GROUP_STATUS_INITIALIZED; group->exit_status = value; group->join_state |= SPU_TGJSF_TERMINATED; - group->join_cv.notify_one(); + group->cv.notify_one(); return CELL_OK; } @@ -538,9 +533,7 @@ s32 sys_spu_thread_group_join(u32 id, vm::ptr cause, vm::ptr status) { if (t) { - auto& spu = static_cast(*t); - - if ((spu.status.load() & SPU_STATUS_STOPPED_BY_STOP) == 0) + if ((t->status.load() & SPU_STATUS_STOPPED_BY_STOP) == 0) { stopped = false; break; @@ -559,7 +552,7 @@ s32 sys_spu_thread_group_join(u32 id, vm::ptr cause, vm::ptr status) return CELL_OK; } - group->join_cv.wait_for(lv2_lock, std::chrono::milliseconds(1)); + group->cv.wait_for(lv2_lock, std::chrono::milliseconds(1)); } switch (group->join_state & ~SPU_TGJSF_IS_JOINING) @@ -615,6 +608,11 @@ s32 sys_spu_thread_write_ls(u32 id, u32 address, u64 value, u32 type) const auto group = thread->tg.lock(); + if (!group) + { + throw EXCEPTION("Invalid SPU thread group"); + } + if ((group->state < SPU_THREAD_GROUP_STATUS_WAITING) || (group->state > SPU_THREAD_GROUP_STATUS_RUNNING)) { return CELL_ESTAT; @@ -652,6 +650,11 @@ s32 sys_spu_thread_read_ls(u32 id, u32 address, vm::ptr value, u32 type) const auto group = thread->tg.lock(); + if (!group) + { + throw EXCEPTION("Invalid SPU thread group"); + } + if ((group->state < SPU_THREAD_GROUP_STATUS_WAITING) || (group->state > SPU_THREAD_GROUP_STATUS_RUNNING)) { return CELL_ESTAT; @@ -684,6 +687,11 @@ s32 sys_spu_thread_write_spu_mb(u32 id, u32 value) const auto group = thread->tg.lock(); + if (!group) + { + throw EXCEPTION("Invalid SPU thread group"); + } + if ((group->state < SPU_THREAD_GROUP_STATUS_WAITING) || (group->state > SPU_THREAD_GROUP_STATUS_RUNNING)) { return CELL_ESTAT; @@ -755,11 +763,16 @@ s32 sys_spu_thread_write_snr(u32 id, u32 number, u32 value) const auto group = thread->tg.lock(); - if ((group->state < SPU_THREAD_GROUP_STATUS_WAITING) || (group->state > SPU_THREAD_GROUP_STATUS_RUNNING)) + if (!group) { - return CELL_ESTAT; + throw EXCEPTION("Invalid SPU thread group"); } + //if ((group->state < SPU_THREAD_GROUP_STATUS_WAITING) || (group->state > SPU_THREAD_GROUP_STATUS_RUNNING)) // ??? + //{ + // return CELL_ESTAT; + //} + thread->write_snr(number, value); return CELL_OK; @@ -1056,9 +1069,7 @@ s32 sys_spu_thread_group_connect_event_all_threads(u32 id, u32 eq, u64 req, vm:: { if (t) { - auto& spu = static_cast(*t); - - if (!spu.spup[port].expired()) + if (!t->spup[port].expired()) { found = false; break; @@ -1081,9 +1092,7 @@ s32 sys_spu_thread_group_connect_event_all_threads(u32 id, u32 eq, u64 req, vm:: { if (t) { - auto& spu = static_cast(*t); - - spu.spup[port] = queue; + t->spup[port] = queue; } } @@ -1114,9 +1123,7 @@ s32 sys_spu_thread_group_disconnect_event_all_threads(u32 id, u8 spup) { if (t) { - auto& spu = static_cast(*t); - - spu.spup[spup].reset(); + t->spup[spup].reset(); } } @@ -1172,16 +1179,14 @@ s32 sys_raw_spu_create_interrupt_tag(u32 id, u32 class_id, u32 hwthread, vm::ptr return CELL_EINVAL; } - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); - - auto& tag = class_id ? spu.int2 : spu.int0; + auto& tag = class_id ? thread->int2 : thread->int0; if (!tag.assigned.compare_and_swap_test(-1, 0)) { @@ -1202,16 +1207,16 @@ s32 sys_raw_spu_set_int_mask(u32 id, u32 class_id, u64 mask) return CELL_EINVAL; } - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); + auto& tag = class_id ? thread->int2 : thread->int0; - (class_id ? spu.int2 : spu.int0).mask.exchange(mask); + tag.mask.exchange(mask); return CELL_OK; } @@ -1225,16 +1230,16 @@ s32 sys_raw_spu_get_int_mask(u32 id, u32 class_id, vm::ptr mask) return CELL_EINVAL; } - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); + auto& tag = class_id ? thread->int2 : thread->int0; - *mask = (class_id ? spu.int2 : spu.int0).mask.load(); + *mask = tag.mask.load(); return CELL_OK; } @@ -1248,16 +1253,16 @@ s32 sys_raw_spu_set_int_stat(u32 id, u32 class_id, u64 stat) return CELL_EINVAL; } - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); + auto& tag = class_id ? thread->int2 : thread->int0; - (class_id ? spu.int2 : spu.int0).clear(stat); + tag.clear(stat); return CELL_OK; } @@ -1271,16 +1276,16 @@ s32 sys_raw_spu_get_int_stat(u32 id, u32 class_id, vm::ptr stat) return CELL_EINVAL; } - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); + auto& tag = class_id ? thread->int2 : thread->int0; - *stat = (class_id ? spu.int2 : spu.int0).stat.load(); + *stat = tag.stat.load(); return CELL_OK; } @@ -1289,16 +1294,14 @@ s32 sys_raw_spu_read_puint_mb(u32 id, vm::ptr value) { sys_spu.Log("sys_raw_spu_read_puint_mb(id=%d, value=*0x%x)", id, value); - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); - - *value = spu.ch_out_intr_mbox.pop_uncond(); + *value = thread->ch_out_intr_mbox.pop_uncond(); return CELL_OK; } @@ -1312,16 +1315,14 @@ s32 sys_raw_spu_set_spu_cfg(u32 id, u32 value) sys_spu.Fatal("sys_raw_spu_set_spu_cfg(id=%d, value=0x%x)", id, value); } - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); - - spu.snr_config = value; + thread->snr_config = value; return CELL_OK; } @@ -1330,16 +1331,14 @@ s32 sys_raw_spu_get_spu_cfg(u32 id, vm::ptr value) { sys_spu.Log("sys_raw_spu_get_spu_afg(id=%d, value=*0x%x)", id, value); - const auto t = Emu.GetCPU().GetRawSPUThread(id); + const auto thread = Emu.GetCPU().GetRawSPUThread(id); - if (!t) + if (!thread) { return CELL_ESRCH; } - auto& spu = static_cast(*t); - - *value = (u32)spu.snr_config; + *value = (u32)thread->snr_config; return CELL_OK; } diff --git a/rpcs3/Emu/SysCalls/lv2/sys_spu.h b/rpcs3/Emu/SysCalls/lv2/sys_spu.h index cf6efdc3d2..cd0f703f7c 100644 --- a/rpcs3/Emu/SysCalls/lv2/sys_spu.h +++ b/rpcs3/Emu/SysCalls/lv2/sys_spu.h @@ -141,6 +141,8 @@ enum : u32 SPU_TGJSF_GROUP_EXIT = (1 << 2), // set if SPU Thread Group is terminated by sys_spu_thread_group_exit }; +class SPUThread; + struct spu_group_t { const std::string name; @@ -148,16 +150,16 @@ struct spu_group_t const s32 type; // SPU Thread Group Type const u32 ct; // Memory Container Id - std::array, 256> threads; // SPU Threads + std::array, 256> threads; // SPU Threads std::array, 256> images; // SPU Images std::array args; // SPU Thread Arguments s32 prio; // SPU Thread Group Priority - u32 state; // SPU Thread Group State + volatile u32 state; // SPU Thread Group State s32 exit_status; // SPU Thread Group Exit Status std::atomic join_state; // flags used to detect exit cause - std::condition_variable join_cv; // used to signal waiting PPU thread + std::condition_variable cv; // used to signal waiting PPU thread std::weak_ptr ep_run; // port for SYS_SPU_THREAD_GROUP_EVENT_RUN events std::weak_ptr ep_exception; // TODO: SYS_SPU_THREAD_GROUP_EVENT_EXCEPTION @@ -206,7 +208,6 @@ struct spu_group_t } }; -class SPUThread; struct vfsStream; void LoadSpuImage(vfsStream& stream, u32& spu_ep, u32 addr); diff --git a/rpcs3/Emu/System.cpp b/rpcs3/Emu/System.cpp index 3fb8f29e2a..914c57b280 100644 --- a/rpcs3/Emu/System.cpp +++ b/rpcs3/Emu/System.cpp @@ -309,7 +309,7 @@ void Emulator::Resume() for (auto& t : GetCPU().GetAllThreads()) { - t->Awake(); // trigger status check + t->Awake(); // untrigger status check } SendDbgCommand(DID_RESUMED_EMU); @@ -327,9 +327,11 @@ void Emulator::Stop() m_status = Stopped; + LOG_NOTICE(GENERAL, "Stopping emulator..."); + for (auto& t : GetCPU().GetAllThreads()) { - t->Pause(); // trigger status check + t->Sleep(); // trigger status check } while (g_thread_count) @@ -337,7 +339,7 @@ void Emulator::Stop() std::this_thread::sleep_for(std::chrono::milliseconds(1)); } - LOG_NOTICE(HLE, "All threads stopped..."); + LOG_NOTICE(GENERAL, "All threads stopped..."); finalize_psv_modules(); clear_all_psv_objects(); diff --git a/rpcs3/Loader/ELF64.cpp b/rpcs3/Loader/ELF64.cpp index d26bb3f267..b38e3097d4 100644 --- a/rpcs3/Loader/ELF64.cpp +++ b/rpcs3/Loader/ELF64.cpp @@ -464,7 +464,7 @@ namespace loader if (!func) { - LOG_ERROR(LOADER, "Unimplemented function '%s' (0x%x)", SysCalls::GetFuncName(nid), addr); + LOG_ERROR(LOADER, "Unknown function '%s' (0x%x)", SysCalls::GetFuncName(nid), addr); index = add_ppu_func(ModuleFunc(nid, 0, module, nullptr, nullptr)); } @@ -695,7 +695,7 @@ namespace loader if (!func) { - LOG_ERROR(LOADER, "Unimplemented function '%s' in '%s' module (0x%x)", SysCalls::GetFuncName(nid), module_name, addr); + LOG_ERROR(LOADER, "Unknown function '%s' in '%s' module (0x%x)", SysCalls::GetFuncName(nid), module_name, addr); index = add_ppu_func(ModuleFunc(nid, 0, module, nullptr, nullptr)); }