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Code Issues Releases Wiki Activity

ARMv7: more opcodes

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This commit is contained in:
Nekotekina 2014-10-29 18:30:35 +03:00
parent bf6415accd
commit 94213bb398
6 changed files with 331 additions and 38 deletions
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3
rpcs3/Emu/ARMv7/ARMv7Decoder.h
View File

@ -18,12 +18,13 @@ public:
const u32 code0 = vm::psv::read16(address & ~1); const u32 code0 = vm::psv::read16(address & ~1);
const u32 code1 = vm::psv::read16(address + 2 & ~1); const u32 code1 = vm::psv::read16(address + 2 & ~1);
const u32 data = code0 << 16 | code1; const u32 data = code0 << 16 | code1;
const u32 arg = address & 1 ? data : code1 << 16 | code0;
for (auto& opcode : ARMv7_opcode_table) for (auto& opcode : ARMv7_opcode_table)
{ {
if ((opcode.type >= A1) == ((address & 1) == 0) && (data & opcode.mask) == opcode.code) if ((opcode.type >= A1) == ((address & 1) == 0) && (data & opcode.mask) == opcode.code)
{ {
(m_op.*opcode.func)(opcode.length == 2 ? code0 : data, opcode.type); (m_op.*opcode.func)(opcode.length == 2 ? code0 : arg, opcode.type);
return opcode.length; return opcode.length;
} }
} }

64
rpcs3/Emu/ARMv7/ARMv7DisAsm.cpp
View File

@ -65,6 +65,61 @@ void ARMv7DisAsm::BLX(const u32 data, const ARMv7_encoding type)
//Write(fmt::Format("bl 0x%x", DisAsmBranchTarget(imm) + intstr_size)); //Write(fmt::Format("bl 0x%x", DisAsmBranchTarget(imm) + intstr_size));
} }
void ARMv7DisAsm::ADC_IMM(const u32 data, const ARMv7_encoding type)
{
Write("ADC...");
}
void ARMv7DisAsm::ADC_REG(const u32 data, const ARMv7_encoding type)
{
Write("ADC...");
}
void ARMv7DisAsm::ADC_RSR(const u32 data, const ARMv7_encoding type)
{
Write("ADC...");
}
void ARMv7DisAsm::ADD_IMM(const u32 data, const ARMv7_encoding type)
{
Write("ADD...");
}
void ARMv7DisAsm::ADD_REG(const u32 data, const ARMv7_encoding type)
{
Write("ADD...");
}
void ARMv7DisAsm::ADD_RSR(const u32 data, const ARMv7_encoding type)
{
Write("ADD...");
}
void ARMv7DisAsm::ADD_SPI(const u32 data, const ARMv7_encoding type)
{
Write("ADD SP...");
}
void ARMv7DisAsm::ADD_SPR(const u32 data, const ARMv7_encoding type)
{
Write("ADD SP...");
}
void ARMv7DisAsm::MOV_IMM(const u32 data, const ARMv7_encoding type)
{
Write("MOV...");
}
void ARMv7DisAsm::MOV_REG(const u32 data, const ARMv7_encoding type)
{
Write("MOV...");
}
void ARMv7DisAsm::MOVT(const u32 data, const ARMv7_encoding type)
{
Write("MOVT...");
}
void ARMv7DisAsm::SUB_IMM(const u32 data, const ARMv7_encoding type) void ARMv7DisAsm::SUB_IMM(const u32 data, const ARMv7_encoding type)
{ {
Write("SUB..."); Write("SUB...");
@ -90,3 +145,12 @@ void ARMv7DisAsm::SUB_SPR(const u32 data, const ARMv7_encoding type)
Write("SUB SP..."); Write("SUB SP...");
} }
void ARMv7DisAsm::STR_IMM(const u32 data, const ARMv7_encoding type)
{
Write("STR...");
}
void ARMv7DisAsm::STR_REG(const u32 data, const ARMv7_encoding type)
{
Write("STR...");
}

47
rpcs3/Emu/ARMv7/ARMv7DisAsm.h
View File

@ -45,23 +45,40 @@ protected:
return regs_str; return regs_str;
} }
void UNK(const u32 data); virtual void UNK(const u32 data);
void NULL_OP(const u32 data, const ARMv7_encoding type); virtual void NULL_OP(const u32 data, const ARMv7_encoding type);
void NOP(const u32 data, const ARMv7_encoding type); virtual void NOP(const u32 data, const ARMv7_encoding type);
void PUSH(const u32 data, const ARMv7_encoding type); virtual void PUSH(const u32 data, const ARMv7_encoding type);
void POP(const u32 data, const ARMv7_encoding type); virtual void POP(const u32 data, const ARMv7_encoding type);
void B(const u32 data, const ARMv7_encoding type); virtual void B(const u32 data, const ARMv7_encoding type);
void CBZ(const u32 data, const ARMv7_encoding type); virtual void CBZ(const u32 data, const ARMv7_encoding type);
void CBNZ(const u32 data, const ARMv7_encoding type); virtual void CBNZ(const u32 data, const ARMv7_encoding type);
void BL(const u32 data, const ARMv7_encoding type); virtual void BL(const u32 data, const ARMv7_encoding type);
void BLX(const u32 data, const ARMv7_encoding type); virtual void BLX(const u32 data, const ARMv7_encoding type);
void SUB_IMM(const u32 data, const ARMv7_encoding type); virtual void ADC_IMM(const u32 data, const ARMv7_encoding type);
void SUB_REG(const u32 data, const ARMv7_encoding type); virtual void ADC_REG(const u32 data, const ARMv7_encoding type);
void SUB_RSR(const u32 data, const ARMv7_encoding type); virtual void ADC_RSR(const u32 data, const ARMv7_encoding type);
void SUB_SPI(const u32 data, const ARMv7_encoding type);
void SUB_SPR(const u32 data, const ARMv7_encoding type); virtual void ADD_IMM(const u32 data, const ARMv7_encoding type);
virtual void ADD_REG(const u32 data, const ARMv7_encoding type);
virtual void ADD_RSR(const u32 data, const ARMv7_encoding type);
virtual void ADD_SPI(const u32 data, const ARMv7_encoding type);
virtual void ADD_SPR(const u32 data, const ARMv7_encoding type);
virtual void MOV_IMM(const u32 data, const ARMv7_encoding type);
virtual void MOV_REG(const u32 data, const ARMv7_encoding type);
virtual void MOVT(const u32 data, const ARMv7_encoding type);
virtual void SUB_IMM(const u32 data, const ARMv7_encoding type);
virtual void SUB_REG(const u32 data, const ARMv7_encoding type);
virtual void SUB_RSR(const u32 data, const ARMv7_encoding type);
virtual void SUB_SPI(const u32 data, const ARMv7_encoding type);
virtual void SUB_SPR(const u32 data, const ARMv7_encoding type);
virtual void STR_IMM(const u32 data, const ARMv7_encoding type);
virtual void STR_REG(const u32 data, const ARMv7_encoding type);
}; };

123
rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp
View File

@ -260,19 +260,116 @@ void ARMv7Interpreter::BLX(const u32 data, const ARMv7_encoding type)
CPU.SetBranch(target); CPU.SetBranch(target);
} }
void ARMv7Interpreter::ADC_IMM(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADC_REG(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADC_RSR(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADD_IMM(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADD_REG(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADD_RSR(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADD_SPI(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::ADD_SPR(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::MOV_IMM(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::MOV_REG(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::MOVT(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::SUB_IMM(const u32 data, const ARMv7_encoding type) void ARMv7Interpreter::SUB_IMM(const u32 data, const ARMv7_encoding type)
{ {
switch (type)
{
default: throw __FUNCTION__;
}
} }
void ARMv7Interpreter::SUB_REG(const u32 data, const ARMv7_encoding type) void ARMv7Interpreter::SUB_REG(const u32 data, const ARMv7_encoding type)
{ {
switch (type)
{
default: throw __FUNCTION__;
}
} }
void ARMv7Interpreter::SUB_RSR(const u32 data, const ARMv7_encoding type) void ARMv7Interpreter::SUB_RSR(const u32 data, const ARMv7_encoding type)
{ {
switch (type)
{
default: throw __FUNCTION__;
}
} }
void ARMv7Interpreter::SUB_SPI(const u32 data, const ARMv7_encoding type) void ARMv7Interpreter::SUB_SPI(const u32 data, const ARMv7_encoding type)
@ -286,6 +383,24 @@ void ARMv7Interpreter::SUB_SPI(const u32 data, const ARMv7_encoding type)
void ARMv7Interpreter::SUB_SPR(const u32 data, const ARMv7_encoding type) void ARMv7Interpreter::SUB_SPR(const u32 data, const ARMv7_encoding type)
{ {
switch (type)
{
default: throw __FUNCTION__;
}
} }
void ARMv7Interpreter::STR_IMM(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}
void ARMv7Interpreter::STR_REG(const u32 data, const ARMv7_encoding type)
{
switch (type)
{
default: throw __FUNCTION__;
}
}

47
rpcs3/Emu/ARMv7/ARMv7Interpreter.h
View File

@ -258,23 +258,40 @@ public:
} }
protected: protected:
void UNK(const u32 data); virtual void UNK(const u32 data);
void NULL_OP(const u32 data, const ARMv7_encoding type); virtual void NULL_OP(const u32 data, const ARMv7_encoding type);
void NOP(const u32 data, const ARMv7_encoding type); virtual void NOP(const u32 data, const ARMv7_encoding type);
void PUSH(const u32 data, const ARMv7_encoding type); virtual void PUSH(const u32 data, const ARMv7_encoding type);
void POP(const u32 data, const ARMv7_encoding type); virtual void POP(const u32 data, const ARMv7_encoding type);
void B(const u32 data, const ARMv7_encoding type); virtual void B(const u32 data, const ARMv7_encoding type);
void CBZ(const u32 data, const ARMv7_encoding type); virtual void CBZ(const u32 data, const ARMv7_encoding type);
void CBNZ(const u32 data, const ARMv7_encoding type); virtual void CBNZ(const u32 data, const ARMv7_encoding type);
void BL(const u32 data, const ARMv7_encoding type); virtual void BL(const u32 data, const ARMv7_encoding type);
void BLX(const u32 data, const ARMv7_encoding type); virtual void BLX(const u32 data, const ARMv7_encoding type);
void SUB_IMM(const u32 data, const ARMv7_encoding type); virtual void ADC_IMM(const u32 data, const ARMv7_encoding type);
void SUB_REG(const u32 data, const ARMv7_encoding type); virtual void ADC_REG(const u32 data, const ARMv7_encoding type);
void SUB_RSR(const u32 data, const ARMv7_encoding type); virtual void ADC_RSR(const u32 data, const ARMv7_encoding type);
void SUB_SPI(const u32 data, const ARMv7_encoding type);
void SUB_SPR(const u32 data, const ARMv7_encoding type); virtual void ADD_IMM(const u32 data, const ARMv7_encoding type);
virtual void ADD_REG(const u32 data, const ARMv7_encoding type);
virtual void ADD_RSR(const u32 data, const ARMv7_encoding type);
virtual void ADD_SPI(const u32 data, const ARMv7_encoding type);
virtual void ADD_SPR(const u32 data, const ARMv7_encoding type);
virtual void MOV_IMM(const u32 data, const ARMv7_encoding type);
virtual void MOV_REG(const u32 data, const ARMv7_encoding type);
virtual void MOVT(const u32 data, const ARMv7_encoding type);
virtual void SUB_IMM(const u32 data, const ARMv7_encoding type);
virtual void SUB_REG(const u32 data, const ARMv7_encoding type);
virtual void SUB_RSR(const u32 data, const ARMv7_encoding type);
virtual void SUB_SPI(const u32 data, const ARMv7_encoding type);
virtual void SUB_SPR(const u32 data, const ARMv7_encoding type);
virtual void STR_IMM(const u32 data, const ARMv7_encoding type);
virtual void STR_REG(const u32 data, const ARMv7_encoding type);
}; };

85
rpcs3/Emu/ARMv7/ARMv7Opcodes.h
View File

@ -59,11 +59,28 @@ public:
virtual void BL(const u32 data, const ARMv7_encoding type) = 0; virtual void BL(const u32 data, const ARMv7_encoding type) = 0;
virtual void BLX(const u32 data, const ARMv7_encoding type) = 0; virtual void BLX(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADC_IMM(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADC_REG(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADC_RSR(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADD_IMM(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADD_REG(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADD_RSR(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADD_SPI(const u32 data, const ARMv7_encoding type) = 0;
virtual void ADD_SPR(const u32 data, const ARMv7_encoding type) = 0;
virtual void MOV_IMM(const u32 data, const ARMv7_encoding type) = 0;
virtual void MOV_REG(const u32 data, const ARMv7_encoding type) = 0;
virtual void MOVT(const u32 data, const ARMv7_encoding type) = 0;
virtual void SUB_IMM(const u32 data, const ARMv7_encoding type) = 0; virtual void SUB_IMM(const u32 data, const ARMv7_encoding type) = 0;
virtual void SUB_REG(const u32 data, const ARMv7_encoding type) = 0; virtual void SUB_REG(const u32 data, const ARMv7_encoding type) = 0;
virtual void SUB_RSR(const u32 data, const ARMv7_encoding type) = 0; virtual void SUB_RSR(const u32 data, const ARMv7_encoding type) = 0;
virtual void SUB_SPI(const u32 data, const ARMv7_encoding type) = 0; virtual void SUB_SPI(const u32 data, const ARMv7_encoding type) = 0;
virtual void SUB_SPR(const u32 data, const ARMv7_encoding type) = 0; virtual void SUB_SPR(const u32 data, const ARMv7_encoding type) = 0;
virtual void STR_IMM(const u32 data, const ARMv7_encoding type) = 0;
virtual void STR_REG(const u32 data, const ARMv7_encoding type) = 0;
}; };
struct ARMv7_opcode_t struct ARMv7_opcode_t
@ -71,15 +88,15 @@ struct ARMv7_opcode_t
u32 mask; u32 mask;
u32 code; u32 code;
u32 length; // 2 or 4 u32 length; // 2 or 4
char* name; const char* name;
ARMv7_encoding type; ARMv7_encoding type;
void (ARMv7Opcodes::*func)(const u32 data, const ARMv7_encoding type); void (ARMv7Opcodes::*func)(const u32 data, const ARMv7_encoding type);
}; };
// single 16-bit value // single 16-bit value
#define ARMv7_OP2(mask, code, type, name) { (mask) << 16, (code) << 16, 2, #name, type, &ARMv7Opcodes::name } #define ARMv7_OP2(mask, code, type, name) { (u32)((mask) << 16), (u32)((code) << 16), 2, #name "_" #type, type, &ARMv7Opcodes::name }
// two 16-bit values // two 16-bit values
#define ARMv7_OP4(mask0, mask1, code0, code1, type, name) { ((mask0) << 16) | (mask1), ((code0) << 16) | (code1), 4, #name, type, &ARMv7Opcodes::name } #define ARMv7_OP4(mask0, mask1, code0, code1, type, name) { (u32)((mask0) << 16) | (mask1), (u32)((code0) << 16) | (code1), 4, #name "_" #type, type, &ARMv7Opcodes::name }
static const ARMv7_opcode_t ARMv7_opcode_table[] = static const ARMv7_opcode_t ARMv7_opcode_table[] =
{ {
@ -111,7 +128,69 @@ static const ARMv7_opcode_t ARMv7_opcode_table[] =
ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff30, A1, BLX), ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff30, A1, BLX),
ARMv7_OP4(0xfe00, 0x0000, 0xfa00, 0x0000, A2, BLX), ARMv7_OP4(0xfe00, 0x0000, 0xfa00, 0x0000, A2, BLX),
ARMv7_OP4(0xfbe0, 0x8000, 0xf140, 0x0000, T1, ADC_IMM),
ARMv7_OP4(0x0fe0, 0x0000, 0x02a0, 0x0000, A1, ADC_IMM),
ARMv7_OP2(0xffc0, 0x4040, T1, ADC_REG),
ARMv7_OP4(0xffe0, 0x8000, 0xeb40, 0x0000, T2, ADC_REG),
ARMv7_OP4(0x0fe0, 0x0010, 0x00a0, 0x0000, A1, ADC_REG),
ARMv7_OP4(0x0fe0, 0x0090, 0x00a0, 0x0010, A1, ADC_RSR),
ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM),
ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM),
ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM),
ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG),
ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG),
ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG),
ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
ARMv7_OP2(0xf800, 0x2000, T1, MOV_IMM),
ARMv7_OP4(0xfbef, 0x8000, 0xf04f, 0x0000, T2, MOV_IMM),
ARMv7_OP4(0xfbf0, 0x8000, 0xf240, 0x0000, T3, MOV_IMM),
ARMv7_OP4(0x0fef, 0x0000, 0x03a0, 0x0000, A1, MOV_IMM),
ARMv7_OP4(0x0ff0, 0x0000, 0x0300, 0x0000, A2, MOV_IMM),
ARMv7_OP2(0xff00, 0x4600, T1, MOV_REG),
ARMv7_OP2(0xffc0, 0x0000, T2, MOV_REG),
ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0000, T3, MOV_REG),
ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0000, A1, MOV_REG),
ARMv7_OP4(0xfbf0, 0x8000, 0xf2c0, 0x0000, T1, MOVT),
ARMv7_OP4(0x0ff0, 0x0000, 0x0340, 0x0000, A1, MOVT),
ARMv7_OP2(0xfe00, 0x1e00, T1, SUB_IMM),
ARMv7_OP2(0xf800, 0x3800, T2, SUB_IMM),
ARMv7_OP4(0xfbe0, 0x8000, 0xf1a0, 0x0000, T3, SUB_IMM),
ARMv7_OP4(0xfbf0, 0x8000, 0xf2a0, 0x0000, T4, SUB_IMM),
ARMv7_OP4(0x0fe0, 0x0000, 0x0240, 0x0000, A1, SUB_IMM),
ARMv7_OP2(0xfe00, 0x1a00, T1, SUB_REG),
ARMv7_OP4(0xffe0, 0x8000, 0xeba0, 0x0000, T2, SUB_REG),
ARMv7_OP4(0x0fe0, 0x0010, 0x0040, 0x0000, A1, SUB_REG),
ARMv7_OP4(0x0fe0, 0x0090, 0x0040, 0x0010, A1, SUB_RSR),
ARMv7_OP2(0xff80, 0xb080, T1, SUB_SPI), ARMv7_OP2(0xff80, 0xb080, T1, SUB_SPI),
ARMv7_OP4(0xfbef, 0x8000, 0xf1ad, 0x0000, T2, SUB_SPI),
ARMv7_OP4(0xfbff, 0x8000, 0xf2ad, 0x0000, T3, SUB_SPI),
ARMv7_OP4(0x0fef, 0x0000, 0x024d, 0x0000, A1, SUB_SPI),
ARMv7_OP4(0xffef, 0x8000, 0xebad, 0x0000, T1, SUB_SPR),
ARMv7_OP4(0x0fef, 0x0010, 0x004d, 0x0000, A1, SUB_SPR),
ARMv7_OP2(0xf800, 0x6000, T1, STR_IMM),
ARMv7_OP2(0xf800, 0x9000, T2, STR_IMM),
ARMv7_OP4(0xfff0, 0x0000, 0xf8c0, 0x0000, T3, STR_IMM),
ARMv7_OP4(0xfff0, 0x0800, 0xf840, 0x0800, T4, STR_IMM),
ARMv7_OP4(0x0e50, 0x0000, 0x0400, 0x0000, A1, STR_IMM),
ARMv7_OP2(0xfe00, 0x5000, T1, STR_REG),
ARMv7_OP4(0xfff0, 0x0fc0, 0xf840, 0x0000, T2, STR_REG),
ARMv7_OP4(0x0e50, 0x0010, 0x0600, 0x0000, A1, STR_REG),
}; };
#undef ARMv7_OP #undef ARMv7_OP