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https://github.com/RPCS3/rpcs3.git
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PPU LLVM improvements
Removed interpreter dependencies Reciprocal instructions improved
This commit is contained in:
Nekotekina
parent
87e38118a5
commit
94da0dbd4d
@ -12,6 +12,7 @@ enum class ppu_attr : u32
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no_return,
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no_size,
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uses_r0,
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entry_point,
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};
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// PPU Function Information
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@ -853,7 +853,7 @@ std::shared_ptr<lv2_prx_t> ppu_load_prx(const ppu_prx_object& elf)
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case 10:
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{
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const u32 value = vm::_ref<ppu_bf_t<u32, 6, 24>>(raddr) = static_cast<u32>(rdata - raddr) >> 2;
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const u32 value = vm::_ref<ppu_bf_t<be_t<u32>, 6, 24>>(raddr) = static_cast<u32>(rdata - raddr) >> 2;
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LOG_WARNING(LOADER, "**** RELOCATION(10): 0x%x <- 0x%06x (0x%llx)", raddr, value, rdata);
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break;
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}
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@ -867,7 +867,7 @@ std::shared_ptr<lv2_prx_t> ppu_load_prx(const ppu_prx_object& elf)
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case 57:
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{
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const u16 value = vm::_ref<ppu_bf_t<u16, 0, 14>>(raddr) = static_cast<u16>(rdata) >> 2;
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const u16 value = vm::_ref<ppu_bf_t<be_t<u16>, 0, 14>>(raddr) = static_cast<u16>(rdata) >> 2;
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LOG_WARNING(LOADER, "**** RELOCATION(57): 0x%x <- 0x%04x (0x%llx)", raddr, value, rdata);
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break;
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}
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@ -1325,12 +1325,13 @@ void ppu_load_exec(const ppu_exec_object& elf)
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*entry++ = MR(r12, r19);
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// Branch to initialization
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make_branch(entry, static_cast<u32>(elf.header.e_entry), true);
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make_branch(entry, static_cast<u32>(elf.header.e_entry), false);
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// Register entry function (addr, size)
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ppu_function entry_func;
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entry_func.addr = entry.addr() & -0x1000;
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entry_func.size = entry.addr() & 0xfff;
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entry_func.attr += ppu_attr::entry_point;
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exec_set.emplace_back(entry_func);
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// Initialize recompiler
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@ -397,28 +397,6 @@ static void ppu_trace(u64 addr)
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LOG_NOTICE(PPU, "Trace: 0x%llx", addr);
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}
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static __m128 sse_rcp_ps(__m128 A)
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{
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return _mm_rcp_ps(A);
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}
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static __m128 sse_rsqrt_ps(__m128 A)
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{
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return _mm_rsqrt_ps(A);
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}
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static float sse_rcp_ss(float A)
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{
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_mm_store_ss(&A, _mm_rcp_ss(_mm_load_ss(&A)));
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return A;
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}
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static float sse_rsqrt_ss(float A)
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{
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_mm_store_ss(&A, _mm_rsqrt_ss(_mm_load_ss(&A)));
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return A;
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}
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static u32 ppu_lwarx(u32 addr)
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{
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be_t<u32> reg_value;
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@ -456,24 +434,6 @@ static bool adde_carry(u64 a, u64 b, bool c)
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#endif
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}
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// Interpreter call for simple vector instructions
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static __m128i ppu_vec3op(decltype(&ppu_interpreter::UNK) func, __m128i _a, __m128i _b, __m128i _c)
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{
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PPUThread& ppu = static_cast<PPUThread&>(*get_current_cpu_thread());
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ppu.VR[21].vi = _a;
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ppu.VR[22].vi = _b;
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ppu.VR[23].vi = _c;
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ppu_opcode_t op{};
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op.vd = 20;
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op.va = 21;
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op.vb = 22;
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op.vc = 23;
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func(ppu, op);
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return ppu.VR[20].vi;
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}
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extern void ppu_initialize(const std::string& name, const std::vector<ppu_function>& funcs, u32 entry)
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{
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if (g_cfg_ppu_decoder.get() != ppu_decoder_type::llvm || funcs.empty())
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@ -504,21 +464,16 @@ extern void ppu_initialize(const std::string& name, const std::vector<ppu_functi
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{ "__ldarx", (u64)&ppu_ldarx },
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{ "__stwcx", (u64)&ppu_stwcx },
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{ "__stdcx", (u64)&ppu_stdcx },
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{ "__vec3op", (u64)&ppu_vec3op },
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{ "__adde_get_ca", (u64)&adde_carry },
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{ "__vexptefp", (u64)&sse_exp2_ps },
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{ "__vlogefp", (u64)&sse_log2_ps },
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{ "__vperm", (u64)&sse_altivec_vperm },
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{ "__vrefp", (u64)&sse_rcp_ps },
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{ "__vrsqrtefp", (u64)&sse_rsqrt_ps },
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{ "__lvsl", (u64)&sse_altivec_lvsl },
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{ "__lvsr", (u64)&sse_altivec_lvsr },
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{ "__lvlx", (u64)&sse_cellbe_lvlx },
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{ "__lvrx", (u64)&sse_cellbe_lvrx },
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{ "__stvlx", (u64)&sse_cellbe_stvlx },
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{ "__stvrx", (u64)&sse_cellbe_stvrx },
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{ "__fre", (u64)&sse_rcp_ss },
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{ "__frsqrte", (u64)&sse_rsqrt_ss },
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};
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#ifdef LLVM_AVAILABLE
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@ -577,7 +532,7 @@ extern void ppu_initialize(const std::string& name, const std::vector<ppu_functi
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pm.add(createAggressiveDCEPass());
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pm.add(createCFGSimplificationPass());
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//pm.add(createLintPass()); // Check
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// Translate functions
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for (const auto& info : funcs)
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{
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@ -10,7 +10,7 @@ using namespace llvm;
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const ppu_decoder<PPUTranslator> s_ppu_decoder;
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/* Interpreter Call Macro */
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/* Interpreter Call Macro (unused) */
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#define VEC3OP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__vec3op",\
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m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
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@ -1081,13 +1081,15 @@ void PPUTranslator::VMSUMSHM(ppu_opcode_t op)
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void PPUTranslator::VMSUMSHS(ppu_opcode_t op)
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{
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// TODO (very rare)
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/**/ return_ VEC3OP(VMSUMSHS);
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//const auto a = GetVr(op.va, VrType::vi16);
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//const auto b = GetVr(op.vb, VrType::vi16);
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//const auto c = GetVr(op.vc, VrType::vi32);
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//SetVr(op.vd, Call(GetType<u32[4]>(), m_pure_attr, "__vmsumshs", a, b, c));
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//SetSat(Call(GetType<bool>(), m_pure_attr, "__vmsumshs_get_sat", a, b, c));
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const auto ab = SExt(GetVrs(VrType::vi16, op.va, op.vb));
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const auto p = m_ir->CreateMul(ab[0], ab[1]);
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const auto c = GetVr(op.vc, VrType::vi32);
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const auto e0 = Shuffle(p, nullptr, { 0, 2, 4, 6 });
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const auto e1 = Shuffle(p, nullptr, { 1, 3, 5, 7 });
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const auto result = Add({ SExt(c), SExt(e0), SExt(e1) });
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const auto saturated = SaturateSigned(result, -0x80000000ll, 0x7fffffff);
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SetVr(op.vd, saturated.first);
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SetSat(IsNotZero(saturated.second));
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}
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void PPUTranslator::VMSUMUBM(ppu_opcode_t op)
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@ -1114,13 +1116,15 @@ void PPUTranslator::VMSUMUHM(ppu_opcode_t op)
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void PPUTranslator::VMSUMUHS(ppu_opcode_t op)
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{
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// TODO (very rare)
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/**/ return_ VEC3OP(VMSUMUHS);
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//const auto a = GetVr(op.va, VrType::vi16);
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//const auto b = GetVr(op.vb, VrType::vi16);
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//const auto c = GetVr(op.vc, VrType::vi32);
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//SetVr(op.vd, Call(GetType<u32[4]>(), m_pure_attr, "__vmsumuhs", a, b, c));
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//SetSat(Call(GetType<bool>(), m_pure_attr, "__vmsumuhs_get_sat", a, b, c));
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const auto ab = ZExt(GetVrs(VrType::vi16, op.va, op.vb));
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const auto p = m_ir->CreateMul(ab[0], ab[1]);
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const auto c = GetVr(op.vc, VrType::vi32);
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const auto e0 = Shuffle(p, nullptr, { 0, 2, 4, 6 });
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const auto e1 = Shuffle(p, nullptr, { 1, 3, 5, 7 });
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const auto result = Add({ ZExt(c), ZExt(e0), ZExt(e1) });
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const auto saturated = Saturate(result, ICmpInst::ICMP_UGT, m_ir->getInt64(0xffffffff));
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SetVr(op.vd, saturated.first);
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SetSat(IsNotZero(saturated.second));
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}
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void PPUTranslator::VMULESB(ppu_opcode_t op)
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@ -1275,7 +1279,10 @@ void PPUTranslator::VPKUWUS(ppu_opcode_t op)
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void PPUTranslator::VREFP(ppu_opcode_t op)
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{
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SetVr(op.vd, Call(GetType<f32[4]>(), m_pure_attr, "__vrefp", GetVr(op.vb, VrType::vf)));
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const auto result = m_ir->CreateFDiv(ConstantVector::getSplat(4, ConstantFP::get(GetType<f32>(), 1.0)), GetVr(op.vb, VrType::vf));
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FastMathFlags x; x.setAllowReciprocal();
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cast<Instruction>(result)->setFastMathFlags(x);
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SetVr(op.vd, result);
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}
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void PPUTranslator::VRFIM(ppu_opcode_t op)
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@ -1318,7 +1325,10 @@ void PPUTranslator::VRLW(ppu_opcode_t op)
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void PPUTranslator::VRSQRTEFP(ppu_opcode_t op)
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{
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SetVr(op.vd, Call(GetType<f32[4]>(), m_pure_attr, "__vrsqrtefp", GetVr(op.vb, VrType::vf)));
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const auto result = m_ir->CreateFDiv(ConstantVector::getSplat(4, ConstantFP::get(GetType<f32>(), 1.0)), Call(GetType<f32[4]>(), "llvm.sqrt.v4f32", GetVr(op.vb, VrType::vf)));
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FastMathFlags x; x.setAllowReciprocal();
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cast<Instruction>(result)->setFastMathFlags(x);
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SetVr(op.vd, result);
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}
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void PPUTranslator::VSEL(ppu_opcode_t op)
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@ -1551,7 +1561,6 @@ void PPUTranslator::VSUBUWS(ppu_opcode_t op)
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void PPUTranslator::VSUMSWS(ppu_opcode_t op)
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{
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// TODO (rare)
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const auto ab = GetVrs(VrType::vi32, op.va, op.vb);
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const auto a = SExt(ab[0]);
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const auto b = SExt(m_ir->CreateExtractElement(ab[1], m_ir->getInt32(m_is_be ? 3 : 0)));
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@ -1566,7 +1575,6 @@ void PPUTranslator::VSUMSWS(ppu_opcode_t op)
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void PPUTranslator::VSUM2SWS(ppu_opcode_t op)
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{
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// TODO (rare)
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const auto ab = GetVrs(VrType::vi32, op.va, op.vb);
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const auto b = SExt(Shuffle(ab[1], nullptr, { 1, 3 }));
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const auto a = SExt(ab[0]);
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@ -1579,27 +1587,32 @@ void PPUTranslator::VSUM2SWS(ppu_opcode_t op)
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void PPUTranslator::VSUM4SBS(ppu_opcode_t op)
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{
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// TODO (very rare)
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/**/ return_ VEC2OP(VSUM4SBS);
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//const auto a = GetVr(op.va, VrType::vi8);
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//const auto b = GetVr(op.vb, VrType::vi32);
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//SetVr(op.vd, Call(GetType<u32[4]>(), m_pure_attr, "__vsum4sbs", a, b));
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//SetSat(Call(GetType<bool>(), m_pure_attr, "__vsum4sbs_get_sat", a, b));
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const auto a = SExt(GetVr(op.va, VrType::vi8), GetType<s32[16]>());
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const auto b = GetVr(op.vb, VrType::vi32);
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const auto e0 = Shuffle(a, nullptr, { 0, 4, 8, 12 });
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const auto e1 = Shuffle(a, nullptr, { 1, 5, 9, 13 });
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const auto e2 = Shuffle(a, nullptr, { 2, 6, 10, 14 });
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const auto e3 = Shuffle(a, nullptr, { 3, 7, 11, 15 });
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const auto result = m_ir->CreateAdd(SExt(b), SExt(Add({ e0, e1, e2, e3 }))); // Summ, (e0+e1+e2+e3) is small
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const auto saturated = SaturateSigned(result, -0x80000000ll, 0x7fffffff);
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SetVr(op.vd, saturated.first);
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SetSat(IsNotZero(saturated.second));
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}
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void PPUTranslator::VSUM4SHS(ppu_opcode_t op)
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{
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// TODO (very rare)
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/**/ return_ VEC2OP(VSUM4SHS);
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//const auto a = GetVr(op.va, VrType::vi16);
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//const auto b = GetVr(op.vb, VrType::vi32);
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//SetVr(op.vd, Call(GetType<u32[4]>(), m_pure_attr, "__vsum4shs", a, b));
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//SetSat(Call(GetType<bool>(), m_pure_attr, "__vsum4shs_get_sat", a, b));
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const auto a = SExt(GetVr(op.va, VrType::vi16));
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const auto b = GetVr(op.vb, VrType::vi32);
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const auto e0 = Shuffle(a, nullptr, { 0, 2, 4, 6 });
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const auto e1 = Shuffle(a, nullptr, { 1, 3, 5, 7 });
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const auto result = m_ir->CreateAdd(SExt(b), SExt(Add({ e0, e1 }))); // Summ, (e0+e1) is small
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const auto saturated = SaturateSigned(result, -0x80000000ll, 0x7fffffff);
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SetVr(op.vd, saturated.first);
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SetSat(IsNotZero(saturated.second));
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}
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void PPUTranslator::VSUM4UBS(ppu_opcode_t op)
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{
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// TODO
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const auto a = ZExt(GetVr(op.va, VrType::vi8), GetType<u32[16]>());
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const auto b = GetVr(op.vb, VrType::vi32);
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const auto e0 = Shuffle(a, nullptr, { 0, 4, 8, 12 });
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@ -3435,7 +3448,9 @@ void PPUTranslator::FSQRTS(ppu_opcode_t op)
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void PPUTranslator::FRES(ppu_opcode_t op)
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{
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const auto b = GetFpr(op.frb, 32);
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const auto result = Call(GetType<f32>(), m_pure_attr, "__fre", b);
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const auto result = m_ir->CreateFDiv(ConstantFP::get(GetType<f32>(), 1.0), b);
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FastMathFlags x; x.setAllowReciprocal();
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cast<Instruction>(result)->setFastMathFlags(x);
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SetFpr(op.frd, result);
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//m_ir->CreateStore(GetUndef<bool>(), m_fpscr_fr);
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@ -3757,7 +3772,9 @@ void PPUTranslator::FMUL(ppu_opcode_t op)
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void PPUTranslator::FRSQRTE(ppu_opcode_t op)
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{
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const auto b = GetFpr(op.frb, 32);
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const auto result = Call(GetType<f32>(), m_pure_attr, "__frsqrte", b);
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const auto result = m_ir->CreateFDiv(ConstantFP::get(GetType<f32>(), 1.0), Call(GetType<f32>(), "llvm.sqrt.f32", b));
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FastMathFlags x; x.setAllowReciprocal();
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cast<Instruction>(result)->setFastMathFlags(x);
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SetFpr(op.frd, result);
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//m_ir->CreateStore(GetUndef<bool>(), m_fpscr_fr);
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